diff -r -u -H -N gcc-2.6.3/Makefile.in gcc-i2.6.3/Makefile.in
--- gcc-2.6.3/Makefile.in	Mon Nov 28 18:54:06 1994
+++ gcc-i2.6.3/Makefile.in	Tue Dec 20 16:04:58 1994
@@ -46,7 +46,7 @@
 # to the stage2 and stage3 compilations
 # XCFLAGS is used for most compilations but not when using the GCC just built.
 XCFLAGS =
-CFLAGS = -g
+CFLAGS = -O2
 BOOT_CFLAGS = -O $(CFLAGS)
 # These exists to be overridden by the x-* and t-* files, respectively.
 X_CFLAGS =
diff -r -u -H -N gcc-2.6.3/c-decl.c gcc-i2.6.3/c-decl.c
--- gcc-2.6.3/c-decl.c	Fri Nov 11 17:52:25 1994
+++ gcc-i2.6.3/c-decl.c	Wed Feb 15 22:46:38 1995
@@ -2122,6 +2122,8 @@
 					  ? 0 : DECL_INITIAL (oldglobal));
 		      DECL_SAVED_INSNS (x) = DECL_SAVED_INSNS (oldglobal);
 		      DECL_FRAME_SIZE (x) = DECL_FRAME_SIZE (oldglobal);
+		      /* intel1 */
+		      DECL_FRAME_SIZE (x) = DECL_FRAME_SIZE (oldglobal);
 		      DECL_ARGUMENTS (x) = DECL_ARGUMENTS (oldglobal);
 		      DECL_RESULT (x) = DECL_RESULT (oldglobal);
 		      TREE_ASM_WRITTEN (x) = TREE_ASM_WRITTEN (oldglobal);
diff -r -u -H -N gcc-2.6.3/c-parse.c gcc-i2.6.3/c-parse.c
--- gcc-2.6.3/c-parse.c	Sat Aug 27 13:51:56 1994
+++ gcc-i2.6.3/c-parse.c	Tue Nov  8 15:47:57 1994
@@ -1290,23 +1290,8 @@
 #endif
 
 #line 184 "/usr/local/lib/bison.simple"
-
-/* The user can define YYPARSE_PARAM as the name of an argument to be passed
-   into yyparse.  The argument should have type void *.
-   It should actually point to an object.
-   Grammar actions can access the variable by casting it
-   to the proper pointer type.  */
-
-#ifdef YYPARSE_PARAM
-#define YYPARSE_PARAM_DECL void *YYPARSE_PARAM;
-#else
-#define YYPARSE_PARAM
-#define YYPARSE_PARAM_DECL
-#endif
-
 int
-yyparse(YYPARSE_PARAM)
-     YYPARSE_PARAM_DECL
+yyparse()
 {
   register int yystate;
   register int yyn;
@@ -3335,7 +3320,7 @@
     break;}
 }
    /* the action file gets copied in in place of this dollarsign */
-#line 480 "/usr/local/lib/bison.simple"
+#line 465 "/usr/local/lib/bison.simple"
 
   yyvsp -= yylen;
   yyssp -= yylen;
diff -r -u -H -N gcc-2.6.3/cexp.c gcc-i2.6.3/cexp.c
--- gcc-2.6.3/cexp.c	Fri Sep 23 14:10:27 1994
+++ gcc-i2.6.3/cexp.c	Tue Nov  8 15:47:37 1994
@@ -521,23 +521,8 @@
 #endif
 
 #line 184 "/usr/local/lib/bison.simple"
-
-/* The user can define YYPARSE_PARAM as the name of an argument to be passed
-   into yyparse.  The argument should have type void *.
-   It should actually point to an object.
-   Grammar actions can access the variable by casting it
-   to the proper pointer type.  */
-
-#ifdef YYPARSE_PARAM
-#define YYPARSE_PARAM_DECL void *YYPARSE_PARAM;
-#else
-#define YYPARSE_PARAM
-#define YYPARSE_PARAM_DECL
-#endif
-
 int
-yyparse(YYPARSE_PARAM)
-     YYPARSE_PARAM_DECL
+yyparse()
 {
   register int yystate;
   register int yyn;
@@ -1061,7 +1046,7 @@
     break;}
 }
    /* the action file gets copied in in place of this dollarsign */
-#line 480 "/usr/local/lib/bison.simple"
+#line 465 "/usr/local/lib/bison.simple"
 
   yyvsp -= yylen;
   yyssp -= yylen;
diff -r -u -H -N gcc-2.6.3/combine.c gcc-i2.6.3/combine.c
--- gcc-2.6.3/combine.c	Wed Nov 30 19:13:30 1994
+++ gcc-i2.6.3/combine.c	Wed Feb 15 23:01:12 1995
@@ -96,6 +96,10 @@
 #include "recog.h"
 #include "real.h"
 
+/* intel1 */
+static int in_recombine=0;
+extern FILE *combine_dump_file;
+
 /* It is not safe to use ordinary gen_lowpart in combine.
    Use gen_lowpart_for_combine instead.  See comments there.  */
 #define gen_lowpart dont_use_gen_lowpart_you_dummy
@@ -377,6 +381,29 @@
 
 static int n_occurrences;
 
+/* intel2 - begin */
+
+#define INSN_SETS_REGNO(INSN, REGNO) dead_or_set_regno_p (INSN, REGNO)
+#define INSN_USES_REGNO(INSN, REGNO) refers_to_regno_p (REGNO, \
+							REGNO + 1, \
+                                                        PATTERN (INSN), \
+                                                        0)
+
+/* if this flag is set do not recombine unscheded riscified insns, which their
+ * original insn's destination was a memory.
+ */
+extern int flag_risc_mem_dest;
+
+/* if this flag is set try to riscify stores of CONST_INTs */
+extern int flag_risc_const;
+
+void update_free_regs (rtx);
+static void update_regno_holds_mem (rtx insn, rtx pat);
+static int remove_redundant_store (rtx mem, int block);
+static void update_entries (rtx reg);
+
+/* intel2 - end */
+
 static void init_reg_last_arrays	PROTO(());
 static void setup_incoming_promotions   PROTO(());
 static void set_nonzero_bits_and_sign_copies  PROTO((rtx, rtx));
@@ -436,6 +463,14 @@
 static void distribute_notes	PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
 static void distribute_links	PROTO((rtx));
 static void mark_used_regs_combine PROTO((rtx));
+/* intel2 */
+#if 0
+static void dump_free_registers ();
+#endif
+int find_free_reg();
+static int find_regno_holds_mem (rtx, enum machine_mode);
+/* intel1 */
+static int try_backwards_replace ();
 
 /* Main entry point for combiner.  F is the first insn of the function.
    NREGS is the first unused pseudo-reg number.  */
@@ -867,6 +902,9 @@
 
   /* Don't eliminate a store in the stack pointer.  */
   if (dest == stack_pointer_rtx
+      /* intel1 
+      || (in_recombine && GET_CODE (dest) == REG
+          && reg_used_between_p (dest, insn, i3)) */
       /* If we couldn't eliminate a field assignment, we can't combine.  */
       || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
       /* Don't combine with an insn that sets a register to itself if it has
@@ -1045,6 +1083,8 @@
    On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
    if the destination of a SET is a hard register that isn't a user
    variable.
+   intel2 - This is true unless we are in recombine (indicated by
+   in_recombine)
 
    Before doing the above check, we first try to expand a field assignment
    into a set of logical operations.
@@ -1114,12 +1154,26 @@
 	     CALL operation.  */
 	  || (GET_CODE (inner_dest) == REG
 	      && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
+	      /* intel2 - begin */
+	      /* if we are in the recombine phase, we should not eliminate the
+	       * possibility for combine if the destination is a hard register.
+	       */
+	      && (!in_recombine)
+	      /* intel2 - end */
 	      && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
 					GET_MODE (inner_dest))
 #ifdef SMALL_REGISTER_CLASSES
 		 || (GET_CODE (src) != CALL && ! REG_USERVAR_P (inner_dest))
 #endif
 		  ))
+
+      /* intel2 - begin */
+      /* if we want to leave mem-dest riscified instructions untouched... */
+      || (in_recombine
+		&& flag_risc_mem_dest
+		&& GET_CODE (inner_dest) == MEM)
+      /* intel2 - end */
+
 	  || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
 	return 0;
 
@@ -1372,6 +1426,25 @@
       return 0;
     }
 
+  /* intel1 */
+  if (in_recombine)
+    {
+      if (i1 && GET_CODE (PATTERN (i1)) == SET 
+          && GET_CODE (SET_DEST (PATTERN (i1))) == REG
+          && reg_used_between_p (SET_DEST (PATTERN (i1)), i1, i2))
+        {
+          undo_all ();
+          return 0;
+        }
+      if (i2 && GET_CODE (PATTERN (i2)) == SET 
+          && GET_CODE (SET_DEST (PATTERN (i2))) == REG
+          && reg_used_between_p (SET_DEST (PATTERN (i2)), i2, i3))
+        {
+          undo_all ();
+          return 0;
+        }
+    }
+
   /* Record whether I2DEST is used in I2SRC and similarly for the other
      cases.  Knowing this will help in register status updating below.  */
   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
@@ -1993,6 +2066,46 @@
 	insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
     }
 
+   /* intel1 , maybe we can rearrange memory so it is recognized */
+#ifdef REWRITE_ADDRESS
+   if (insn_code_number==-1 && GET_CODE(newpat)==SET && i1==NULL)
+     {
+       rtx copy_of_newpat,try_to_make_good(); /* see loop.c */
+       rtx new_src_copy,new_dest_copy;
+       int dummy;
+       char * storage;
+       storage = (char *) oballoc(0);
+       copy_of_newpat = copy_rtx (newpat);
+       new_src_copy = SET_SRC (copy_of_newpat);
+       try_to_make_good (SET_SRC (copy_of_newpat));
+       try_to_make_good (SET_DEST (copy_of_newpat));
+       if (recog (copy_of_newpat, i3, &dummy) != -1)
+         {
+           newpat = copy_of_newpat;
+           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
+         }
+       else if (GET_CODE (new_src_copy) != MEM)
+         {
+           new_src_copy = gen_rtx (MEM, GET_MODE( new_src_copy), new_src_copy);
+           try_to_make_good (new_src_copy);
+           SET_SRC (copy_of_newpat) = XEXP (new_src_copy,0);
+           if (recog (copy_of_newpat,i3,&dummy) != -1)
+             {
+               newpat = copy_of_newpat;
+               insn_code_number = recog_for_combine (&newpat,i3,&new_i3_notes);
+             }
+           else
+             {
+               obfree (storage);
+             }
+         }
+       else
+         {
+           obfree (storage);
+         }
+     }
+#endif /* REWRITE_ADDRESS */
+
   /* If it still isn't recognized, fail and change things back the way they
      were.  */
   if ((insn_code_number < 0
@@ -2003,6 +2116,30 @@
       return 0;
     }
 
+ /* intel2 - begin */
+#ifdef REGISTER_CONSTRAINTS
+   /* check if the combined insn is a legal one */
+   if (in_recombine)
+     {
+       register rtx temp_pat = PATTERN (i3);
+       register int temp_code_number = INSN_CODE (i3);
+
+       /* change it only for the following check */
+       PATTERN (i3) = newpat;
+       INSN_CODE (i3) = insn_code_number;
+       insn_extract (i3);
+       /* restore the data */
+       PATTERN (i3) = temp_pat;
+       INSN_CODE (i3) = temp_code_number;
+       if (! constrain_operands (insn_code_number, 1))
+         {
+           undo_all();
+           return 0;
+         }
+     }
+#endif
+ /* intel2 - end */
+
   /* If we had to change another insn, make sure it is valid also.  */
   if (undobuf.other_insn)
     {
@@ -4197,6 +4334,14 @@
       int other_changed = 0;
       enum machine_mode compare_mode = GET_MODE (dest);
 
+    /* intel1 */
+#ifdef HAVE_cc0
+    if(SET_DEST (x) == cc0_rtx && compare_mode==VOIDmode)
+      {
+        compare_mode = GET_MODE (SET_SRC (x));
+      }
+#endif
+
       if (GET_CODE (src) == COMPARE)
 	op0 = XEXP (src, 0), op1 = XEXP (src, 1);
       else
@@ -9712,7 +9857,13 @@
   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
     {
       if (REG_NOTE_KIND (link) == REG_DEAD
-	  && GET_CODE (XEXP (link, 0)) == REG)
+          /* intel2 - begin */
+          /* if in_recombine we might encounter a REG_DEAD note of memory!
+           */
+          && (! in_recombine
+              || GET_CODE (XEXP (link, 0)) == REG)
+          /* intel2 - end */
+      	 )
 	{
 	  int regno = REGNO (XEXP (link, 0));
 	  int endregno
@@ -10544,13 +10695,26 @@
 		      }
 		    else
 		      {
+              /* intel1 making this into reg_unused causes
+                 bug in scheduler since sched will see this
+                 as a reg_dead */
+#if 0
 			PUT_REG_NOTE_KIND (note, REG_UNUSED);
+#endif
 
+#if 0
 			/*  If there isn't already a REG_UNUSED note, put one
 			    here.  */
 			if (! find_regno_note (tem, REG_UNUSED,
 					       REGNO (XEXP (note, 0))))
 			  place = tem;
+#else
+          /*  If there isn't already a REG_DEAD note, put one
+              here.  */
+          if (! find_regno_note (tem, REG_DEAD,
+                         REGNO (XEXP (note, 0))))
+            place = tem;
+#endif
 			break;
 		      }
 		  }
@@ -10817,4 +10981,2580 @@
     (file,
      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
      total_attempts, total_merges, total_extras, total_successes);
+}
+
+/* intel1 */
+/* intel1 - those split insns that remained consecutive should now
+           be combined 
+*/
+void
+combine_unscheded (f, nregs)
+     rtx f;
+     int nregs;
+{
+  register rtx insn, next, prev;
+  register int i;
+  register rtx links, nextlinks, note;
+
+  in_recombine = 1;
+  combine_attempts = 0;
+  combine_merges = 0;
+  combine_extras = 0;
+  combine_successes = 0;
+
+  combine_max_regno = nregs;
+
+  reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
+  reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
+  reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
+  reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
+  reg_last_set_label = (int *) alloca (nregs * sizeof (int));
+  reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
+
+  bzero (reg_last_death, nregs * sizeof (rtx));
+  bzero (reg_last_set, nregs * sizeof (rtx));
+  bzero (reg_last_set_value, nregs * sizeof (rtx));
+  bzero (reg_last_set_table_tick, nregs * sizeof (short));
+  bzero (reg_last_set_invalid, nregs * sizeof (char));
+
+  init_recog_no_volatile ();
+
+  /* Compute maximum uid value so uid_cuid can be allocated.  */
+
+  for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
+    if (INSN_UID (insn) > i)
+      i = INSN_UID (insn);
+
+  uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
+
+  /* Compute the mapping from uids to cuids.
+     Cuids are numbers assigned to insns, like uids,
+     except that cuids increase monotonically through the code. 
+
+     Scan all SETs and see if we can deduce anything about what
+     bits are significant for some registers.  */
+
+  for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
+    {
+      INSN_CUID (insn) = ++i;
+      if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
+	note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
+    }
+
+
+  label_tick = 1;
+  last_call_cuid = 0;
+  mem_last_set = 0;
+  /* Now scan all the insns in forward order.  */
+  for (insn = f; insn; insn = NEXT_INSN (insn))
+    {
+      if (GET_CODE (insn) == CODE_LABEL)
+	label_tick++;
+      if(GET_CODE (insn) == INSN)
+	{
+	  /* Try this insn with each insn it links back to.  */
+	  for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
+	    {
+	      if(REG_NOTE_KIND (links) != REG_DEP_ANTI 
+	         /*&& REG_NOTE_KIND (links) != REG_DEP_OUTPUT 
+	         && */ && (GET_CODE (XEXP (links, 0)) == INSN 
+	              && next_nonnote_insn (XEXP (links, 0))
+	                   == ORG_NEXT_INSN (XEXP (links, 0)))
+	         && GET_CODE (PATTERN (XEXP (links, 0))) == SET
+	         && GET_CODE (SET_DEST (PATTERN (XEXP (links, 0))))
+	              == REG
+	         && (note
+	              = find_regno_note (insn,
+	                                 REG_DEAD,
+	                  REGNO(SET_DEST (PATTERN (XEXP (links, 0))))))
+	         && rtx_equal_p (XEXP (note, 0),
+	                          SET_DEST (PATTERN (XEXP (links, 0))))
+		 /* intel2 - begin */
+		 /* combine only insns that were created by memory_simplify.
+		  */
+		 && (RTX_IS_RISC_P (XEXP (links, 0)))
+		 /* intel2 - end */
+	        )
+	        {
+		  /* intel2 - begin */
+		  rtx inner_link = LOG_LINKS (XEXP (links, 0));
+		  int three_insns = 0;
+
+		  /* Check that we consider the case of three-insns riscified
+		   * insn
+		   */
+		  if (inner_link)
+		    {
+		      for (; inner_link; inner_link = XEXP (inner_link, 1))
+		        {
+		          rtx temp_insn = XEXP (inner_link, 0);
+
+		          if (REG_NOTE_KIND (inner_link) != REG_DEP_ANTI
+		              /*&& REG_NOTE_KIND (inner_link) != REG_DEP_OUTPUT
+		              &&*/ && (GET_CODE (temp_insn) == INSN
+		                  && next_nonnote_insn (temp_insn) ==
+		                  		ORG_NEXT_INSN (temp_insn))
+		              && RTX_IS_RISC_P (temp_insn)
+		              && GET_CODE (PATTERN (temp_insn)) == SET
+		              && GET_CODE (SET_DEST (PATTERN (temp_insn)))
+		                   == REG
+		              && (note
+		                   = find_regno_note (insn,
+		                                      REG_DEAD,
+		                       REGNO(SET_DEST (PATTERN (temp_insn)))))
+		              && rtx_equal_p (XEXP (note, 0),
+		                               SET_DEST (PATTERN (temp_insn)))
+		            )
+		            {
+		              try_combine (insn, XEXP (links, 0), temp_insn);
+		              three_insns = 1;
+		            }
+		        }
+		    }
+
+		  if (! three_insns)
+		    {
+		     /* intel2 - end */
+	             try_combine (insn, XEXP (links, 0), 0);
+	           }
+	        }
+	    }
+	}
+      if(GET_CODE (insn) == INSN ||
+         GET_CODE (insn) == CALL_INSN ||
+         GET_CODE (insn) == JUMP_INSN)
+	  record_dead_and_set_regs (insn);
+    }
+
+  in_recombine = 0;
+
+}
+
+
+
+/* intel2 - begin */
+
+/* we will probably need this - check it and remvoe it if not... */
+
+/*#include "hard-reg-set.h"*/
+
+/* Set of registers that are free and ready to use at this moment.  */
+
+HARD_REG_SET free_regs;
+
+/* Set of registers that are not recommended for allocating at this moment.  */
+
+static HARD_REG_SET not_recommended_regs;
+
+typedef struct {
+  rtx mem;  /* mem rtx, this regno holds */
+  rtx insn_dead;  /* insn in which this regno dies */
+  rtx insn_load;  /* insn in which this regno is loaded */
+  rtx insn_store;  /* insn in which this regno is stored */
+}  MEM_HOLDER;
+
+/* Indexed by regno, indicates which register currently, holds a copy of
+   memory and the rtx represents this memory, as well as the insn loaded it,
+   and the insn in which this register was dead. */
+
+MEM_HOLDER regno_holds_mem[FIRST_PSEUDO_REGISTER];
+/* Perform simplification of memory accessed instructions by replacing them
+   with risc-like instructions.
+   FILE is a file to output debugging information on,
+   or zero if such output is not desired.  */
+
+void
+memory_simplify (file, f)
+     FILE *file;
+     rtx f;
+{
+  register int block, j;
+  int regno, limit;
+  int i; /* intel1 */
+  int nregs; /* intel1 */
+  char * fmt; /* intel1 */
+  MEM_HOLDER *mhp;
+  rtx copy_reg = NULL;
+  rtx t_insn;
+
+  /* record which is the last register used for a spill reload */
+  static int last_load_reg;
+  /* Initialize reg_holds_mem */
+
+  bzero (regno_holds_mem, sizeof regno_holds_mem);
+    
+  /* since all registers now are hard registers, FIRST_PSEUDO_REGISTER is a
+     valid initialization value */
+
+  last_load_reg = FIRST_PSEUDO_REGISTER;
+
+  hard_reg_flow_analysis (f, file, 0 /* no pseudo registers' info. save */ );
+
+  if (n_basic_blocks <= 0)
+    {
+      return ;
+    }
+  /* To determine which registers are live after any insn, start from
+     the beginning of the basic block and scan insns, noting
+     which registers are set by each insn and which die there. */
+  for (block = 0; block < n_basic_blocks; block++)
+    {
+      register rtx insn;
+      int end_of_block_f;
+
+      if (file)
+	fprintf (file, "\nblock number: %d:\n", block);
+
+      last_load_reg = FIRST_PSEUDO_REGISTER;
+      /* since we cannot remove stores before a jump, we clean all the
+         insn_store data */
+
+      for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
+	regno_holds_mem[regno].insn_store = 0;
+
+      for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
+        /* at the beginning of a block, each non-live hard register is
+	   considered free. */
+	{
+	  register int offset = regno / REGSET_ELT_BITS;
+	  register int bit = 1 << (regno % REGSET_ELT_BITS);
+	  if (basic_block_live_at_start[block][offset] & bit)
+	    CLEAR_HARD_REG_BIT (free_regs, regno);
+	  else
+	    SET_HARD_REG_BIT (free_regs, regno);
+        }
+
+      /* Traverse the block, an insn by insn, check for memory references,
+	 and find whether a risc-like insns instead are valid. If yes,
+	 replace the insn by another insn(s). */
+
+      end_of_block_f = 0;	/* signals the end of block reached */
+
+      for (insn = basic_block_head[block];
+	   !end_of_block_f;
+	   insn = NEXT_INSN (insn))
+	{
+	  rtx note, next, mem_opr = 0;
+	  rtx pat = PATTERN (insn);
+	  int regno, old_regno;
+	  int saved_code;
+
+	  /* try to eliminate as much stores as we can using the free_regs
+	     and regno_holds_mem information */
+
+	  if (GET_CODE (insn) == INSN
+	      && GET_CODE (pat) == SET
+	      && GET_CODE (SET_DEST (pat)) == MEM
+	      && GET_CODE (SET_SRC (pat)) == REG
+	      && GET_CODE (XEXP (SET_DEST (pat), 0)) != PRE_DEC
+	      && GET_CODE (XEXP (SET_DEST (pat), 0)) != PRE_INC
+	      && GET_CODE (XEXP (SET_DEST (pat), 0)) != POST_DEC
+	      && GET_CODE (XEXP (SET_DEST (pat), 0)) != POST_INC
+	      && (i = remove_redundant_store (SET_DEST (pat), block))
+	      && file)
+	    fprintf (file,
+	             "insn %d caused a deletion of a redundant store: %d\n",
+	                 INSN_UID (insn),
+	                 i);
+
+	  /* Try to eliminate as much loads as we can using the free_regs
+	     and regno_holds_mem information */
+
+	  else if (GET_CODE (insn) == INSN
+		   && GET_CODE (pat) == SET
+		   && (GET_CODE (SET_DEST (pat)) == REG
+		       || GET_CODE (SET_DEST (pat)) == MEM)
+		   && (GET_CODE (SET_SRC (pat)) == MEM
+		       || (GET_CODE (SET_SRC (pat)) == CONST_INT
+		           && flag_risc_const)))
+	    {
+	      int simple_copy_f = 0;
+	      rtx set_src = SET_SRC (pat);
+	      rtx set_dest = SET_DEST (pat);
+	      enum machine_mode mode = GET_MODE (set_dest);
+
+              if (GET_CODE (SET_DEST (pat)) == REG)
+	        old_regno = REGNO (set_dest);
+	      else
+	        old_regno = FIRST_PSEUDO_REGISTER;
+
+	      if (old_regno != FIRST_PSEUDO_REGISTER
+	          && (next = next_nonnote_insn (insn))
+      	          && GET_RTX_CLASS (GET_CODE (next)) == 'i'
+	          && ((note = find_regno_note (next, REG_DEAD, old_regno))
+	              ||
+	              (GET_CODE (PATTERN (next)) == SET && 
+	               rtx_equal_p (set_dest, SET_DEST (PATTERN (next)))))
+	          /* tevid */
+	          && (note == NULL 
+	              || mode == GET_MODE (XEXP (note, 0))))
+	        {
+		  rtx new_reg = NULL;
+	          rtx old_reg = set_dest; 
+	          int stop_replacement = 0;
+
+	          /* if this load is redundant (i.e. the memory loaded
+	             exists in any register, and the register we're loading
+	             to will die in the next insn), we can replace loaded
+	             register in the next insn with the already loaded register,
+	             and delete this insn.
+	          */
+	          if ((regno = find_regno_holds_mem (set_src, mode))
+	          	 				!= FIRST_PSEUDO_REGISTER
+		       && HARD_REGNO_NREGS (regno, mode) == 1
+		       && regno_holds_mem[regno].insn_load
+#ifdef STACK_REGS
+		       && (STACK_REG_P (old_reg)
+			   || NON_STACK_REG_P (new_reg = gen_rtx (REG,
+			      	     mode,
+			      	     regno)))
+
+#endif
+		       && TEST_HARD_REG_BIT (free_regs, regno))
+		    {
+#ifdef STACK_REGS
+                      if (!new_reg)
+		        new_reg = gen_rtx (REG, mode, regno);
+#endif
+
+		      /* replace this register in the next insn */
+                      init_undo_buf ();
+                      saved_code = INSN_CODE (next);
+		      subst_in_insn (next,
+		      		     PATTERN (next),
+		      		     old_reg,
+		      		     new_reg,
+		      		     0,
+		      		     0);
+		      if (note == NULL)
+		        { /* Then the dest of next must remain old_reg */
+		          SET_DEST (PATTERN (next)) = old_reg;
+		        }
+
+#ifdef REGISTER_CONSTRAINTS
+
+	              INSN_CODE (next) = recog (PATTERN (next), next, 0);
+	              if (INSN_CODE (next) != -1)
+		        insn_extract (next);
+
+		      if (INSN_CODE (next) == -1
+		          || !constrain_operands (INSN_CODE (next), 1))
+		        {
+			  /* restore the previous situation */
+			  loop_undo_all();
+			  INSN_CODE (next) = saved_code;
+		          stop_replacement = 1;
+ 		        }
+#endif
+		      if (!stop_replacement)
+		        {
+			      
+			  if (regno != old_regno)
+			    {
+			      if (note != NULL)
+			        {
+			          /* The regno in the REG_DEAD note should be
+			             also changed */
+
+		                  XEXP (note, 0) = new_reg;
+		          
+		                  /* Now, if we replaced a REG_DEAD note, and
+		                     the new_reg is the destination of the next
+		                     insn, we should remove this note */
+
+		                  if (GET_CODE (SET_DEST (PATTERN (next)))
+		                       == REG
+			              && REGNO (SET_DEST (PATTERN (next)))
+			                   == regno)
+		                    remove_death (regno, next);
+		                }	  
+		              /* replace the registers in the free_register
+		                 list */
+
+		              nregs = HARD_REGNO_NREGS (old_regno, mode);
+		              for (i = 0; i < nregs; i++)
+		                SET_HARD_REG_BIT (free_regs, old_regno + i);
+		              nregs = HARD_REGNO_NREGS (regno, mode);
+		              for (i = 0; i < nregs; i++)
+		                CLEAR_HARD_REG_BIT (free_regs, regno + i);
+		            }  /* if (regno != old_regno) */
+		          else
+		          /* regno == old_regno */
+		            {
+		              /* mark that regno is not free anymore */
+		              nregs = HARD_REGNO_NREGS (regno, mode);
+		              for (i = 0; i < nregs; i++)
+		                CLEAR_HARD_REG_BIT (free_regs, regno + i);
+		            }
+
+		          /* now we can delete this insn ... */
+
+		          if (basic_block_head[block] == insn)
+		            basic_block_head[block] = NEXT_INSN (insn);
+
+			  mhp = &regno_holds_mem[regno];
+                          /* we should reset the RISC flag on the insns
+	                     added for risc, so that they will not be
+			     recombined later */
+
+			  
+			  if (mhp -> insn_dead)
+			    {
+			      t_insn = PREV_INSN (mhp->insn_dead);
+			      while (t_insn && RTX_IS_RISC_P (t_insn))
+			        {
+			          RTX_IS_RISC_P (t_insn) = 0;
+			          t_insn = PREV_INSN (t_insn);
+			        }
+			      remove_death (regno, mhp -> insn_dead);
+			      if (! t_insn)
+			        /* something went wrong */
+			        abort ();
+			    }
+
+		          if (file)
+		            fprintf (file,
+		                     "insn %d: deleted - redundant "
+		                     "load encountered (insn %d)\n",
+		                     INSN_UID (insn),
+		                     INSN_UID (mhp -> insn_load));
+		                
+			  PUT_CODE (insn, NOTE);
+		          NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
+		          NOTE_SOURCE_FILE (insn) = 0;
+
+			  /* ... and start working on the next insn */
+
+		          continue;
+
+		 	}  /* if (!stop_replacement) */
+	              
+		    }  /* if ((regno = find_regno_holds_mem (set_src)) !=
+							   FIRST_PSEUDO_REGISTER
+			           && TEST_HARD_REG_BIT (free_regs, regno)) */
+	             
+		  else if (regno != FIRST_PSEUDO_REGISTER)
+		    /* regno holds the appropriate value but is not free, 
+		       so we can use its contents to
+		       convert this insn to a simple reg to reg copy */
+		    {
+		      copy_reg = gen_rtx (REG, mode, regno);
+#ifdef STACK_REGS
+		      if (GET_CODE (SET_DEST (pat)) != REG
+		          || (STACK_REG_P (SET_DEST (pat))
+                              == STACK_REG_P (copy_reg)))
+#endif
+                        {                  
+		          simple_copy_f = 1;
+		        }
+		    }
+
+	          else if (old_regno == last_load_reg
+			   && (regno =
+			        find_free_reg (GET_MODE (SET_DEST (pat)))) !=
+		               FIRST_PSEUDO_REGISTER
+		           && regno != old_regno)
+	            {
+		      new_reg = gen_rtx (REG, mode, regno);
+
+	              /* replace this insn's register with regno */
+
+	              SET_DEST (pat) = new_reg;
+
+		      /* replace this register in the next insn and its
+		         REG_NOTES */
+		      init_undo_buf ();
+		      saved_code = INSN_CODE (next);
+		      subst_in_insn (next,
+		    		     PATTERN (next),
+		    		     old_reg,
+		    		     new_reg,
+		    		     0,
+		    		     0);
+		      if (note == NULL)
+		       { /* Then the dest of next must remain old_reg */
+		         SET_DEST (PATTERN (next)) = old_reg;
+		       }
+
+#ifdef REGISTER_CONSTRAINTS
+	              if ((INSN_CODE (next) = recog (PATTERN (next),
+							 next,
+							 0)) != -1)
+		        insn_extract (next);
+
+		      if (INSN_CODE (next) == -1
+		          || !constrain_operands (INSN_CODE (next), 1))
+		        {
+			  /* restore the previous situation */
+	                  SET_DEST (pat) = old_reg;
+	                  loop_undo_all ();
+		      	  INSN_CODE (next) = saved_code;
+		          stop_replacement = 1;
+ 		        }
+#endif
+		      if (!stop_replacement)
+		        {
+		          if (note != NULL)
+		            {
+			      /* The regno in the REG_DEAD note should be
+			         changed */
+
+		              XEXP (note, 0) = new_reg;
+		          
+		              /* Now, if we replaced a REG_DEAD note, and the
+		                 new_reg is the destination of the next insn, we
+		                 should remove this note */
+
+		              if (GET_CODE (SET_DEST (PATTERN (next))) == REG
+			          && REGNO (SET_DEST (PATTERN (next))) == regno)
+		                remove_death (regno, next);
+			    }
+		          /* replace the registers in the free_register
+		             list */
+
+		          nregs = HARD_REGNO_NREGS (regno, mode);
+		          for (i = 0; i < nregs; i++)
+		            CLEAR_HARD_REG_BIT (free_regs, regno + i);
+		          nregs = HARD_REGNO_NREGS (old_regno, mode);
+		          for (i = 0; i < nregs; i++)
+		            SET_HARD_REG_BIT (free_regs, old_regno + i);
+
+		          /* replace relevant data in regno_holds_mem */
+		          regno_holds_mem[regno].mem = set_src;
+		          regno_holds_mem[regno].insn_load = insn;
+		          regno_holds_mem[regno].insn_dead = next;
+
+		          if (file)
+		            fprintf (file, 
+		            "insn %d: replacing reload register %d with register %d\n",
+			    INSN_UID (insn), old_regno, regno);
+		 	}  /* if (!stop_replacement) */
+	              
+	            }  /* else if (old_regno == last_load_reg
+			       && (regno =
+				  find_free_reg (GET_MODE (set_dest))) !=
+							  FIRST_PSEUDO_REGISTER)
+			   */
+
+		  else if (old_regno == last_load_reg
+			   && file)
+		    fprintf (file,
+			     "insn %d: no free register found for reload."
+		             "\n", 
+			     INSN_UID (insn));
+
+	        }  /* if ((next = next_nonnote_insn (insn))
+      	                && GET_RTX_CLASS (GET_CODE (next)) == 'i'
+	                && (note = find_regno_note (next, REG_DEAD, old_regno)))
+	               */
+
+	      else if ((regno = find_regno_holds_mem (set_src, mode)) 
+	                != FIRST_PSEUDO_REGISTER
+		        && HARD_REGNO_NREGS (regno, mode) == 1)
+		{
+		  copy_reg = gen_rtx (REG, mode, regno);
+#ifdef STACK_REGS
+		  if (GET_CODE (set_dest) != REG
+		      || (STACK_REG_P (set_dest) == STACK_REG_P (copy_reg)))
+#endif
+                    simple_copy_f = 1;
+	        }
+
+	      if (simple_copy_f)
+		{
+		  MEM_HOLDER *mhp_org;
+		  rtx mem;
+		        
+		  /* we can change this insn to a simple reg copy, instead
+		     of a load or store */
+
+		  mem = SET_SRC (pat);
+		  if (copy_reg == NULL)
+		    {
+		      copy_reg = gen_rtx (REG, mode, regno);
+		    }
+
+		  saved_code = INSN_CODE (insn);
+		  SET_SRC (pat) = copy_reg;
+
+#ifdef REGISTER_CONSTRAINTS
+	          if ((INSN_CODE (insn) = recog (PATTERN (insn),
+						 insn,
+						 0)) != -1)
+		    insn_extract (insn);
+
+		  if (INSN_CODE (insn) == -1
+		      || !constrain_operands (INSN_CODE (insn), 1))
+		    {
+		      SET_SRC (pat) = mem;
+		      INSN_CODE (insn) = saved_code;
+		    }
+		  else
+		    {
+#endif
+
+		      /* now we should eliminate the possibility of the risc
+		         sequence loaded the memory int regno, to be later
+		         recombined */
+
+		      mhp_org = &regno_holds_mem[regno];
+		      mhp = &regno_holds_mem[old_regno];
+		      if (mhp_org -> insn_load)
+			{
+		          /* we should reset the RISC flag on the insns
+		             added for risc, so that they will not be
+		             recombined later */
+
+
+			  if (mhp_org -> insn_dead)
+			    {
+			      t_insn = PREV_INSN (mhp_org->insn_dead);
+			      while (t_insn  && RTX_IS_RISC_P (t_insn))
+			        {
+			          RTX_IS_RISC_P (t_insn) = 0;
+			          t_insn = PREV_INSN (t_insn);
+			        }
+			      if (! t_insn)
+			        fprintf (stderr,
+			                 "Not encountered insn_dead\n");
+			      remove_death (regno, mhp_org -> insn_dead);
+			    }
+			}  /* if (mhp_org -> insn_load) */
+
+		      /* we should update old_regno entries in
+			 regno_holds_mem array */
+
+		      mhp -> mem = mhp_org -> mem;
+		      mhp -> insn_load = insn;
+			  
+		      if (file)
+		        fprintf (file,
+		                 "insn %d: mem source replaced with reg\n",
+		                 INSN_UID (insn));
+
+#ifdef REGISTER_CONSTRAINTS
+		    }  /* else of if (INSN_CODE (insn) == -1
+		                   || !constrain_operands (INSN_CODE (insn), 1))
+		       */
+#endif
+		}  /* if (simple_copy_f) */
+
+              if (GET_CODE (pat) == SET 
+                  && GET_CODE (SET_DEST (pat)) == REG)
+	        last_load_reg = REGNO (SET_DEST (pat));
+
+	    }  /* if (GET_CODE (insn) == INSN
+	                  && GET_CODE (pat) == SET
+	                  && GET_CODE (SET_DEST (pat)) == REG
+	                  && GET_CODE (SET_SRC (pat)) == MEM) */
+
+	  /* mark all the original insns (those not created here). Since
+	     we use here the same bit as RTX_IS_SPILL_P, we should do this
+	     after checking for the spill reload register substitution. */
+	  RTX_IS_RISC_P (insn) = 0;
+
+	  end_of_block_f = (insn == basic_block_end[block]);
+	  if (!INSN_UID (insn))
+	    fatal ("\nMemory simplify: Scanning illegal insn.");
+
+	  if (GET_CODE (insn) == INSN)
+	    {
+	      register rtx note;
+
+	      if (GET_CODE (pat) == SET)
+		{
+		  rtx prev_insn, next_insn;
+		  rtx insn_src = SET_SRC (pat);
+		  rtx insn_dest = SET_DEST (pat);
+		  int mem_opr_is_src = 0;
+
+		  /* indicates which of the two SET_SRC's arguments is a
+		     memory reference. 0 - indicates the first one and 1 -
+		     the second */
+		         
+		  int mem_loc;
+
+		  switch (GET_CODE (insn_src))
+		    {
+		      case CONST_INT:
+		        if (flag_risc_const
+		            && GET_CODE (insn_dest) == MEM
+		            && !push_operand (insn_dest, 
+		                                 GET_MODE (insn_dest)))
+			  {
+			    mem_opr = insn_src;
+			    mem_loc = 1;
+                            mem_opr_is_src = 1;
+			    /* this is a trick to make the code replacing
+			       the memory operand in any other insn, valid
+			       even here.
+			       Note that insn_src now is actually the
+			       insn's pattern, and not the SET_SRC of it. */
+			    insn_src = pat;
+			  }
+                        break;
+		      case REG:
+		      case SYMBOL_REF:
+			/* do nothing, this is a simple copy */
+			break;
+		      case MEM:
+			if (GET_CODE (insn_dest) == CC0)
+			  /* this insn is not a simple load */
+			  {
+			    mem_opr = insn_src;
+			    mem_loc = 1;
+
+                            mem_opr_is_src = 1;
+			    /* this is a trick to make the code replacing
+			       the memory operand in any other insn, valid
+			       even here.
+			       Note that insn_src now is actually the
+			       insn's pattern, and not the SET_SRC of it. */
+			    insn_src = pat;
+			  }
+			break;
+		      default:
+		        if (GET_CODE (insn_src) == SIGN_EXTRACT
+		            || GET_CODE (insn_src) == ZERO_EXTRACT)
+		          { /* These cannot be handled properly */
+		            break;
+		          }
+			fmt = GET_RTX_FORMAT (GET_CODE (insn_src));
+			if (GET_CODE (XEXP (insn_src, 0)) == MEM)
+			  {
+			    mem_loc = 0;
+			    mem_opr = XEXP (insn_src, 0);
+			  }
+			else if (GET_RTX_LENGTH (GET_CODE (insn_src)) > 1
+				 && fmt[1] == 'e'
+				 && GET_CODE (XEXP (insn_src, 1)) == MEM)
+			  {
+			    mem_loc = 1;
+			    mem_opr = XEXP (insn_src, 1);
+			  }
+			break;
+		    }	/* switch (GET_CODE(insn_src)) */
+
+		  if (mem_opr)
+		    /* we found a memory operand that we should replace */
+		    {
+		      int skip_load_f = 0;  /* should we skip mem load? */
+		      int regno_is_free = 0; /* was it allocated by find_free_reg */
+		      int memory_dest_changed  
+			      		 = GET_CODE (insn_dest) == MEM
+			      		    && rtx_equal_p (insn_dest, mem_opr);
+		      enum machine_mode mode = GET_MODE (mem_opr);
+
+                      if (GET_CODE (mem_opr) == CONST_INT)
+                        mode = GET_MODE (insn_dest);
+		      if ((regno = find_regno_holds_mem (mem_opr, mode)) 
+		           != FIRST_PSEUDO_REGISTER)
+			{
+			  if (HARD_REGNO_NREGS (regno, mode) == 1
+			      && TEST_HARD_REG_BIT (free_regs, regno))
+			    skip_load_f = 1;
+			  else
+			    regno = FIRST_PSEUDO_REGISTER;
+			}
+                      if (regno == FIRST_PSEUDO_REGISTER
+#ifdef IS_RISC_MODE
+		          && (IS_RISC_MODE (GET_MODE (mem_opr))
+		              || GET_CODE (mem_opr) == CONST_INT)
+#endif
+                         )
+                        { /* Look forward a few insns to see
+                             if this mem_opr will be loaded
+                             into a register and if it is then
+                             try to use that register for riscifying.  */
+                          t_insn = next_nonnote_insn (insn);
+                          while (t_insn && regno == FIRST_PSEUDO_REGISTER)
+                            {
+                              if (GET_CODE (t_insn) == CODE_LABEL
+                                  || GET_CODE (t_insn) == CALL_INSN)
+                                {
+                                  break;
+                                }
+                              if (GET_CODE (t_insn) == INSN)
+                                {
+                                  register rtx dest;
+                                  
+                                  if (GET_CODE (PATTERN (t_insn)) != SET)
+                                    {
+                                      break;
+                                    }
+                                  dest = SET_DEST (PATTERN (t_insn));
+                                  if (GET_CODE (dest) == REG
+                                      && rtx_equal_p (mem_opr,
+                                          SET_SRC (PATTERN (t_insn))))
+                                    {
+                                      regno = REGNO (dest);
+			              nregs = HARD_REGNO_NREGS (regno, mode);
+			              if (HARD_REGNO_MODE_OK (regno, mode))
+			                {
+			                  for (i = 0; i < nregs; i++)
+			                    if (! TEST_HARD_REG_BIT (free_regs,
+			            			          regno + i))
+			                      {
+			                        regno = FIRST_PSEUDO_REGISTER;
+			                        break;
+			                      }
+			                }
+			              else
+			                regno = FIRST_PSEUDO_REGISTER;
+                                    }
+                                  else if (GET_CODE (dest) == MEM
+                                           && ! push_operand (dest,
+                                           		      GET_MODE (dest)))
+                                    /* since there is a write to memory, no use
+                                       in trying to load something that might be
+                                       clobbered. */
+			            regno = FIRST_PSEUDO_REGISTER;
+                                }
+                              t_insn = next_nonnote_insn (t_insn);
+                            }
+                                     
+                        }
+                      if (regno == FIRST_PSEUDO_REGISTER
+			  && GET_CODE (insn_dest) == REG
+#ifdef IS_RISC_MODE
+		          && (IS_RISC_MODE (GET_MODE (mem_opr))
+		              || GET_CODE (mem_opr) == CONST_INT)
+#endif
+                         )
+			{
+			  regno = REGNO (insn_dest);
+			  nregs = HARD_REGNO_NREGS (regno, mode);
+
+			  if (HARD_REGNO_MODE_OK (regno, mode))
+			    {
+			      for (i = 0; i < nregs; i++)
+			        if (! TEST_HARD_REG_BIT (free_regs,
+			        			 regno + i))
+			          {
+			            regno = FIRST_PSEUDO_REGISTER;
+			            break;
+			          }
+			    }
+			  else
+			    regno = FIRST_PSEUDO_REGISTER;
+			}
+
+	              if (regno == FIRST_PSEUDO_REGISTER
+#ifdef IS_RISC_MODE
+		          && (IS_RISC_MODE (GET_MODE (mem_opr))
+		              || GET_CODE (mem_opr) == CONST_INT)
+#endif
+                         )
+			{
+			  prev_insn = prev_nonnote_insn (insn);
+			  next_insn = next_nonnote_insn (insn);
+
+			  /* update set of not recommended hard registers
+			     for find_free_reg () */
+			  /* NOTE that we can refer only to integer
+			     registers, but now we do it more general. */
+
+			  for (regno = 0;
+			       regno < FIRST_PSEUDO_REGISTER;
+			       regno++)
+
+			    if ((prev_insn
+			         && GET_RTX_CLASS (GET_CODE (prev_insn))
+						  == 'i'
+			         && (INSN_USES_REGNO (prev_insn, regno)
+				     || INSN_SETS_REGNO (prev_insn, regno)))
+				     || (next_insn
+				        && GET_RTX_CLASS (GET_CODE (next_insn))
+									  == 'i'
+				 && (INSN_USES_REGNO (next_insn, regno)
+			         /* If the destination is MEM we
+			            might write the new register
+			            contents to the memory as the
+			            last insn. This will force us to
+			            also consider a write to the
+			            allocated register in the next
+			            insn. */
+
+				  || (memory_dest_changed
+				      && INSN_SETS_REGNO (next_insn,
+				                          regno)))))
+			      SET_HARD_REG_BIT (not_recommended_regs,regno);
+			    else
+			      CLEAR_HARD_REG_BIT (not_recommended_regs,
+			      		      regno);
+
+			  regno = find_free_reg (mode);
+			  regno_is_free = 1;
+			}
+
+	              if (regno != FIRST_PSEUDO_REGISTER)
+			{
+			  rtx new_insn, new_reg, link;
+
+			  /* before changing the insn, and adding others, we
+			     check the changed insn will be legal. */
+
+			  new_reg = gen_rtx (REG, mode, regno);
+			  saved_code = INSN_CODE (insn);
+			  if (mem_opr_is_src)
+			    {
+			      SET_SRC (pat) = new_reg;
+			    }
+			  else
+			    {
+                              init_undo_buf ();
+			      subst_in_insn (insn, pat, mem_opr, new_reg, 0, 0);
+			    }
+			      
+#ifdef REGISTER_CONSTRAINTS
+			  /* now check if the insn's O.K. */
+
+			  INSN_CODE (insn) = recog (pat, insn, 0);
+
+			  if (INSN_CODE (insn) != -1)
+			    insn_extract (insn);
+
+			  if (INSN_CODE (insn) == -1
+			      || ! constrain_operands (INSN_CODE (insn), 1))
+		            {
+			      if (mem_opr_is_src)
+			        {
+			          SET_SRC (pat) = mem_opr;
+			        }
+			      else
+			        {
+			          loop_undo_all ();
+			        }
+			      INSN_CODE (insn) = saved_code;
+			    }
+			  else  /* the replacement is valid */
+			    {
+#endif
+			      if (! skip_load_f)
+			        {
+
+			          if (mode != SImode && regno_is_free
+			              && GET_CODE (mem_opr) == CONST_INT)
+			            {
+			              new_reg = gen_rtx (REG, SImode, regno);
+			            }
+			          /* load the memory into regno */
+			          new_insn 
+			           = make_insn_raw (gen_rtx (SET,
+							     VOIDmode,
+							     new_reg,
+							      mem_opr));
+
+				  RTX_IS_RISC_P (new_insn) = 1;
+			          add_insn_after (new_insn,
+						  PREV_INSN (insn));
+
+				  /* record regno as the last register that
+				    is used for loading */
+			      
+				  last_load_reg = regno;
+
+
+				  /* update new data in regno_holds_mem[] */
+				      
+#if 0
+				  mhp = &regno_holds_mem[regno];
+				  mhp -> insn_load = new_insn;
+#endif
+				  update_regno_holds_mem(new_insn,
+				    	     PATTERN(new_insn));
+				      
+				  /* if insn was the first insn in this
+				     block this should be updated */
+
+				  if (basic_block_head[block] == insn)
+				    basic_block_head[block] = new_insn;
+
+				  if (file)
+				    {
+					fprintf (file, "insn %d was added ",
+						   INSN_UID (new_insn));
+					fprintf (file, "before insn %d\n",
+						       INSN_UID (insn));
+				    }
+
+				  /* move the insn's LOG_LINKS to new_insn */
+				  LOG_LINKS (new_insn) = LOG_LINKS (insn);
+				  LOG_LINKS (insn) = 0;
+
+				  /* move all relevant REG_DEAD notes to
+				     new_insn */
+				  for (note = REG_NOTES (insn);
+				       note;
+				       note = XEXP (note, 1))
+				    {
+				      if (REG_NOTE_KIND (note) == REG_DEAD)
+					{
+					  register int regno 
+					    = REGNO (XEXP (note, 0));
+
+					  if (GET_RTX_LENGTH (
+					  	GET_CODE (insn_src)) < 2
+					        || GET_CODE (XEXP (insn_src,
+					      	     1 - mem_loc))
+					      	     != REG
+					       || REGNO (XEXP (insn_src,
+							 1 - mem_loc))
+							!= regno)
+					    {
+					          
+					      /* this note does not refer to
+					         the register that will be
+					         used from now on within
+					         insn, thus we move it to
+					        new_insn. */
+
+					      remove_note (insn, note);
+					      mhp = &regno_holds_mem[regno];
+					      REG_NOTES (new_insn) =
+					      gen_rtx (EXPR_LIST,
+							REG_DEAD,
+							XEXP (note, 0),
+							REG_NOTES(new_insn));
+					      mhp -> insn_dead = new_insn;
+
+					      SET_HARD_REG_BIT
+						       (free_regs,
+						        REGNO (XEXP (note, 0)));
+					    }
+					}  /* if (REG_NOTE_KIND (note) == REG_DEAD) */
+				    }  /* for (note = REG_NOTES (insn);
+					           note;
+					           note = XEXP (note, 1)) */
+				}  /* if (! skip_load_f) */
+		              else
+				/* we use an already loaded register */
+				{
+
+				  /* since we use a load for a possibly 
+				     previously riscified insn, we should
+				     unmark the insns created for that insn,
+				     so that recombine will not try to
+				     delete its load */
+				  mhp = &regno_holds_mem[regno];
+				  if (mhp -> insn_dead)
+				    {
+				      /* we should reset the RISC flag on
+				         the insns added for risc, so that
+				         they will not be recombined later
+				      */
+
+				      t_insn = PREV_INSN (mhp -> insn_dead);
+				      while (t_insn && RTX_IS_RISC_P (t_insn))
+					{
+					   RTX_IS_RISC_P (t_insn) = 0;
+					   t_insn = PREV_INSN (t_insn);
+					}
+			              remove_death (regno, mhp->insn_dead);
+			            }  /* if (mhp -> insn_load) */
+
+				  if (file)
+				    {
+				      fprintf (file, "insn %d: changed mem ",
+							   INSN_UID (insn));
+				      fprintf (file, "operand with already "
+							   "loaded register %d\n",
+							   regno);
+				    }
+				}
+
+		              /* in the case the memory operand was also the
+				 insn's destination, we should add an insn
+				 to store the result, now stored in
+				 new_reg. */
+
+		              if (memory_dest_changed)
+			        {
+			          /* Since memory destination was replaced by
+			             a register, its contents is clobbered */
+
+#if 0
+				  regno_holds_mem[regno].mem = 0;
+#endif
+				  bzero (&regno_holds_mem[regno],
+				         sizeof (MEM_HOLDER));
+				  update_entries (new_reg);
+
+				  new_insn = make_insn_raw (pat);
+
+				  RTX_IS_RISC_P (new_insn) = 1;
+				  add_insn_after (new_insn,
+					          PREV_INSN (insn));
+
+				  if (skip_load_f
+				      && basic_block_head[block] == insn)
+				    basic_block_head[block] = new_insn;
+
+				  if (file
+				      && ! skip_load_f)
+				    {
+				      fprintf (file, "insn %d was also ",
+					       INSN_UID (new_insn));
+				      fprintf (file, "added before insn ");
+				      fprintf (file, "%d\n",
+					  		INSN_UID (insn));
+				    }
+				  else if (file)
+				    {
+				    fprintf (file,
+				             "insn %d was added before "
+				             "insn %d, load was saved\n",
+				             INSN_UID (new_insn),
+				             INSN_UID (insn));
+				   }
+
+
+				  /* change insn to be just a store insn */
+				  PATTERN (insn) = gen_rtx (SET,
+								VOIDmode,
+								mem_opr,
+								new_reg);
+
+				  /* now we might find that a previous
+				     store is redundant... */
+				  if ((i = remove_redundant_store (mem_opr,
+								   block))
+				       && file)
+				    {
+				    fprintf (file,
+				             "insn %d: caused deletion of "
+				             "a redundant store: %d\n",
+				             INSN_UID (insn),
+				             i);
+				    }
+
+				  /* now we actually changed the insn's
+				     code, so we erase the current one and
+				     we let next phases (probably sched2) to
+				     update this code. */
+
+				  INSN_CODE (insn) = -1;
+
+				  if (! skip_load_f)
+				    {
+				      /* add the last_new_insn to the new_insn's
+					 dependency list */
+
+				      link = rtx_alloc (INSN_LIST);
+				      PUT_REG_NOTE_KIND (link, 0);
+				      XEXP (link, 0) = PREV_INSN (new_insn);
+				      XEXP (link, 1) = LOG_LINKS (new_insn);
+				      LOG_LINKS (new_insn) = link;
+				    }
+				}	/* if (memory_dest_changed) */
+
+		              /* add the new_insn to the insn's dependency
+				 list */
+
+		              if (! skip_load_f
+				  || memory_dest_changed)
+				{
+				  link = rtx_alloc (INSN_LIST);
+				  PUT_REG_NOTE_KIND (link, 0);
+				  XEXP (link, 0) = new_insn;
+				  XEXP (link, 1) = LOG_LINKS (insn);
+				  LOG_LINKS (insn) = link;
+				}
+
+				  /* Add a REG_DEAD note to the last insn to
+				     indicate that the used register is no
+				     longer needed.
+				     This is not needed for this phase since we
+				     do not remove this register from the free
+				     register list (we just mark it to indicate
+				     that next allocation of free register, will
+				     not return it again, so that dependency
+				     between adjacent insns will be as less as
+				     possible). */
+
+			      if (GET_CODE (insn_dest) != REG
+				  || REGNO (insn_dest) != REGNO (new_reg))
+		              {
+				REG_NOTES (insn) 
+				  = gen_rtx (EXPR_LIST,
+					     REG_DEAD,
+					     new_reg, 
+					     REG_NOTES (insn));
+		              }
+#ifdef REGISTER_CONSTRAINTS
+		            }  /* the replacement is valid */
+#endif
+			}  /* if (regno != FIRST_PSEUDO_REGISTER) */
+		      else if (file)
+			{
+			        fprintf (file, "insn %d: No suitable free hard",
+			      				       INSN_UID (insn));
+			        fprintf (file, " register found for risc\n");
+			}
+		    }  /* if (mem_opr) */
+		}  /* if (GET_CODE (pat) == SET) */
+            }  /* if (GET_CODE(insn) == INSN) */
+
+	  if (GET_CODE (insn) == CODE_LABEL)
+	    bzero (regno_holds_mem, sizeof regno_holds_mem);
+
+	  if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
+	    {
+
+	      if (GET_CODE (insn) == CALL_INSN)
+	        {
+		   /* all call clobbered registers are now free */
+
+		   for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
+		     if (call_used_regs[j])
+		          SET_HARD_REG_BIT (free_regs, j);
+	        }
+
+	      update_free_regs (PATTERN (insn));
+
+	      update_regno_holds_mem (insn, PATTERN (insn));
+
+	      /* add each dead register to the free_regs set */
+	      /* mark each dead regno in the regno_holds_mem array */
+	      for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
+	        {
+		  if ((REG_NOTE_KIND (note) == REG_DEAD
+		       || REG_NOTE_KIND (note) == REG_UNUSED)
+		      && GET_CODE (XEXP (note, 0)) == REG)
+		    {
+		      regno = REGNO (XEXP (note, 0));
+		      nregs = 
+		        HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
+  
+		      for (i = 0; i < nregs; i++)
+		        SET_HARD_REG_BIT (free_regs, regno + i);
+		      regno_holds_mem[regno].insn_dead = insn;
+		    }
+		}
+	      if ((note = find_reg_note (insn, REG_WAS_0, 0)))
+	        {
+	          rtx set;
+	          set = single_set (insn);
+	          if (set == NULL 
+		      || GET_CODE (SET_DEST (set)) == REG)
+	            { /* Since reg may have been reused.  */
+		      remove_note (insn, note);
+	            }
+	        }
+	    }  /* if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') */
+	}  /* for (insn = basic_block_head[block]; */
+    }  /* for (block = 0; block < n_basic_blocks; block++) */
+
+    /* mark each insn with it's next nonnote insn so that recombine can work */
+    {
+
+      t_insn = f;
+      while (t_insn)
+        {
+          if (GET_CODE (t_insn) == INSN)
+            ORG_NEXT_INSN (t_insn) = next_nonnote_insn (t_insn);
+          t_insn = NEXT_INSN (t_insn);
+        }
+    }
+}				/* memory_simplify (file, f) */
+
+
+static void
+dump_free_registers (file)
+     FILE *file;
+{
+  register int regno;
+
+  fprintf (file, "Free registers now are: ");
+  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
+    if (TEST_HARD_REG_BIT (free_regs, regno))
+      {
+	fprintf (file, " %d", regno);
+      }
+  fprintf (file, "\n");
+}
+
+/*  Finds a free register that is able to contain a value of mode MODE.
+ *  Returns the number of the hard register (or the first hard register, in
+ *  case of multi-register value) found, if such exists, and mark it in the
+ *  regs_ever_live array. Otherwise returns  FIRST_PSEUDO_REGISTER.
+ */
+
+int
+find_free_reg (mode)
+     enum machine_mode mode;
+{
+  register int regno;
+
+  /* record last_reg retunrned. Try next find form this reg on. */
+  static int last_reg;
+
+  int not_desired;		/* is this the "not-desired" regset: i.e. are we going to
+            * take the register from those who are not "safe" within
+            * a function (their values is promised not to be altered).
+            */
+  int second_half;		/* is this the second half of the "round-robin" search */
+
+#ifdef IS_RISC_MODE
+  if (!IS_RISC_MODE (mode))
+    {
+      return (FIRST_PSEUDO_REGISTER);
+    }
+#endif
+  /* we handle only DImode SImode, HImode and QImode */
+  switch (mode)
+    {
+    case DImode:
+    case SImode:
+    case HImode:
+    case QImode:
+
+      /* Try to find the register among those whos value is not "safe"
+       * first.
+       */
+      for (not_desired = 0; not_desired < 2; not_desired++)
+	{
+	  int last_reg_scanned = 0;
+
+	  /* implement a "round-robin" algorithm for register scanning.
+	     fisrt look from the last_reg and on, and then from 0 to
+	     last_reg. */
+	     
+	  for (regno = (last_reg + 1) % FIRST_PSEUDO_REGISTER;
+	       ! last_reg_scanned;
+	       regno = (regno + 1) % FIRST_PSEUDO_REGISTER)
+	    {
+	      register int i, nregs = HARD_REGNO_NREGS (regno, mode);
+	      register int found = 1;
+
+	      last_reg_scanned = last_reg == regno;
+	      for (i = 0; i < nregs; i++)
+	        {
+	          if (! not_desired
+		      && (! call_used_regs[regno + i]
+			  || TEST_HARD_REG_BIT (not_recommended_regs,
+			  			regno + i)))
+		    found = 0;
+	          else if (! fixed_regs[regno + i]
+	            	   && TEST_HARD_REG_BIT (free_regs, regno + i)
+	            	   && HARD_REGNO_MODE_OK (regno + i, mode)
+#ifdef ELIMINABLE_REGS
+			   && (! frame_pointer_needed
+			       || regno != FRAME_POINTER_REGNUM)
+#endif
+			   /* allow only registers that lived before this
+			      phase to take part. This might reduce the number
+			      of registers available, but otherwise some
+			      problems may occur due to use of a register that
+			      need to be pushed at the the function prologue,
+			      thus corrupting the calculations of stack slots
+			      previously performed at the reload phase. */
+			   && (call_used_regs[regno + i]
+			       || regs_ever_live[regno + i])
+			  )
+		    continue;
+		  else
+			found = 0;
+		}  /* for (i = 0; i < nregs; i++) */
+	      if (found)
+		{
+		  /* save regno for the next invokation */
+		  last_reg = regno + nregs - 1;
+
+		  return (regno);
+		}
+	    } /* for (regno = (last_reg + 1) % FIRST_PSEUDO_REG;
+	         regno != last_reg;
+	         regno = (regno + 1) % FIRST_PSEUDO_REG) */
+	}  /* for (not_desired = 0; not_desired < 2; not_desired ++) */
+      break;
+    }  /* switch (mode) */
+  return (FIRST_PSEUDO_REGISTER);
+}
+
+/* Updates the free_regs regset according the contents of PAT */
+
+void
+update_free_regs (rtx pat)
+{
+  register int i, regno, nregs;
+  register j;
+  register char *fmt;
+  register RTX_CODE code = GET_CODE (pat);
+
+  switch (code)
+    {
+      case SET:
+      case USE:
+      case CLOBBER:
+        if (GET_CODE (SET_DEST (pat)) == REG)
+          {
+            regno = REGNO (SET_DEST (pat));
+            nregs = HARD_REGNO_NREGS (regno,
+            					   GET_MODE (SET_DEST (pat)));
+
+            if (GET_CODE (pat) == SET
+                || GET_CODE (pat) == USE)
+              for (i = 0; i < nregs; i++)
+                CLEAR_HARD_REG_BIT (free_regs, regno + i);
+#if 0
+            else /* GET_CODE (pat) == CLOBBER */
+              for (i = 0; i < nregs; i++)
+                SET_HARD_REG_BIT (free_regs, regno + i);
+#endif
+          }
+        else if (GET_CODE (SET_DEST (pat)) == SUBREG
+                 && GET_CODE (SUBREG_REG (SET_DEST (pat))) == REG)
+          {
+            regno = REGNO (SUBREG_REG (SET_DEST (pat))) 
+                         + SUBREG_WORD (SET_DEST (pat));
+            nregs = HARD_REGNO_NREGS (regno,
+            					   GET_MODE (SET_DEST (pat)));
+
+            if (GET_CODE (pat) == SET
+                || GET_CODE (pat) == USE)
+              for (i = 0; i < nregs; i++)
+                CLEAR_HARD_REG_BIT (free_regs, regno + i);
+          }
+        break;
+      case ADDR_VEC:
+      case CALL:
+      case HIGH:
+      case CONST_INT:
+      case CONST:
+      case CONST_DOUBLE:
+      case SYMBOL_REF:
+      case LABEL_REF:
+      case PC:
+      case CC0:
+      case REG:
+        /* do nothing */
+        return;
+   }  /* switch (GET_CODE (pat)) */
+
+  fmt = GET_RTX_FORMAT (code);
+  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+    if (fmt[i] == 'e')
+      {
+        if( XEXP (pat, i))
+          update_free_regs (XEXP (pat, i));
+      }
+    else if (fmt[i] == 'E' || fmt[i] == 'V')
+      {
+	for (j = 0; j < XVECLEN (pat, i); j++)
+	  update_free_regs (XVECEXP (pat, i, j));
+      }
+}
+
+#if 0
+/* Returns a hard register regno, if the contents of entry regno in
+   last_reloads array equals to MEM, FIRST_PSEUDO_REGISTER otherwise. */
+
+static int
+find_last_reload (rtx mem)
+{
+  register int regno;
+  
+  if (GET_CODE (mem) != MEM)
+    abort ();
+
+  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
+    if (rtx_equal_p (LAST_RELOAD (regno), mem))
+      return (regno);
+
+  return (FIRST_PSEUDO_REGISTER);
+}
+#endif
+
+/* Returns regno of a free register holding MEM, or FIRST_PSEUDO_REGISTER if
+   not exist such register. */
+
+static int
+find_regno_holds_mem (rtx mem, enum machine_mode mode)
+{
+  int i, is_const;
+  MEM_HOLDER *mhp;
+
+  is_const = GET_CODE (mem) == CONST_INT;
+  
+  for (mhp = regno_holds_mem;
+       mhp < regno_holds_mem + FIRST_PSEUDO_REGISTER;
+       mhp++)
+    {
+      if (mhp->mem && GET_CODE (mhp->insn_load) == NOTE)
+        { /* was deleted */
+          mhp->insn_load = NULL;
+          mhp->mem = NULL;
+          mhp->insn_dead = NULL;
+        }
+      if (mhp->insn_store && GET_CODE (mhp->insn_store) == NOTE)
+        { /* was deleted */
+          mhp->insn_store = NULL;
+        }
+#if 0
+      if ((mhp->insn_load 
+           && mhp->mem
+#endif
+      if ((mhp->mem
+           && GET_CODE (mhp -> mem) == GET_CODE (mem)
+           && (is_const 
+                ? rtx_equal_p ( (mhp -> mem), (mem))
+                : rtx_equal_p (XEXP (mhp -> mem, 0), XEXP (mem, 0)))
+           && HARD_REGNO_MODE_OK (mhp - regno_holds_mem, mode)
+           && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (mhp -> insn_load))))
+               >= GET_MODE_SIZE (mode))
+	  || (mhp -> mem
+	      && mhp -> insn_store
+              && GET_MODE_SIZE (GET_MODE (SET_SRC (PATTERN (mhp -> insn_store))))
+                   >= GET_MODE_SIZE (mode)
+              && GET_CODE (SET_DEST ( PATTERN (mhp -> insn_store))) 
+                   == GET_CODE (mem)
+              && HARD_REGNO_MODE_OK (mhp - regno_holds_mem, mode)
+              && (is_const
+                  ? rtx_equal_p (SET_DEST ( PATTERN (mhp -> insn_store)), 
+                                 mem)
+                  : rtx_equal_p (XEXP (SET_DEST (PATTERN (mhp -> insn_store)),
+                  		       0),
+                                 XEXP (mem, 0)))))
+        return (mhp - regno_holds_mem);
+    }
+  return FIRST_PSEUDO_REGISTER;
+}  /* find_regno_holds_mem (rtx mem) */
+
+
+
+/* Updates the regno_holds_mem array as required from pat */
+
+static void
+update_regno_holds_mem (rtx insn, rtx pat)
+{
+  register int i, j, regno, nregs;
+  MEM_HOLDER *mhp;
+  rtx set_src, set_dest;
+  register char *fmt;
+  register RTX_CODE code = GET_CODE (pat);
+
+  if (GET_CODE (insn) == JUMP_INSN)
+    {
+      for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+        regno_holds_mem[i].insn_store = 0;
+      return;
+    }
+
+  switch (GET_CODE (pat))
+    {
+      case SET:
+        set_src = SET_SRC (pat);
+        set_dest = SET_DEST (pat);
+        if (GET_CODE (set_dest) == REG)
+          {
+            regno = REGNO (set_dest);
+            nregs = HARD_REGNO_NREGS (regno, GET_MODE (set_dest));
+
+            mhp = &regno_holds_mem[regno];
+            if (nregs == 1
+                && (GET_CODE (set_src) == MEM
+                    && !MEM_VOLATILE_P (set_src)
+                    && GET_CODE (XEXP (set_src, 0)) != PRE_INC
+                    && GET_CODE (XEXP (set_src, 0)) != PRE_DEC
+                    && GET_CODE (XEXP (set_src, 0)) != POST_INC
+                    && GET_CODE (XEXP (set_src, 0)) != POST_DEC)
+                   || GET_CODE (set_src) == CONST_INT)
+              {
+                mhp -> mem = set_src;
+                mhp -> insn_load = insn;
+                mhp -> insn_store = mhp -> insn_dead = 0;
+              }
+            else
+              {
+                for (; mhp < &regno_holds_mem[regno] + nregs; mhp++)
+                  {
+                    bzero (mhp, sizeof (MEM_HOLDER));
+                  }
+              }
+            if (nregs == 1)
+              {
+                /* since we set a register, each mem using this reg is not valid
+                   any more */
+
+                update_entries (set_dest);
+              }
+            else
+              {
+                /* memory holds more than one register. This is a simplification
+                   Actually we should zero only those register entries which are
+                   relevant for nregs... */
+                bzero (regno_holds_mem, sizeof regno_holds_mem);
+                break;
+              }
+            update_regno_holds_mem (insn, set_src);
+          }
+        else if (GET_CODE (set_dest) == SUBREG)
+          {
+            if (GET_CODE (SUBREG_REG (set_dest)) == REG)
+              {
+                regno = REGNO (SUBREG_REG (set_dest)) + SUBREG_WORD (set_dest);
+                nregs 
+                  = HARD_REGNO_NREGS (regno, GET_MODE (SUBREG_REG (set_dest)));
+
+                mhp = &regno_holds_mem[regno];
+                for (; mhp < &regno_holds_mem[regno] + nregs; mhp++)
+                  {
+                    bzero (mhp, sizeof (MEM_HOLDER));
+                  }
+                if (nregs == 1)
+                  {
+                    update_entries (SUBREG_REG (set_dest));
+                  }
+                else
+                  {
+                    /* memory holds more than one register. This is a simplification.
+                       Actually we should zero only those register entries which are
+                       relevant for nregs... */
+                    bzero (regno_holds_mem, sizeof regno_holds_mem);
+                  }
+                update_regno_holds_mem (insn, set_src);
+                return;
+              }
+            else /* subreg of mem */
+              {
+	        for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+	          regno_holds_mem[i].mem = 0;
+                update_regno_holds_mem (insn, XEXP (XEXP (set_dest, 0), 0));
+                update_regno_holds_mem (insn, set_src);
+                return;
+              }
+          }
+        else if (GET_CODE (set_dest) == MEM)
+          {
+	    MEM_HOLDER save_mh;
+	    int is_push = 0;
+
+	    mhp = 0;
+
+            if ((GET_CODE (set_src) == REG
+                 || GET_CODE (set_src) == CONST_INT)
+                && push_operand (set_dest, Pmode))
+              { /* A push only ruins memory references based on stack_pointer */
+                is_push = 1;
+              }
+            else if (GET_CODE (set_src) == REG
+                /* We might want to add the possibility of SUBREG, isn't it? */
+                && !MEM_VOLATILE_P (set_dest)
+                && GET_CODE (XEXP (set_dest, 0)) != PRE_INC
+                && GET_CODE (XEXP (set_dest, 0)) != PRE_DEC
+                && GET_CODE (XEXP (set_dest, 0)) != POST_INC
+                && GET_CODE (XEXP (set_dest, 0)) != POST_DEC)
+              {
+                register int regno = REGNO (set_src);
+                register int nregs = HARD_REGNO_NREGS (regno,
+                				       GET_MODE (set_src));
+
+                if (nregs == 1)
+                  {
+                    mhp = &regno_holds_mem[regno];
+                    save_mh = *mhp;
+                  }
+              }
+            else if (GET_CODE (set_src) != REG)
+              update_regno_holds_mem (insn, set_src);
+
+            if (!is_push)
+              {
+                MEM_HOLDER *p = regno_holds_mem;
+                rtx store_pat;
+                
+	        for (; p < regno_holds_mem + FIRST_PSEUDO_REGISTER; p++)
+	          {
+	            if (p -> mem)
+	              {
+	                if (GET_CODE (p -> mem) == MEM
+	                    && true_dependence (set_dest, p -> mem))
+	                  {
+	                    p -> mem = 0;
+	                  }
+	              }
+	            if (p -> insn_store
+	                && (store_pat = PATTERN (p -> insn_store))
+	                && GET_CODE (SET_DEST (store_pat)) == MEM
+	                && true_dependence (set_dest,
+	                    		    SET_DEST (store_pat)))
+	              {
+	                /* insn_store is not valid any more */
+	                p -> insn_store = 0;
+	              }
+	          }
+	      }
+
+            if (mhp)
+              {
+                /* restore the relevant entry */
+		*mhp = save_mh;
+		mhp -> insn_store = insn;
+
+		/* if there was no load, we can consider this insn as if it is a
+		   load */
+		if (! mhp -> insn_load || GET_CODE (mhp -> insn_load) == NOTE)
+		  {
+		    mhp -> insn_load = insn;
+		    mhp -> mem = set_dest;
+		  }
+	      }
+              update_regno_holds_mem (insn, XEXP (set_dest, 0));
+          }
+        else
+          {
+            update_regno_holds_mem (insn, set_dest);
+            update_regno_holds_mem (insn, set_src);
+          }
+        return;
+      case CLOBBER:
+	set_dest = SET_DEST (pat);
+        if (GET_CODE (set_dest) == REG)
+          {
+            register int regno = REGNO (set_dest);
+            register int nregs = HARD_REGNO_NREGS (regno,
+                				   GET_MODE (set_dest));
+
+	    if (nregs == 1)
+	      {
+	        bzero (&regno_holds_mem[regno], sizeof (MEM_HOLDER));
+	        update_entries (set_dest);
+              }
+            else
+              /* memory holds more than one register. This is a simplification.
+                 Actually we should zero only those register entries which are
+                 relevant for nregs... */
+              bzero (regno_holds_mem, sizeof regno_holds_mem);
+          }
+        else if (GET_CODE (set_dest) == SUBREG)
+          {
+            regno = REGNO (SUBREG_REG (set_dest));
+            nregs = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (set_dest, 0)));
+
+            mhp = &regno_holds_mem[regno];
+            for (; mhp < &regno_holds_mem[regno] + nregs; mhp++)
+              {
+                bzero (mhp, sizeof (MEM_HOLDER));
+              }
+            if (nregs == 1)
+              {
+                update_entries (XEXP (set_dest, 0));
+              }
+            else
+              {
+                /* memory holds more than one register. This is a simplification.
+                   Actually we should zero only those register entries which are
+                   relevant for nregs... */
+                bzero (regno_holds_mem, sizeof regno_holds_mem);
+              }
+            return;
+          }
+        else if (GET_CODE (set_dest) == MEM)
+          for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+            {
+              /* the mem field indicates that this regno is no more valid for
+                 replacement in loads. Note that this regno might be valid for
+                 redundant store, or even replace loads with memory to which
+                 this reg was writing in the insn_store, and in such case we
+                 would like to reset the risc flags on all insns, from insn_load
+                 to insn_dead. This is why we don't reset here insn_load and
+                 insn_dead. */
+	      if (regno_holds_mem[i].mem
+	          && GET_CODE (regno_holds_mem[i].mem) == MEM
+	          && true_dependence (set_dest, regno_holds_mem[i].mem))
+                regno_holds_mem[i].mem = 0;
+            }
+        else
+          {
+            fprintf (stderr,
+                     "unpredicted case caused reset of regno_holds_mem:\n");
+            fprintf (stderr, "pattern:\n");
+            debug_rtx (pat);
+            fprintf (stderr, "insn:\n");
+	    debug_rtx (insn);
+	    bzero (regno_holds_mem, sizeof regno_holds_mem);
+	  }
+        return;
+      case CALL:
+        /* since we cannot know what writes to memory in the function call,
+           we must not use the information in regno_holds_mem anymore */
+
+	bzero (regno_holds_mem, sizeof regno_holds_mem);
+        return;
+      case PRE_DEC:
+      case PRE_INC:
+      case POST_DEC:
+      case POST_INC:
+        if (GET_CODE (XEXP (pat, 0)) == REG)
+          {
+            bzero (&regno_holds_mem[REGNO (XEXP (pat,0))], sizeof (MEM_HOLDER));
+	    update_entries (XEXP (pat, 0));
+          }
+        else
+          {
+            update_regno_holds_mem (insn, XEXP (pat, 0));
+          }
+        return;
+      case MEM:
+        /* there is a use of a memory in this insn, we cannot trust the
+           insn_store data anymore */
+        for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+          {
+            regno_holds_mem[i].insn_store = 0;
+            if (regno_holds_mem[i].insn_load == NULL)
+              {
+                regno_holds_mem[i].insn_dead = 0;
+                regno_holds_mem[i].mem = NULL;
+              }
+          }
+        update_regno_holds_mem (insn, XEXP (pat, 0));
+        return;
+      case USE:
+        update_regno_holds_mem (insn, SET_DEST (pat));
+        return;
+    case HIGH:
+    case CONST_INT:
+    case CONST:
+    case CONST_DOUBLE:
+    case SYMBOL_REF:
+    case LABEL_REF:
+    case PC:
+    case CC0:
+    case REG:
+    /*case SUBREG:*/
+        /* do nothing */
+        return;
+  }  /* switch (GET_CODE (pat)) */
+
+  fmt = GET_RTX_FORMAT (code);
+  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+    if (fmt[i] == 'e')
+      {
+        if( XEXP (pat, i))
+          update_regno_holds_mem (insn, XEXP (pat, i));
+      }
+    else if (fmt[i] == 'E' || fmt[i] == 'V')
+      {
+	for (j = 0; j < XVECLEN (pat, i); j++)
+	  update_regno_holds_mem (insn, XVECEXP (pat, i, j));
+      }
+}  /* update_regno_holds_mem (rtx pat) */
+
+
+
+
+/* Invalidates entries of memory mentioning REG in their memories, and the
+   entry of the appropriate REG */
+
+static void
+update_entries (rtx reg)
+{
+  register MEM_HOLDER *mhp = regno_holds_mem;
+  register int regno = REGNO (reg);
+
+  for (; mhp < regno_holds_mem + FIRST_PSEUDO_REGISTER; mhp++)
+    {
+      if (mhp->mem && reg_overlap_mentioned_p (reg, mhp->mem))
+        {
+          if (mhp->insn_store && mhp->insn_store != mhp->insn_load)
+            {
+              mhp -> insn_load = mhp -> insn_store;
+              mhp -> mem = SET_DEST (PATTERN (mhp -> insn_load));
+              mhp -> insn_dead = 0;
+            }
+          else
+            bzero (mhp, sizeof (MEM_HOLDER));
+        }
+      if (mhp -> insn_store && GET_CODE (mhp -> insn_store) == INSN
+          /* insn_store can be deleted by redundant store elimination */
+          && reg_overlap_mentioned_p (reg, 
+                                      SET_DEST (PATTERN (mhp->insn_store))))
+        {
+          if (mhp->insn_load == mhp->insn_store)
+           {
+              bzero (mhp, sizeof (MEM_HOLDER));
+           }
+          else
+           {
+             mhp -> insn_store = 0;
+           }
+        }
+    }  /* for (; mhp < regno_holds_mem + FIRST_PSEUDO_REGISTER; mhp++) */
+}  /* update_entries (rtx reg) */
+
+
+
+/* for each regno found to be non-free (is used or set) from (and including)
+   FIRST, to LAST, clears the appropriate bit in HARD_REG_SET pointed to by
+   FREE. */
+   
+void
+find_free_regs_between (free, first, last)
+    HARD_REG_SET *free;
+    rtx first;
+    rtx last;
+
+{
+  rtx insn, pat;
+  char *funcname = "find_free_regs_between";
+  register int i;
+
+
+  if (! first)
+    abort ();
+  if (! last)
+    abort ();
+
+  insn = first;
+  while (insn
+         && insn != last)
+    {
+      if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
+        {
+          if (GET_CODE (insn) == CALL_INSN)
+            {
+              /* we should reset all regs clobbered by a call */
+              for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+	        if (call_used_regs[i])
+		  CLEAR_HARD_REG_BIT (*free, i);
+	    }
+	  else  /* GET_RTX_CLASS (GET_CODE (insn)) != 'i' */
+	    {
+	      pat = PATTERN (insn);
+              for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+		if (INSN_SETS_REGNO (insn, i)
+		    || INSN_USES_REGNO (insn, i))
+	          CLEAR_HARD_REG_BIT (*free, i);
+	    }
+        } /* if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') */
+      insn = NEXT_INSN (insn);
+    }
+  if (insn != last)
+    fprintf (stderr, "%s (): didn't encounterd last!\n", funcname);
+  
+}
+
+/* removes a previous store of MEM if found, and returns INSN_UID of the insn
+   deleted. Otherwise returns 0. */
+static int
+remove_redundant_store (rtx mem, int block)
+{
+  rtx t_insn;
+  int regno;
+
+  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
+    if ((t_insn = regno_holds_mem[regno].insn_store)
+	&& GET_CODE (t_insn) == INSN
+        && rtx_equal_p (SET_DEST (PATTERN (t_insn)), mem))
+      {
+        if (basic_block_head[block] == t_insn)
+          basic_block_head[block] = NEXT_INSN (t_insn);
+        PUT_CODE (t_insn, NOTE);
+        NOTE_LINE_NUMBER (t_insn) = NOTE_INSN_DELETED;
+        NOTE_SOURCE_FILE (t_insn) = 0;
+
+        /* if the insn we have just deleted, was preceded with one or two risc
+           additions (i.e. memory_simplify added insns before it), and they are
+           not used for anything else, remove them as well */
+        if (RTX_IS_RISC_P (PREV_INSN (t_insn)))
+          {
+            PUT_CODE (PREV_INSN (t_insn), NOTE);
+            NOTE_LINE_NUMBER (PREV_INSN (t_insn)) = NOTE_INSN_DELETED;
+            NOTE_SOURCE_FILE (PREV_INSN (t_insn)) = 0;
+            if (RTX_IS_RISC_P (PREV_INSN (PREV_INSN (t_insn))))
+              {
+                PUT_CODE (PREV_INSN (PREV_INSN (t_insn)), NOTE);
+                NOTE_LINE_NUMBER (PREV_INSN (PREV_INSN (t_insn)))
+                					    = NOTE_INSN_DELETED;
+                NOTE_SOURCE_FILE (PREV_INSN (PREV_INSN (t_insn))) = 0;
+              }
+          }
+           
+        return INSN_UID (t_insn);
+      }
+  return 0;
+}  /* remove_redundant_store (rtx mem) */
+
+/* intel2 - end */
+/* intel1 */
+
+/*
+  Try to eliminate unnecessary reg to reg moves, and also
+  if the destination is a register try to use that register
+  as one of the sources.  
+
+  EXAMPLE:
+
+(insn 618 614 616 (set (reg:SI %eax)
+        (mem/s:SI (plus:SI (mult:SI (reg/v:SI %ebx)
+                    (const_int 4))
+                (reg:SI %esi)))) -1 (nil)
+    (nil))
+
+(insn 616 618 59 (set (reg:SI %esi)
+        (mem:SI (plus:SI (reg:SI %esp)
+                (const_int 36)))) -1 (nil)
+    (nil))
+
+(insn:HI 59 616 60 (set (reg:SI %eax)
+        (ior:SI (reg:SI %eax)
+            (mem/s:SI (plus:SI (mult:SI (reg/v:SI %ebx)
+                        (const_int 4))
+                    (reg:SI %esi))))) 105 {iorsi3} (nil)
+    (nil))
+
+(insn 60 59 620 (set (reg:SI %eax)
+        (not:SI (reg:SI %eax))) 130 {one_cmplsi2} (insn_list 59 (nil))
+        (nil))
+
+(insn 620 60 61 (set (reg/v:SI %ecx)
+        (reg:SI %eax)) -1 (nil)
+    (expr_list:REG_DEAD (reg:SI %eax)
+    (nil)))
+
+WILL BECOME:
+
+(insn 618 614 616 (set (reg:SI %ecx)
+        (mem/s:SI (plus:SI (mult:SI (reg/v:SI %ebx)
+                    (const_int 4))
+                (reg:SI %esi)))) -1 (nil)
+    (nil))
+
+(insn 616 618 59 (set (reg:SI %esi)
+        (mem:SI (plus:SI (reg:SI %esp)
+                (const_int 36)))) -1 (nil)
+    (nil))
+
+(insn:HI 59 616 60 (set (reg:SI %ecx)
+        (ior:SI (reg:SI %ecx)
+            (mem/s:SI (plus:SI (mult:SI (reg/v:SI %ebx)
+                        (const_int 4))
+                    (reg:SI %esi))))) 105 {iorsi3} (nil)
+    (nil))
+
+(insn 60 59 620 (set (reg:SI %ecx)
+        (not:SI (reg:SI %ecx))) 130 {one_cmplsi2} (insn_list 59 (nil))
+        (nil))
+
+(note 620 60 61 "" NOTE_INSN_DELETED)
+
+
+The trigger for the optimization is:
+
+(insn 620 60 61 (set (reg/v:SI %ecx)
+        (reg:SI %eax)) -1 (nil)
+    (expr_list:REG_DEAD (reg:SI %eax)
+    (nil)))
+
+*/
+void
+reg_to_reg_copy_opt (f, file)
+     rtx f;
+     FILE *file;
+{
+  rtx this_insn, regx, note, src;
+  int regno, success, length, i;
+  char * fmt;
+
+  if (file)
+    {
+      fprintf (file, "\n\ndoing reg to reg copy opt\n");
+    }
+  hard_reg_flow_analysis (f, NULL, 1);
+  this_insn = f;
+  while (this_insn)
+    {
+      if (GET_CODE (this_insn) == INSN 
+          && GET_CODE (PATTERN (this_insn)) == SET
+          && GET_CODE (SET_DEST (PATTERN (this_insn))) == REG
+          && GET_CODE (SET_SRC (PATTERN (this_insn))) == REG
+          && REGNO (SET_SRC (PATTERN (this_insn))) 
+             != REGNO (SET_DEST (PATTERN (this_insn))) 
+          && GET_MODE (SET_SRC (PATTERN (this_insn))) 
+             == GET_MODE (SET_DEST (PATTERN (this_insn))) 
+          && find_regno_note (this_insn, REG_DEAD, 
+                              REGNO (SET_SRC (PATTERN (this_insn))))
+         )
+        {
+          success = try_backwards_replace (SET_DEST (PATTERN (this_insn)), 
+                                 SET_SRC (PATTERN (this_insn)),
+                                 this_insn, 1, file);
+          if (!success)
+            {
+               success = try_forwards_replace (SET_DEST (PATTERN (this_insn)), 
+                                 SET_SRC (PATTERN (this_insn)),
+                                 this_insn, file);
+            }
+        }
+      else if (GET_CODE (this_insn) == INSN 
+               && GET_CODE (PATTERN (this_insn)) == SET
+               && GET_CODE (SET_DEST (PATTERN (this_insn))) == REG
+               && GET_CODE (SET_SRC (PATTERN (this_insn))) == SUBREG
+               && REGNO (SET_DEST (PATTERN (this_insn))) 
+                  != REGNO (SUBREG_REG (SET_SRC (PATTERN (this_insn))))
+               && SUBREG_WORD (SET_SRC (PATTERN (this_insn))) == 0
+               && GET_MODE (SET_SRC (PATTERN (this_insn))) 
+                  == GET_MODE (SET_DEST (PATTERN (this_insn))) 
+               && (note = find_regno_note (this_insn, REG_DEAD, 
+                                   REGNO (SUBREG_REG (SET_SRC (PATTERN (this_insn))))))
+               && rtx_equal_p (XEXP (note, 0), 
+                               SUBREG_REG (SET_SRC (PATTERN (this_insn))))
+               && HARD_REGNO_NREGS (REGNO (SET_DEST (PATTERN (this_insn))),
+            		            GET_MODE (SUBREG_REG (SET_SRC (PATTERN (this_insn)))))
+                   ==
+                  HARD_REGNO_NREGS (REGNO (SET_DEST (PATTERN (this_insn))),
+            			    GET_MODE (SET_DEST (PATTERN (this_insn))))
+               && HARD_REGNO_NREGS (REGNO (SET_DEST (PATTERN (this_insn))),
+            			    GET_MODE (SET_DEST (PATTERN (this_insn))))
+                   == 1
+               && HARD_REGNO_MODE_OK (REGNO (SET_DEST (PATTERN (this_insn))) ,
+                                      GET_MODE (SUBREG_REG (SET_SRC (PATTERN (this_insn)))))
+              )
+        {
+          regx = gen_rtx (REG, 
+                          GET_MODE (SUBREG_REG (SET_SRC (PATTERN (this_insn)))),
+                          REGNO (SET_DEST (PATTERN (this_insn))));
+          success 
+           = try_backwards_replace (regx,
+                                 SUBREG_REG (SET_SRC (PATTERN (this_insn))),
+                                 this_insn, 1, file);
+          if (!success)
+            {
+              success 
+               = try_forwards_replace (SET_DEST (PATTERN (this_insn)),
+                                 SET_SRC (PATTERN (this_insn)),
+                                 this_insn, file);
+            }
+        }
+      else if (GET_CODE (this_insn) == INSN 
+          && GET_CODE (PATTERN (this_insn)) == SET
+          && GET_CODE (SET_DEST (PATTERN (this_insn))) == REG
+          && GET_CODE (SET_SRC (PATTERN (this_insn))) != MEM
+          && GET_CODE (SET_SRC (PATTERN (this_insn))) != SUBREG
+          && !reg_overlap_mentioned_p (SET_DEST (PATTERN (this_insn)),
+                                       SET_SRC (PATTERN (this_insn)))
+          )
+        {
+          src = SET_SRC (PATTERN (this_insn));
+          fmt = GET_RTX_FORMAT (GET_CODE (src));
+          length = GET_RTX_LENGTH (GET_CODE (src));
+          for (i=0; i<length; i++)
+            {
+              if (fmt[i] == 'e' 
+                  && GET_CODE (XEXP (src, i)) == SUBREG)
+                {  /* Makes matters too complex.  */
+                  return;
+                }
+            }
+          for (i=0; i<length; i++)
+            {
+              if (fmt[i] == 'e' 
+                  && GET_CODE (XEXP (src, i)) == REG
+                  && (note = find_regno_note (this_insn, REG_DEAD,
+                                              REGNO (XEXP (src, i))))
+                  && rtx_equal_p (XEXP (src, i), XEXP (note, 0))
+                  )
+                { /* One of the sources dies in this insn -
+                     see if the destination register can be used
+                     to replace that register.  This has a chance
+                     of producing better code e.g. reg1 <- reg1 AND reg3
+                     produces more efficient code than 
+                     reg1 <- reg2 AND reg3.  */
+                  rtx regx, regy;
+                  regy = XEXP (src, i);
+                  regx = SET_DEST (PATTERN (this_insn));
+                  if (reg_overlap_mentioned_p (regx, PATTERN (this_insn)))
+                    {
+                      break;
+                    }
+                  if (GET_MODE (regx) != GET_MODE (regy))
+                    {
+                      if (HARD_REGNO_NREGS (REGNO (regx), GET_MODE (regy)) != 1
+                          || 
+                          !(HARD_REGNO_MODE_OK (REGNO (regx), GET_MODE (regy))))
+                        {
+                          continue;
+                        }
+                      regx = gen_rtx (REG, GET_MODE (regy), REGNO (regx)); 
+                    }
+                  if (try_backwards_replace (regx, regy, this_insn, 0, file))
+                    {
+                      remove_note (this_insn, note);
+                      break; /* Since now the dest reg is 
+                                mentioned in the src.  */
+                    }
+                }
+            }
+
+        }
+      this_insn = NEXT_INSN (this_insn);
+    }
+  if (file)
+    {
+      fprintf (file, "\n");
+    }
+}
+
+/*
+  insn is of the form
+     regx <- regy (regy dead)
+   or
+     regx <- SUBREG (regy) (regy dead)
+   or
+     regx <- OP (regy, ...) (regy dead)
+   
+  Search backwards for last previous setting of regy in which the 
+  setting of regy can be replaced with regx.  If it can then
+  do the replacement and then if delete_flag is set delete insn.  
+*/
+
+static
+int
+try_backwards_replace (regx, regy, insn, delete_flag, file)
+  rtx regx, regy, insn;
+  FILE *file;
+{
+  rtx this_insn, set_insn, stop_insn;
+  int stop_replacement = 0;
+  int found = 0, insn_code_number, not_yet_recoged;
+  
+  
+  if (file)
+    {
+      fprintf (file, "\ninsn %d reg%d <- reg%d (reg%d dead) (try backwards)\n", 
+      INSN_UID(insn), REGNO (regx), REGNO (regy), REGNO(regy));
+    }
+  this_insn = prev_nonnote_insn (insn);
+  /* Find the first previous insn in the block that sets regy and in
+     which regy can be replaced with regx */
+  while (!found && this_insn 
+         && !(GET_CODE (this_insn) == CODE_LABEL 
+              || GET_CODE (this_insn) == CALL_INSN
+              || GET_CODE (this_insn) == JUMP_INSN))
+    {
+      if (GET_CODE (this_insn) == INSN)
+        {
+          if (GET_CODE (PATTERN (this_insn)) != SET)
+            {
+              return (0);
+            }
+          if (GET_CODE (SET_DEST (PATTERN (this_insn))) == REG)
+            {
+              if (REGNO (regx) == REGNO (SET_DEST (PATTERN (this_insn))))
+                {
+                  return (0);
+                }
+              else if (REGNO (regy) == REGNO (SET_DEST (PATTERN (this_insn))))
+                {
+                  if (GET_MODE (regy) 
+                       == GET_MODE (SET_DEST (PATTERN (this_insn))))
+                    {
+#ifdef REGISTER_CONSTRAINTS
+                      if (INSN_CODE (this_insn) == -1)
+                        {
+                          INSN_CODE (this_insn) 
+                            = recog (PATTERN (this_insn), this_insn, 0);
+                        }
+#endif
+                      SET_DEST (PATTERN (this_insn)) = regx;
+#ifdef REGISTER_CONSTRAINTS
+
+	              if ((insn_code_number
+	                   = recog (PATTERN (this_insn), this_insn, 0)) < 0
+                          || (INSN_CODE (this_insn) != -1
+                              && insn_code_number != INSN_CODE (this_insn)))
+	                {/* Need to have the same code number since 
+	                    constraints are sometimes more lax than 
+	                    predicates */
+		          SET_DEST (PATTERN (this_insn)) = regy;
+		          stop_replacement = 1;
+		        }
+		        else
+	                {
+	                  INSN_CODE (this_insn) = insn_code_number;
+		          insn_extract (this_insn);
+		          if(!constrain_operands (INSN_CODE (this_insn), 1))
+	                    {
+		              /* restore the previous situation */
+	  	              SET_DEST (PATTERN (this_insn)) = regy;
+	                      /*INSN_CODE (this_insn) 
+	                       = recog (PATTERN (this_insn), this_insn, 0);*/
+		              stop_replacement = 1;
+ 		            }
+		        }
+        
+#endif
+                      if (!stop_replacement)
+                        {
+                          found = 1;
+                          set_insn = this_insn;
+                        }
+                    }
+                  else
+                    {
+                      return (0);
+                    }
+                }
+            }
+          else if (reg_overlap_mentioned_p (regx, SET_DEST (PATTERN (this_insn))))
+            {
+              return (0);
+            }
+          if (!found
+              && reg_overlap_mentioned_p (regx, SET_SRC (PATTERN (this_insn))))
+            {
+              return (0);
+            }
+        }
+      if (!found)
+        {
+          stop_replacement = 0;
+          this_insn = prev_nonnote_insn (this_insn);
+        }
+    }
+  if (found)
+    {/* We have found the insn that last sets regy and successfully 
+        replaced regx as the dest of that insn.  
+        In all insns between set_insn and insn replace regy with regx.  */
+      stop_replacement = 0;
+      this_insn = next_nonnote_insn (set_insn);
+      init_undo_buf ();
+      stop_insn = next_nonnote_insn (insn);
+      while (this_insn != stop_insn && !stop_replacement)
+        {
+#ifdef REGISTER_CONSTRAINTS
+          if (INSN_CODE (this_insn) == -1)
+            {
+              INSN_CODE (this_insn) 
+                = recog (PATTERN (this_insn), this_insn, 0);
+            }
+#endif
+          subst_in_insn (this_insn, PATTERN (this_insn), regy, regx, 0, 0);
+          if (reg_set_p (regy, this_insn)
+              || reg_overlap_mentioned_p (regy, PATTERN (this_insn)))
+            { /* regy was used in some other mode - fail */
+              stop_replacement = 1;
+            }
+#ifdef REGISTER_CONSTRAINTS
+          if (stop_replacement
+              ||
+              (insn_code_number
+                = recog (PATTERN (this_insn), this_insn, 0)) < 0
+              || (INSN_CODE (this_insn) != -1
+                  && insn_code_number != INSN_CODE (this_insn)))
+            {/* Need to have the same code number since constraints
+                 are sometimes more lax than predicates */
+              stop_replacement = 1;
+            }
+          else
+            {
+              INSN_CODE (this_insn) = insn_code_number;
+              insn_extract (this_insn);
+	      if(!constrain_operands (INSN_CODE (this_insn), 1))
+	        {
+	          stop_replacement = 1;
+	        }
+            }
+#endif
+          this_insn = next_nonnote_insn ( this_insn);
+        }
+        
+      if (stop_replacement)
+        { /* A replacement was unsuccessful - undo all of the replacements */
+          SET_DEST (PATTERN (set_insn)) = regy;
+          /*INSN_CODE (this_insn) 
+            = recog (PATTERN (this_insn), this_insn, 0);*/
+          this_insn = next_nonnote_insn (set_insn);
+          loop_undo_all ();
+          /*while (this_insn != insn)
+            {
+              INSN_CODE (this_insn) 
+                = recog (PATTERN (this_insn), this_insn, 0); 
+              this_insn = next_nonnote_insn (this_insn);
+            }*/
+          return (0);
+        }
+      else 
+        { 
+	  if (file)
+	    {
+	      fprintf (file, "replaced dest reg%d of insn %d with reg%d\n",
+	        REGNO (regy), INSN_UID (set_insn), REGNO (regx));
+	      fprintf (file, " in insns %d through %d replaced reg%d with reg%d\n",
+	        INSN_UID (next_nonnote_insn (set_insn)),
+	        INSN_UID (insn), 
+	        REGNO (regy), REGNO (regx));
+	    }
+          if (delete_flag)
+            {/* Delete insn */
+              PUT_CODE (insn, NOTE);
+	      NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
+	      NOTE_SOURCE_FILE (insn) = 0;
+	      if (file)
+	        {
+	          fprintf (file, " deleted insn %d\n", INSN_UID (insn));
+	        }
+	    }
+          return (1);
+        }
+    }
+  return (0);
+}
+
+
+/*
+  insn is of the form
+     regx <- regy (regy dead)
+   or
+     regx <- SUBREG (regy) (regy dead)
+   
+  Search forwards for next insn in which the regx is dead.
+  Try to replace all uses of regx with regy in those insns
+  and if successful then delete insn.  
+*/
+
+static
+int
+try_forwards_replace (regx, regy, insn, file)
+  rtx regx, regy, insn;
+  FILE *file;
+{
+  rtx this_insn, dead_insn, dead_note, stop_insn;
+  int stop_replacement = 0;
+  int found = 0, insn_code_number;
+  
+  
+  if (file)
+    {
+      if (GET_CODE (regy) == REG )
+        fprintf (file, "\ninsn %d reg%d <- reg%d (reg%d dead) (try forwards)\n", 
+        INSN_UID(insn), REGNO (regx), REGNO (regy), REGNO(regy));
+      else
+        fprintf (file, "\ninsn %d reg%d <- reg%d (reg%d dead) (try forwards)\n", 
+        INSN_UID(insn), REGNO (regx), 
+        REGNO (SUBREG_REG (regy)), 
+        REGNO (SUBREG_REG (regy)));
+    }
+  this_insn = next_nonnote_insn (insn);
+  /* Find the next insn in the block where regx dies */
+  while (!found && this_insn 
+         && !(GET_CODE (this_insn) == CODE_LABEL 
+              || GET_CODE (this_insn) == CALL_INSN
+              || GET_CODE (this_insn) == JUMP_INSN))
+    {
+      if (GET_CODE (this_insn) == INSN)
+        {
+          if (GET_CODE (PATTERN (insn)) == USE
+              && reg_overlap_mentioned_p (regx, SET_DEST (PATTERN (insn))))
+            {
+              return (0);
+            }
+          if (reg_set_p (regy, this_insn))
+            {
+              return (0);
+            }
+          else if ((dead_note 
+                    = find_regno_note (this_insn, REG_DEAD, REGNO (regx)))
+                   && rtx_equal_p (XEXP (dead_note, 0), regx))
+            {
+              found = 1;
+              dead_insn = this_insn;
+            }
+        }
+      if (!found)
+        {
+          this_insn = next_nonnote_insn (this_insn);
+        }
+    }
+  if (found)
+    {/* We have found the insn where regx dies.  */
+      stop_replacement = 0;
+      this_insn = next_nonnote_insn (insn);
+      init_undo_buf ();
+      stop_insn = next_nonnote_insn (dead_insn);
+      while (this_insn != stop_insn && !stop_replacement)
+        {
+#ifdef REGISTER_CONSTRAINTS
+          if (INSN_CODE (this_insn) == -1)
+            {
+              INSN_CODE (this_insn) 
+                = recog (PATTERN (this_insn), this_insn, 0);
+            }
+#endif
+          subst_in_insn (this_insn, PATTERN (this_insn), regx, regy, 0, 0);
+          if (reg_set_p (regx, this_insn)
+              || reg_overlap_mentioned_p (regx, PATTERN (this_insn)))
+            { /* regx is used in some other mode - fail.  */
+              if (file)
+                {
+                  fprintf (file, "fail insn %d reg %d still mentioned\n",
+                  INSN_UID (this_insn), REGNO (regx));
+                  tdebug_rtx (this_insn, file);
+                }
+              stop_replacement = 1;
+            }
+#ifdef REGISTER_CONSTRAINTS
+          if (stop_replacement
+              ||
+              (insn_code_number
+                = recog (PATTERN (this_insn), this_insn, 0)) < 0
+              || (INSN_CODE (this_insn) != -1
+                  && insn_code_number != INSN_CODE (this_insn)))
+            { /* Need to have the same code number since constraints
+                 are sometimes more lax than predicates */
+              if (file)
+                {
+                  fprintf (file, "fail insn %d new_recog %d old_recog %d\n",
+                  INSN_UID (this_insn), insn_code_number, INSN_CODE (this_insn));
+                }
+              stop_replacement = 1;
+            }
+          else
+            {
+              INSN_CODE (this_insn) = insn_code_number;
+              insn_extract (this_insn);
+	      if(!constrain_operands (INSN_CODE (this_insn), 1))
+	        {
+	          stop_replacement = 1;
+	        }
+            }
+#endif
+          this_insn = next_nonnote_insn ( this_insn);
+        }
+        
+      if (stop_replacement)
+        { /* A replacement was unsuccessful - undo all of the replacements */
+          this_insn = next_nonnote_insn (insn);
+          loop_undo_all ();
+          stop_insn = next_nonnote_insn (dead_insn);
+          /*while (this_insn != stop_insn)
+            {
+              INSN_CODE (this_insn) 
+                 = recog (PATTERN (this_insn), this_insn, 0); 
+              this_insn = next_nonnote_insn (this_insn);
+            }*/
+          return (0);
+        }
+      else
+        { /* Delete insn */
+          PUT_CODE (insn, NOTE);
+	  NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
+	  NOTE_SOURCE_FILE (insn) = 0;
+	  XEXP (dead_note, 0) = regy;
+	  if (file)
+	    {
+	      fprintf (file, " in insns %d through %d replaced reg%d with reg%d\n",
+		       INSN_UID (next_nonnote_insn (insn)),
+		       INSN_UID (dead_insn), 
+		       REGNO (regx), 
+		       GET_CODE (regy) == REG 
+		         ? REGNO (regy)
+		         : REGNO (SUBREG_REG (regy)));
+	      fprintf (file, " deleted insn %d\n", INSN_UID (insn));
+	    }
+          return (1);
+        }
+    }
+  return (0);
 }
diff -r -u -H -N gcc-2.6.3/config/i386/i386.c gcc-i2.6.3/config/i386/i386.c
--- gcc-2.6.3/config/i386/i386.c	Sat Nov  5 13:57:47 1994
+++ gcc-i2.6.3/config/i386/i386.c	Thu Feb 16 12:51:33 1995
@@ -1,6 +1,9 @@
 /* Subroutines for insn-output.c for Intel X86.
-   Copyright (C) 1988, 1992, 1994 Free Software Foundation, Inc.
+   Copyright (C) 1988, 1992 Free Software Foundation, Inc.
 
+   Pentium cpu support and other enhancements by Tevi Devor Intel Corp.
+   (tevi@iil.intel.com).
+  
 This file is part of GNU CC.
 
 GNU CC is free software; you can redistribute it and/or modify
@@ -33,6 +36,8 @@
 #include "flags.h"
 #include "function.h"
 
+/* intel1 Need the EXTRA_CONSTRAINT - changed s to */
+#if 0
 #ifdef EXTRA_CONSTRAINT
 /* If EXTRA_CONSTRAINT is defined, then the 'S'
    constraint in REG_CLASS_FROM_LETTER will no longer work, and various
@@ -41,6 +46,10 @@
 /* The previous line used to be #error, but some compilers barf
    even if the conditional was untrue.  */
 #endif
+#endif
+
+/* which cpu are we scheduling for intel1*/
+enum processor_type x86_cpu;
 
 #define AT_BP(mode) (gen_rtx (MEM, (mode), frame_pointer_rtx))
 
@@ -51,6 +60,9 @@
 char *output_move_const_single ();
 char *output_fp_cc0_set ();
 
+/* intel1 */
+static int opt_level=0;
+
 char *hi_reg_name[] = HI_REGISTER_NAMES;
 char *qi_reg_name[] = QI_REGISTER_NAMES;
 char *qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
@@ -74,151 +86,8 @@
 /* Test and compare insns in i386.md store the information needed to
    generate branch and scc insns here.  */
 
-struct rtx_def *i386_compare_op0 = NULL_RTX;
-struct rtx_def *i386_compare_op1 = NULL_RTX;
+struct rtx_def *i386_compare_op0, *i386_compare_op1;
 struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)();
-
-/* Register allocation order */
-char *i386_reg_alloc_order = (char *)0;
-static char regs_allocated[FIRST_PSEUDO_REGISTER];
-
-
-/* Sometimes certain combinations of command options do not make
-   sense on a particular target machine.  You can define a macro
-   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
-   defined, is executed once just after all the command options have
-   been parsed.
-
-   Don't use this macro to turn on various extra optimizations for
-   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */
-
-void
-override_options ()
-{
-  int ch, i, regno;
-
-#ifdef SUBTARGET_OVERRIDE_OPTIONS
-  SUBTARGET_OVERRIDE_OPTIONS;
-#endif
-
-  /* Validate registers in register allocation order */
-  if (i386_reg_alloc_order)
-    {
-      for (i = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++)
-	{
-	  switch (ch)
-	    {
-	    case 'a':	regno = 0;	break;
-	    case 'd':	regno = 1;	break;
-	    case 'c':	regno = 2;	break;
-	    case 'b':	regno = 3;	break;
-	    case 'S':	regno = 4;	break;
-	    case 'D':	regno = 5;	break;
-	    case 'B':	regno = 6;	break;
-
-	    default:	fatal ("Register '%c' is unknown", ch);
-	    }
-
-	  if (regs_allocated[regno])
-	    fatal ("Register '%c' was already specified in the allocation order", ch);
-
-	  regs_allocated[regno] = 1;
-	}
-    }
-}
-
-/* A C statement (sans semicolon) to choose the order in which to
-   allocate hard registers for pseudo-registers local to a basic
-   block.
-
-   Store the desired register order in the array `reg_alloc_order'.
-   Element 0 should be the register to allocate first; element 1, the
-   next register; and so on.
-
-   The macro body should not assume anything about the contents of
-   `reg_alloc_order' before execution of the macro.
-
-   On most machines, it is not necessary to define this macro.  */
-
-void
-order_regs_for_local_alloc ()
-{
-  int i, ch, order, regno;
-
-  /* User specified the register allocation order */
-  if (i386_reg_alloc_order)
-    {
-      for (i = order = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++)
-	{
-	  switch (ch)
-	    {
-	    case 'a':	regno = 0;	break;
-	    case 'd':	regno = 1;	break;
-	    case 'c':	regno = 2;	break;
-	    case 'b':	regno = 3;	break;
-	    case 'S':	regno = 4;	break;
-	    case 'D':	regno = 5;	break;
-	    case 'B':	regno = 6;	break;
-	    }
-
-	  reg_alloc_order[order++] = regno;
-	}
-
-      for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-	{
-	  if (!regs_allocated[i])
-	    reg_alloc_order[order++] = i;
-	}
-    }
-
-  /* If users did not specify a register allocation order, favor eax
-     normally except if DImode variables are used, in which case
-     favor edx before eax, which seems to cause less spill register
-     not found messages.  */
-  else
-    {
-      rtx insn;
-
-      for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-	reg_alloc_order[i] = i;
-
-      if (optimize)
-	{
-	  int use_dca = FALSE;
-
-	  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
-	    {
-	      if (GET_CODE (insn) == INSN)
-		{
-		  rtx set = NULL_RTX;
-		  rtx pattern = PATTERN (insn);
-
-		  if (GET_CODE (pattern) == SET)
-		    set = pattern;
-
-		  else if ((GET_CODE (pattern) == PARALLEL
-			    || GET_CODE (pattern) == SEQUENCE)
-			   && GET_CODE (XVECEXP (pattern, 0, 0)) == SET)
-		    set = XVECEXP (pattern, 0, 0);
-
-		  if (set && GET_MODE (SET_SRC (set)) == DImode)
-		    {
-		      use_dca = TRUE;
-		      break;
-		    }
-		}
-	    }
-
-	  if (use_dca)
-	    {
-	      reg_alloc_order[0] = 1;	/* edx */
-	      reg_alloc_order[1] = 2;	/* ecx */
-	      reg_alloc_order[2] = 0;	/* eax */
-	    }
-	}
-    }
-}
-
 
 /* Output an insn whose source is a 386 integer register.  SRC is the
    rtx for the register, and TEMPLATE is the op-code template.  SRC may
@@ -378,7 +247,6 @@
   abort ();
 }
 
-
 /* Output an insn to add the constant N to the register X.  */
 
 static void
@@ -387,25 +255,19 @@
      rtx x;
 {
   rtx xops[2];
-  xops[0] = x;
-
-  if (n == -1)
-    output_asm_insn (AS1 (dec%L0,%0), xops);
-  else if (n == 1)
-    output_asm_insn (AS1 (inc%L0,%0), xops);
-  else if (n < 0)
+  xops[1] = x;
+  if (n < 0)
     {
-      xops[1] = GEN_INT (-n);
-      output_asm_insn (AS2 (sub%L0,%1,%0), xops);
+      xops[0] = GEN_INT (-n);
+      output_asm_insn (AS2 (sub%L0,%0,%1), xops);
     }
   else if (n > 0)
     {
-      xops[1] = GEN_INT (n);
-      output_asm_insn (AS2 (add%L0,%1,%0), xops);
+      xops[0] = GEN_INT (n);
+      output_asm_insn (AS2 (add%L0,%0,%1), xops);
     }
 }
 
-
 /* Output assembler code to perform a doubleword move insn
    with operands OPERANDS.  */
 
@@ -737,199 +599,6 @@
 
   return "";
 }
-
-
-#define MAX_TMPS 2		/* max temporary registers used */
-
-/* Output the appropriate code to move push memory on the stack */
-
-char *
-output_move_pushmem (operands, insn, length, tmp_start, n_operands)
-     rtx operands[];
-     rtx insn;
-     int length;
-     int tmp_start;
-     int n_operands;
-{
-
-  struct {
-    char *load;
-    char *push;
-    rtx   xops[2];
-  } tmp_info[MAX_TMPS];
-
-  rtx src = operands[1];
-  int max_tmps = 0;
-  int offset = 0;
-  int stack_p = reg_overlap_mentioned_p (stack_pointer_rtx, src);
-  int stack_offset = 0;
-  int i, num_tmps;
-  rtx xops[1];
-
-  if (!offsettable_memref_p (src))
-    fatal_insn ("Source is not offsettable", insn);
-
-  if ((length & 3) != 0)
-    fatal_insn ("Pushing non-word aligned size", insn);
-
-  /* Figure out which temporary registers we have available */
-  for (i = tmp_start; i < n_operands; i++)
-    {
-      if (GET_CODE (operands[i]) == REG)
-	{
-	  if (reg_overlap_mentioned_p (operands[i], src))
-	    continue;
-
-	  tmp_info[ max_tmps++ ].xops[1] = operands[i];
-	  if (max_tmps == MAX_TMPS)
-	    break;
-	}
-    }
-
-  if (max_tmps == 0)
-    for (offset = length - 4; offset >= 0; offset -= 4)
-      {
-	xops[0] = adj_offsettable_operand (src, offset + stack_offset);
-	output_asm_insn (AS1(push%L0,%0), xops);
-	if (stack_p)
-	  stack_offset += 4;
-      }
-
-  else
-    for (offset = length - 4; offset >= 0; )
-      {
-	for (num_tmps = 0; num_tmps < max_tmps && offset >= 0; num_tmps++)
-	  {
-	    tmp_info[num_tmps].load    = AS2(mov%L0,%0,%1);
-	    tmp_info[num_tmps].push    = AS1(push%L0,%1);
-	    tmp_info[num_tmps].xops[0] = adj_offsettable_operand (src, offset + stack_offset);
-	    offset -= 4;
-	  }
-
-	for (i = 0; i < num_tmps; i++)
-	  output_asm_insn (tmp_info[i].load, tmp_info[i].xops);
-
-	for (i = 0; i < num_tmps; i++)
-	  output_asm_insn (tmp_info[i].push, tmp_info[i].xops);
-
-	if (stack_p)
-	  stack_offset += 4*num_tmps;
-      }
-
-  return "";
-}
-
-
-
-/* Output the appropriate code to move data between two memory locations */
-
-char *
-output_move_memory (operands, insn, length, tmp_start, n_operands)
-     rtx operands[];
-     rtx insn;
-     int length;
-     int tmp_start;
-     int n_operands;
-{
-  struct {
-    char *load;
-    char *store;
-    rtx   xops[3];
-  } tmp_info[MAX_TMPS];
-
-  rtx dest = operands[0];
-  rtx src  = operands[1];
-  rtx qi_tmp = NULL_RTX;
-  int max_tmps = 0;
-  int offset = 0;
-  int i, num_tmps;
-  rtx xops[3];
-
-  if (GET_CODE (dest) == MEM
-      && GET_CODE (XEXP (dest, 0)) == PRE_INC
-      && XEXP (XEXP (dest, 0), 0) == stack_pointer_rtx)
-    return output_move_pushmem (operands, insn, length, tmp_start, n_operands);
-
-  if (!offsettable_memref_p (src))
-    fatal_insn ("Source is not offsettable", insn);
-
-  if (!offsettable_memref_p (dest))
-    fatal_insn ("Destination is not offsettable", insn);
-
-  /* Figure out which temporary registers we have available */
-  for (i = tmp_start; i < n_operands; i++)
-    {
-      if (GET_CODE (operands[i]) == REG)
-	{
-	  if ((length & 1) != 0 && !qi_tmp && QI_REG_P (operands[i]))
-	    qi_tmp = operands[i];
-
-	  if (reg_overlap_mentioned_p (operands[i], dest))
-	    fatal_insn ("Temporary register overlaps the destination", insn);
-
-	  if (reg_overlap_mentioned_p (operands[i], src))
-	    fatal_insn ("Temporary register overlaps the source", insn);
-
-	  tmp_info[ max_tmps++ ].xops[2] = operands[i];
-	  if (max_tmps == MAX_TMPS)
-	    break;
-	}
-    }
-
-  if (max_tmps == 0)
-    fatal_insn ("No scratch registers were found to do memory->memory moves", insn);
-
-  if ((length & 1) != 0)
-    {
-      if (!qi_tmp)
-	fatal_insn ("No byte register found when moving odd # of bytes.", insn);
-    }
-
-  while (length > 1)
-    {
-      for (num_tmps = 0; num_tmps < max_tmps; num_tmps++)
-	{
-	  if (length >= 4)
-	    {
-	      tmp_info[num_tmps].load    = AS2(mov%L0,%1,%2);
-	      tmp_info[num_tmps].store   = AS2(mov%L0,%2,%0);
-	      tmp_info[num_tmps].xops[0] = adj_offsettable_operand (dest, offset);
-	      tmp_info[num_tmps].xops[1] = adj_offsettable_operand (src, offset);
-	      offset += 4;
-	      length -= 4;
-	    }
-	  else if (length >= 2)
-	    {
-	      tmp_info[num_tmps].load    = AS2(mov%W0,%1,%2);
-	      tmp_info[num_tmps].store   = AS2(mov%W0,%2,%0);
-	      tmp_info[num_tmps].xops[0] = adj_offsettable_operand (dest, offset);
-	      tmp_info[num_tmps].xops[1] = adj_offsettable_operand (src, offset);
-	      offset += 2;
-	      length -= 2;
-	    }
-	  else
-	    break;
-	}
-
-      for (i = 0; i < num_tmps; i++)
-	output_asm_insn (tmp_info[i].load, tmp_info[i].xops);
-
-      for (i = 0; i < num_tmps; i++)
-	output_asm_insn (tmp_info[i].store, tmp_info[i].xops);
-    }
-
-  if (length == 1)
-    {
-      xops[0] = adj_offsettable_operand (dest, offset);
-      xops[1] = adj_offsettable_operand (src, offset);
-      xops[2] = qi_tmp;
-      output_asm_insn (AS2(mov%B0,%1,%2), xops);
-      output_asm_insn (AS2(mov%B0,%2,%0), xops);
-    }
-
-  return "";
-}
-
 
 int
 standard_80387_constant_p (x)
@@ -1084,6 +753,111 @@
   return 0;
 }
 
+/* Return a legitimate reference for ORIG (an address) using the
+   register REG.  If REG is 0, a new pseudo is generated.
+
+   There are three types of references that must be handled:
+
+   1. Global data references must load the address from the GOT, via
+      the PIC reg.  An insn is emitted to do this load, and the reg is
+      returned.
+
+   2. Static data references must compute the address as an offset
+      from the GOT, whose base is in the PIC reg.  An insn is emitted to
+      compute the address into a reg, and the reg is returned.  Static
+      data objects have SYMBOL_REF_FLAG set to differentiate them from
+      global data objects.
+
+   3. Constant pool addresses must be handled special.  They are
+      considered legitimate addresses, but only if not used with regs.
+      When printed, the output routines know to print the reference with the
+      PIC reg, even though the PIC reg doesn't appear in the RTL.
+
+   GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
+   reg also appears in the address (except for constant pool references,
+   noted above).
+
+   "switch" statements also require special handling when generating
+   PIC code.  See comments by the `casesi' insn in i386.md for details.  */
+
+rtx
+legitimize_pic_address (orig, reg)
+     rtx orig;
+     rtx reg;
+{
+  rtx addr = orig;
+  rtx new = orig;
+
+  if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
+    {
+      if (GET_CODE (addr) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (addr))
+	reg = new = orig;
+      else
+	{
+	  if (reg == 0)
+	    reg = gen_reg_rtx (Pmode);
+
+	  if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_FLAG (addr))
+	    new = gen_rtx (PLUS, Pmode, pic_offset_table_rtx, orig);
+	  else
+	    new = gen_rtx (MEM, Pmode,
+			   gen_rtx (PLUS, Pmode,
+				    pic_offset_table_rtx, orig));
+
+	  emit_move_insn (reg, new);
+	}
+      current_function_uses_pic_offset_table = 1;
+      return reg;
+    }
+  else if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS)
+    {
+      rtx base;
+
+      if (GET_CODE (addr) == CONST)
+	{
+	  addr = XEXP (addr, 0);
+	  if (GET_CODE (addr) != PLUS)
+	    abort ();
+	}
+
+      if (XEXP (addr, 0) == pic_offset_table_rtx)
+	return orig;
+
+      if (reg == 0)
+	reg = gen_reg_rtx (Pmode);
+
+      base = legitimize_pic_address (XEXP (addr, 0), reg);
+      addr = legitimize_pic_address (XEXP (addr, 1),
+				     base == reg ? NULL_RTX : reg);
+
+      if (GET_CODE (addr) == CONST_INT)
+	return plus_constant (base, INTVAL (addr));
+
+      if (GET_CODE (addr) == PLUS && CONSTANT_P (XEXP (addr, 1)))
+	{
+	  base = gen_rtx (PLUS, Pmode, base, XEXP (addr, 0));
+	  addr = XEXP (addr, 1);
+	}
+	return gen_rtx (PLUS, Pmode, base, addr);
+    }
+  return new;
+}
+
+/* Emit insns to move operands[1] into operands[0].  */
+
+void
+emit_pic_move (operands, mode)
+     rtx *operands;
+     enum machine_mode mode;
+{
+  rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
+
+  if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1]))
+    operands[1] = (rtx) force_reg (SImode, operands[1]);
+  else
+    operands[1] = legitimize_pic_address (operands[1], temp);
+}
+
 /* This function generates the assembly code for function entry.
    FILE is an stdio stream to output the code to.
    SIZE is an int: how many units of temporary storage to allocate. */
@@ -1177,7 +951,6 @@
   return nregs == 0 || ! frame_pointer_needed;
 }
 
-
 /* This function generates the assembly code for function exit.
    FILE is an stdio stream to output the code to.
    SIZE is an int: how many units of temporary storage to deallocate. */
@@ -1251,7 +1024,7 @@
     {
       /* On i486, mov & pop is faster than "leave". */
 
-      if (!TARGET_386)
+      if (TARGET_486)
 	{
 	  xops[0] = frame_pointer_rtx;
 	  output_asm_insn (AS2 (mov%L2,%0,%2), xops);
@@ -1290,1572 +1063,2060 @@
   else
     output_asm_insn ("ret", xops);
 }
-
 
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   On x86, legitimate addresses are:
-	base				movl (base),reg
-	displacement			movl disp,reg
-	base + displacement		movl disp(base),reg
-	index + base			movl (base,index),reg
-	(index + base) + displacement	movl disp(base,index),reg
-	index*scale			movl (,index,scale),reg
-	index*scale + disp		movl disp(,index,scale),reg
-	index*scale + base 		movl (base,index,scale),reg
-	(index*scale + base) + disp	movl disp(base,index,scale),reg
-
-	In each case, scale can be 1, 2, 4, 8.  */
-
-/* This is exactly the same as print_operand_addr, except that
-   it recognizes addresses instead of printing them.
-
-   It only recognizes address in canonical form.  LEGITIMIZE_ADDRESS should
-   convert common non-canonical forms to canonical form so that they will
-   be recognized.  */
-
-#define ADDR_INVALID(msg,insn)						\
-do {									\
-  if (TARGET_DEBUG_ADDR)						\
-    {									\
-      fprintf (stderr, msg);						\
-      debug_rtx (insn);							\
-    }									\
-} while (0)
+/* Print an integer constant expression in assembler syntax.  Addition
+   and subtraction are the only arithmetic that may appear in these
+   expressions.  FILE is the stdio stream to write to, X is the rtx, and
+   CODE is the operand print code from the output string.  */
 
-int
-legitimate_address_p (mode, addr, strict)
-     enum machine_mode mode;
-     register rtx addr;
-     int strict;
+static void
+output_pic_addr_const (file, x, code)
+     FILE *file;
+     rtx x;
+     int code;
 {
-  rtx base  = NULL_RTX;
-  rtx indx  = NULL_RTX;
-  rtx scale = NULL_RTX;
-  rtx disp  = NULL_RTX;
-
-  if (TARGET_DEBUG_ADDR)
-    {
-      fprintf (stderr,
-	       "\n==========\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n",
-	       GET_MODE_NAME (mode), strict);
-
-      debug_rtx (addr);
-    }
-
-  if (GET_CODE (addr) == REG || GET_CODE (addr) == SUBREG)
-      base = addr;				/* base reg */
+  char buf[256];
 
-  else if (GET_CODE (addr) == PLUS)
+  switch (GET_CODE (x))
     {
-      rtx op0 = XEXP (addr, 0);
-      rtx op1 = XEXP (addr, 1);
-      enum rtx_code code0 = GET_CODE (op0);
-      enum rtx_code code1 = GET_CODE (op1);
+    case PC:
+      if (flag_pic)
+	putc ('.', file);
+      else
+	abort ();
+      break;
 
-      if (code0 == REG || code0 == SUBREG)
+    case SYMBOL_REF:
+    case LABEL_REF:
+      if (GET_CODE (x) == SYMBOL_REF)
+	assemble_name (file, XSTR (x, 0));
+      else
 	{
-	  if (code1 == REG || code1 == SUBREG)
-	    {
-	      indx = op0;			/* index + base */
-	      base = op1;
-	    }
-
-	  else
-	    {
-	      base = op0;			/* base + displacement */
-	      disp = op1;
-	    }
+	  ASM_GENERATE_INTERNAL_LABEL (buf, "L",
+				       CODE_LABEL_NUMBER (XEXP (x, 0)));
+	  assemble_name (asm_out_file, buf);
 	}
 
-      else if (code0 == MULT)
-	{
-	  indx  = XEXP (op0, 0);
-	  scale = XEXP (op0, 1);
+      if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
+	fprintf (file, "@GOTOFF(%%ebx)");
+      else if (code == 'P')
+	fprintf (file, "@PLT");
+      else if (GET_CODE (x) == LABEL_REF || ! SYMBOL_REF_FLAG (x))
+	fprintf (file, "@GOT");
+      else
+	fprintf (file, "@GOTOFF");
 
-	  if (code1 == REG || code1 == SUBREG)
-	    base = op1;				/* index*scale + base */
+      break;
 
-	  else
-	    disp = op1;				/* index*scale + disp */
-	}
+    case CODE_LABEL:
+      ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
+      assemble_name (asm_out_file, buf);
+      break;
 
-      else if (code0 == PLUS && GET_CODE (XEXP (op0, 0)) == MULT)
-	{
-	  indx  = XEXP (XEXP (op0, 0), 0);	/* index*scale + base + disp */
-	  scale = XEXP (XEXP (op0, 0), 1);
-	  base  = XEXP (op0, 1);
-	  disp  = op1;
-	}
+    case CONST_INT:
+      fprintf (file, "%d", INTVAL (x));
+      break;
 
-      else if (code0 == PLUS)
-	{
-	  indx = XEXP (op0, 0);			/* index + base + disp */
-	  base = XEXP (op0, 1);
-	  disp = op1;
-	}
+    case CONST:
+      /* This used to output parentheses around the expression,
+	 but that does not work on the 386 (either ATT or BSD assembler).  */
+      output_pic_addr_const (file, XEXP (x, 0), code);
+      break;
 
-      else
+    case CONST_DOUBLE:
+      if (GET_MODE (x) == VOIDmode)
 	{
-	  ADDR_INVALID ("PLUS subcode is not valid.\n", op0);
-	  return FALSE;
+	  /* We can use %d if the number is <32 bits and positive.  */
+	  if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
+	    fprintf (file, "0x%x%08x",
+		     CONST_DOUBLE_HIGH (x), CONST_DOUBLE_LOW (x));
+	  else
+	    fprintf (file, "%d", CONST_DOUBLE_LOW (x));
 	}
-    }
-
-  else if (GET_CODE (addr) == MULT)
-    {
-      indx  = XEXP (addr, 0);			/* index*scale */
-      scale = XEXP (addr, 1);
-    }
-
-  else
-    disp = addr;				/* displacement */
-
-  /* Allow arg pointer and stack pointer as index if there is not scaling */
-  if (base && indx && !scale
-      && (indx == arg_pointer_rtx || indx == stack_pointer_rtx))
-    {
-      rtx tmp = base;
-      base = indx;
-      indx = tmp;
-    }
+      else
+	/* We can't handle floating point constants;
+	   PRINT_OPERAND must handle them.  */
+	output_operand_lossage ("floating constant misused");
+      break;
 
-  /* Validate base register */
-  /* Don't allow SUBREG's here, it can lead to spill failures when the base
-     is one word out of a two word structure, which is represented internally
-     as a DImode int.  */
-  if (base)
-    {
-      if (GET_CODE (base) != REG)
+    case PLUS:
+      /* Some assemblers need integer constants to appear last (eg masm).  */
+      if (GET_CODE (XEXP (x, 0)) == CONST_INT)
 	{
-	  ADDR_INVALID ("Base is not a register.\n", base);
-	  return FALSE;
+	  output_pic_addr_const (file, XEXP (x, 1), code);
+	  if (INTVAL (XEXP (x, 0)) >= 0)
+	    fprintf (file, "+");
+	  output_pic_addr_const (file, XEXP (x, 0), code);
 	}
-
-      if ((strict && !REG_OK_FOR_BASE_STRICT_P (base))
-	  || (!strict && !REG_OK_FOR_BASE_NONSTRICT_P (base)))
+      else
 	{
-	  ADDR_INVALID ("Base is not valid.\n", base);
-	  return FALSE;
+	  output_pic_addr_const (file, XEXP (x, 0), code);
+	  if (INTVAL (XEXP (x, 1)) >= 0)
+	    fprintf (file, "+");
+	  output_pic_addr_const (file, XEXP (x, 1), code);
 	}
-    }
+      break;
 
-  /* Validate index register */
-  /* Don't allow SUBREG's here, it can lead to spill failures when the index
-     is one word out of a two word structure, which is represented internally
-     as a DImode int.  */
-  if (indx)
-    {
-      if (GET_CODE (indx) != REG)
-	{
-	  ADDR_INVALID ("Index is not a register.\n", indx);
-	  return FALSE;
-	}
+    case MINUS:
+      output_pic_addr_const (file, XEXP (x, 0), code);
+      fprintf (file, "-");
+      output_pic_addr_const (file, XEXP (x, 1), code);
+      break;
 
-      if ((strict && !REG_OK_FOR_INDEX_STRICT_P (indx))
-	  || (!strict && !REG_OK_FOR_INDEX_NONSTRICT_P (indx)))
-	{
-	  ADDR_INVALID ("Index is not valid.\n", indx);
-	  return FALSE;
-	}
+    default:
+      output_operand_lossage ("invalid expression as operand");
     }
-  else if (scale)
-    abort ();					/* scale w/o index illegal */
+}
+
+/* Meaning of CODE:
+   f -- float insn (print a CONST_DOUBLE as a float rather than in hex).
+   D,L,W,B,Q,S -- print the opcode suffix for specified size of operand.
+   R -- print the prefix for register names.
+   z -- print the opcode suffix for the size of the current operand.
+   * -- print a star (in certain assembler syntax)
+   w -- print the operand as if it's a "word" (HImode) even if it isn't.
+   c -- don't print special prefixes before constant operands.
+*/
 
-  /* Validate scale factor */
-  if (scale)
+void
+print_operand (file, x, code)
+     FILE *file;
+     rtx x;
+     int code;
+{
+  if (code)
     {
-      HOST_WIDE_INT value;
-
-      if (GET_CODE (scale) != CONST_INT)
+      switch (code)
 	{
-	  ADDR_INVALID ("Scale is not valid.\n", scale);
-	  return FALSE;
-	}
+	case '*':
+	  if (USE_STAR)
+	    putc ('*', file);
+	  return;
 
-      value = INTVAL (scale);
-      if (value != 1 && value != 2 && value != 4 && value != 8)
-	{
-	  ADDR_INVALID ("Scale is not a good multiplier.\n", scale);
-	  return FALSE;
-	}
-    }
+	case 'L':
+	  PUT_OP_SIZE (code, 'l', file);
+	  return;
 
-  /* Validate displacement */
-  if (disp)
-    {
-      if (!CONSTANT_ADDRESS_P (disp))
-	{
-	  ADDR_INVALID ("Displacement is not valid.\n", disp);
-	  return FALSE;
-	}
+	case 'W':
+	  PUT_OP_SIZE (code, 'w', file);
+	  return;
 
-      if (GET_CODE (disp) == CONST_DOUBLE)
-	{
-	  ADDR_INVALID ("Displacement is a const_double.\n", disp);
-	  return FALSE;
-	}
+	case 'B':
+	  PUT_OP_SIZE (code, 'b', file);
+	  return;
 
-      if (flag_pic && SYMBOLIC_CONST (disp) && base != pic_offset_table_rtx
-	  && (indx != pic_offset_table_rtx || scale != NULL_RTX))
-	{
-	  ADDR_INVALID ("Displacement is an invalid pic reference.\n", disp);
-	  return FALSE;
-	}
+	case 'Q':
+	  PUT_OP_SIZE (code, 'l', file);
+	  return;
 
-      if (HALF_PIC_P () && HALF_PIC_ADDRESS_P (disp)
-	  && (base != NULL_RTX || indx != NULL_RTX))
-	{
-	  ADDR_INVALID ("Displacement is an invalid half-pic reference.\n", disp);
-	  return FALSE;
-	}
-    }
+	case 'S':
+	  PUT_OP_SIZE (code, 's', file);
+	  return;
 
-  if (TARGET_DEBUG_ADDR)
-    fprintf (stderr, "Address is valid.\n");
+	case 'T':
+	  PUT_OP_SIZE (code, 't', file);
+	  return;
 
-  /* Everything looks valid, return true */
-  return TRUE;
-}
+	case 'z':
+	  /* 387 opcodes don't get size suffixes if the operands are
+	     registers. */
 
-
-/* Return a legitimate reference for ORIG (an address) using the
-   register REG.  If REG is 0, a new pseudo is generated.
+	  if (STACK_REG_P (x))
+	    return;
 
-   There are three types of references that must be handled:
+	  /* this is the size of op from size of operand */
+	  switch (GET_MODE_SIZE (GET_MODE (x)))
+	    {
+	    case 1:
+	      PUT_OP_SIZE ('B', 'b', file);
+	      return;
 
-   1. Global data references must load the address from the GOT, via
-      the PIC reg.  An insn is emitted to do this load, and the reg is
-      returned.
+	    case 2:
+	      PUT_OP_SIZE ('W', 'w', file);
+	      return;
 
-   2. Static data references must compute the address as an offset
-      from the GOT, whose base is in the PIC reg.  An insn is emitted to
-      compute the address into a reg, and the reg is returned.  Static
-      data objects have SYMBOL_REF_FLAG set to differentiate them from
-      global data objects.
+	    case 4:
+	      if (GET_MODE (x) == SFmode)
+		{
+		  PUT_OP_SIZE ('S', 's', file);
+		  return;
+		}
+	      else
+		PUT_OP_SIZE ('L', 'l', file);
+	      return;
 
-   3. Constant pool addresses must be handled special.  They are
-      considered legitimate addresses, but only if not used with regs.
-      When printed, the output routines know to print the reference with the
-      PIC reg, even though the PIC reg doesn't appear in the RTL.
+	    case 12:
+		  PUT_OP_SIZE ('T', 't', file);
+		  return;
 
-   GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
-   reg also appears in the address (except for constant pool references,
-   noted above).
+	    case 8:
+	      if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
+		{
+#ifdef GAS_MNEMONICS
+		  PUT_OP_SIZE ('Q', 'q', file);
+		  return;
+#else
+		  PUT_OP_SIZE ('Q', 'l', file);	/* Fall through */
+#endif
+		}
 
-   "switch" statements also require special handling when generating
-   PIC code.  See comments by the `casesi' insn in i386.md for details.  */
+	      PUT_OP_SIZE ('Q', 'l', file);
+	      return;
+	    }
 
-rtx
-legitimize_pic_address (orig, reg)
-     rtx orig;
-     rtx reg;
-{
-  rtx addr = orig;
-  rtx new = orig;
+	case 'b':
+	case 'w':
+	case 'k':
+	case 'h':
+	case 'y':
+	case 'P':
+	  break;
 
-  if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
-    {
-      if (GET_CODE (addr) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (addr))
-	reg = new = orig;
-      else
-	{
-	  if (reg == 0)
-	    reg = gen_reg_rtx (Pmode);
+	default:
+	  {
+	    char str[50];
 
-	  if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_FLAG (addr))
-	      || GET_CODE (addr) == LABEL_REF)
-	    new = gen_rtx (PLUS, Pmode, pic_offset_table_rtx, orig);
-	  else
-	    new = gen_rtx (MEM, Pmode,
-			   gen_rtx (PLUS, Pmode,
-				    pic_offset_table_rtx, orig));
-
-	  emit_move_insn (reg, new);
+	    sprintf (str, "invalid operand code `%c'", code);
+	    output_operand_lossage (str);
+	  }
 	}
-      current_function_uses_pic_offset_table = 1;
-      return reg;
     }
-  else if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS)
+  if (GET_CODE (x) == REG)
     {
-      rtx base;
-
-      if (GET_CODE (addr) == CONST)
+      PRINT_REG (x, code, file);
+    }
+  else if (GET_CODE (x) == MEM)
+    {
+      PRINT_PTR (x, file);
+      if (CONSTANT_ADDRESS_P (XEXP (x, 0)))
 	{
-	  addr = XEXP (addr, 0);
-	  if (GET_CODE (addr) != PLUS)
-	    abort ();
+	  if (flag_pic)
+	    output_pic_addr_const (file, XEXP (x, 0), code);
+	  else
+	    output_addr_const (file, XEXP (x, 0));
 	}
-
-      if (XEXP (addr, 0) == pic_offset_table_rtx)
-	return orig;
-
-      if (reg == 0)
-	reg = gen_reg_rtx (Pmode);
-
-      base = legitimize_pic_address (XEXP (addr, 0), reg);
-      addr = legitimize_pic_address (XEXP (addr, 1),
-				     base == reg ? NULL_RTX : reg);
-
-      if (GET_CODE (addr) == CONST_INT)
-	return plus_constant (base, INTVAL (addr));
-
-      if (GET_CODE (addr) == PLUS && CONSTANT_P (XEXP (addr, 1)))
+      else
+	output_address (XEXP (x, 0));
+    }
+  else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
+    {
+      REAL_VALUE_TYPE r; long l;
+      REAL_VALUE_FROM_CONST_DOUBLE (r, x);
+      REAL_VALUE_TO_TARGET_SINGLE (r, l);
+      PRINT_IMMED_PREFIX (file);
+      fprintf (file, "0x%x", l);
+    }
+ /* These float cases don't actually occur as immediate operands. */
+ else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
+    {
+      REAL_VALUE_TYPE r; char dstr[30];
+      REAL_VALUE_FROM_CONST_DOUBLE (r, x);
+      REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
+      fprintf (file, "%s", dstr);
+    }
+  else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == XFmode)
+    {
+      REAL_VALUE_TYPE r; char dstr[30];
+      REAL_VALUE_FROM_CONST_DOUBLE (r, x);
+      REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
+      fprintf (file, "%s", dstr);
+    }
+  else 
+    {
+      if (code != 'P')
 	{
-	  base = gen_rtx (PLUS, Pmode, base, XEXP (addr, 0));
-	  addr = XEXP (addr, 1);
+	  if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
+	    PRINT_IMMED_PREFIX (file);
+	  else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
+		   || GET_CODE (x) == LABEL_REF)
+	    PRINT_OFFSET_PREFIX (file);
 	}
-	return gen_rtx (PLUS, Pmode, base, addr);
+      if (flag_pic)
+	output_pic_addr_const (file, x, code);
+      else
+	output_addr_const (file, x);
     }
-  return new;
 }
 
-
-/* Emit insns to move operands[1] into operands[0].  */
+/* Print a memory operand whose address is ADDR.  */
 
 void
-emit_pic_move (operands, mode)
-     rtx *operands;
-     enum machine_mode mode;
-{
-  rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
-
-  if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1]))
-    operands[1] = (rtx) force_reg (SImode, operands[1]);
-  else
-    operands[1] = legitimize_pic_address (operands[1], temp);
-}
-
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.
-
-   For the 80386, we handle X+REG by loading X into a register R and
-   using R+REG.  R will go in a general reg and indexing will be used.
-   However, if REG is a broken-out memory address or multiplication,
-   nothing needs to be done because REG can certainly go in a general reg.
-
-   When -fpic is used, special handling is needed for symbolic references.
-   See comments by legitimize_pic_address in i386.c for details.  */
-
-rtx
-legitimize_address (x, oldx, mode)
-     register rtx x;
-     register rtx oldx;
-     enum machine_mode mode;
+print_operand_address (file, addr)
+     FILE *file;
+     register rtx addr;
 {
-  int changed = 0;
-  unsigned log;
-
-  if (TARGET_DEBUG_ADDR)
-    {
-      fprintf (stderr, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n", GET_MODE_NAME (mode));
-      debug_rtx (x);
-    }
-
-  if (flag_pic && SYMBOLIC_CONST (x))
-    return legitimize_pic_address (x, 0);
+  register rtx reg1, reg2, breg, ireg;
+  rtx offset;
 
-  /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
-  if (GET_CODE (x) == ASHIFT
-      && GET_CODE (XEXP (x, 1)) == CONST_INT
-      && (log = (unsigned)exact_log2 (INTVAL (XEXP (x, 1)))) < 4)
+  switch (GET_CODE (addr))
     {
-      changed = 1;
-      x = gen_rtx (MULT, Pmode,
-		   force_reg (Pmode, XEXP (x, 0)),
-		   GEN_INT (1 << log));
-    }
+    case REG:
+      ADDR_BEG (file);
+      fprintf (file, "%se", RP);
+      fputs (hi_reg_name[REGNO (addr)], file);
+      ADDR_END (file);
+      break;
 
-  if (GET_CODE (x) == PLUS)
-    {
-      /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
-      if (GET_CODE (XEXP (x, 0)) == ASHIFT
-	  && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
-	  && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) < 4)
+    case PLUS:
+      reg1 = 0;
+      reg2 = 0;
+      ireg = 0;
+      breg = 0;
+      offset = 0;
+      if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))
 	{
-	  changed = 1;
-	  XEXP (x, 0) = gen_rtx (MULT, Pmode,
-				 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
-				 GEN_INT (1 << log));
+	  offset = XEXP (addr, 0);
+	  addr = XEXP (addr, 1);
 	}
-
-      if (GET_CODE (XEXP (x, 1)) == ASHIFT
-	  && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
-	  && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1)))) < 4)
+      else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))
 	{
-	  changed = 1;
-	  XEXP (x, 1) = gen_rtx (MULT, Pmode,
-				 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
-				 GEN_INT (1 << log));
+	  offset = XEXP (addr, 1);
+	  addr = XEXP (addr, 0);
 	}
-
-      /* Put multiply first if it isn't already */
-      if (GET_CODE (XEXP (x, 1)) == MULT)
+      if (GET_CODE (addr) != PLUS) ;
+      else if (GET_CODE (XEXP (addr, 0)) == MULT)
 	{
-	  rtx tmp = XEXP (x, 0);
-	  XEXP (x, 0) = XEXP (x, 1);
-	  XEXP (x, 1) = tmp;
-	  changed = 1;
+	  reg1 = XEXP (addr, 0);
+	  addr = XEXP (addr, 1);
 	}
-
-      /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
-	 into (plus (plus (mult (reg) (const)) (reg)) (const)).  This can be
-	 created by virtual register instantiation, register elimination, and
-	 similar optimizations.  */
-      if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
+      else if (GET_CODE (XEXP (addr, 1)) == MULT)
+	{
+	  reg1 = XEXP (addr, 1);
+	  addr = XEXP (addr, 0);
+	}
+      else if (GET_CODE (XEXP (addr, 0)) == REG)
+	{
+	  reg1 = XEXP (addr, 0);
+	  addr = XEXP (addr, 1);
+	}
+      else if (GET_CODE (XEXP (addr, 1)) == REG)
+	{
+	  reg1 = XEXP (addr, 1);
+	  addr = XEXP (addr, 0);
+	}
+      if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT)
+	{
+	  if (reg1 == 0) reg1 = addr;
+	  else reg2 = addr;
+	  addr = 0;
+	}
+      if (offset != 0)
+	{
+	  if (addr != 0) abort ();
+	  addr = offset;
+	}
+      if ((reg1 && GET_CODE (reg1) == MULT)
+	  || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))
+	{
+	  breg = reg2;
+	  ireg = reg1;
+	}
+      else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))
 	{
-	  changed = 1;
-	  x = gen_rtx (PLUS, Pmode,
-		       gen_rtx (PLUS, Pmode, XEXP (x, 0), XEXP (XEXP (x, 1), 0)),
-		       XEXP (XEXP (x, 1), 1));
+	  breg = reg1;
+	  ireg = reg2;
 	}
 
-      /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
-	 into (plus (plus (mult (reg) (const)) (reg)) (const)).  */
-      else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
-	       && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
-	       && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
-	       && CONSTANT_P (XEXP (x, 1)))
+      if (ireg != 0 || breg != 0)
 	{
-	  rtx constant, other;
+	  int scale = 1;
 
-	  if (GET_CODE (XEXP (x, 1)) == CONST_INT)
-	    {
-	      constant = XEXP (x, 1);
-	      other = XEXP (XEXP (XEXP (x, 0), 1), 1);
-	    }
-	  else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
+	  if (addr != 0)
 	    {
-	      constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
-	      other = XEXP (x, 1);
+	      if (GET_CODE (addr) == LABEL_REF)
+		output_asm_label (addr);
+	      else
+		{
+		  if (flag_pic)
+		    output_pic_addr_const (file, addr, 0);
+		  else
+		    output_addr_const (file, addr);
+		}
 	    }
-	  else
-	    constant = 0;
 
-	  if (constant)
+  	  if (ireg != 0 && GET_CODE (ireg) == MULT)
 	    {
-	      changed = 1;
-	      x = gen_rtx (PLUS, Pmode,
-			   gen_rtx (PLUS, Pmode, XEXP (XEXP (x, 0), 0),
-				    XEXP (XEXP (XEXP (x, 0), 1), 0)),
-			   plus_constant (other, INTVAL (constant)));
+	      scale = INTVAL (XEXP (ireg, 1));
+	      ireg = XEXP (ireg, 0);
 	    }
-	}
 
-      if (changed && legitimate_address_p (mode, x, FALSE))
-	return x;
-
-      if (GET_CODE (XEXP (x, 0)) == MULT)
-	{
-	  changed = 1;
-	  XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
-	}
+	  /* The stack pointer can only appear as a base register,
+	     never an index register, so exchange the regs if it is wrong. */
 
-      if (GET_CODE (XEXP (x, 1)) == MULT)
-	{
-	  changed = 1;
-	  XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
-	}
+	  if (scale == 1 && ireg && REGNO (ireg) == STACK_POINTER_REGNUM)
+	    {
+	      rtx tmp;
 
-      if (changed
-	  && GET_CODE (XEXP (x, 1)) == REG
-	  && GET_CODE (XEXP (x, 0)) == REG)
-	return x;
+	      tmp = breg;
+	      breg = ireg;
+	      ireg = tmp;
+	    }
 
-      if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
-	{
-	  changed = 1;
-	  x = legitimize_pic_address (x, 0);
+	  /* output breg+ireg*scale */
+	  PRINT_B_I_S (breg, ireg, scale, file);
+	  break;
 	}
 
-      if (changed && legitimate_address_p (mode, x, FALSE))
-	return x;
-
-      if (GET_CODE (XEXP (x, 0)) == REG)
-	{
-	  register rtx temp = gen_reg_rtx (Pmode);
-	  register rtx val  = force_operand (XEXP (x, 1), temp);
-	  if (val != temp)
-	    emit_move_insn (temp, val);
-
-	  XEXP (x, 1) = temp;
-	  return x;
-	}
+    case MULT:
+      {
+	int scale;
+	if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
+	  {
+	    scale = INTVAL (XEXP (addr, 0));
+	    ireg = XEXP (addr, 1);
+	  }
+	else
+	  {
+	    scale = INTVAL (XEXP (addr, 1));
+	    ireg = XEXP (addr, 0);
+	  }
+	output_addr_const (file, const0_rtx);
+	PRINT_B_I_S ((rtx) 0, ireg, scale, file);
+      }
+      break;
 
-      else if (GET_CODE (XEXP (x, 1)) == REG)
+    default:
+      if (GET_CODE (addr) == CONST_INT
+	  && INTVAL (addr) < 0x8000
+	  && INTVAL (addr) >= -0x8000)
+	fprintf (file, "%d", INTVAL (addr));
+      else
 	{
-	  register rtx temp = gen_reg_rtx (Pmode);
-	  register rtx val  = force_operand (XEXP (x, 0), temp);
-	  if (val != temp)
-	    emit_move_insn (temp, val);
-
-	  XEXP (x, 0) = temp;
-	  return x;
+	  if (flag_pic)
+	    output_pic_addr_const (file, addr, 0);
+	  else
+	    output_addr_const (file, addr);
 	}
     }
-
-  return x;
 }
-
 
-/* Print an integer constant expression in assembler syntax.  Addition
-   and subtraction are the only arithmetic that may appear in these
-   expressions.  FILE is the stdio stream to write to, X is the rtx, and
-   CODE is the operand print code from the output string.  */
+/* Set the cc_status for the results of an insn whose pattern is EXP.
+   On the 80386, we assume that only test and compare insns, as well
+   as SI, HI, & DI mode ADD, SUB, NEG, AND, IOR, XOR, ASHIFT, LSHIFT,
+   ASHIFTRT, and LSHIFTRT instructions set the condition codes usefully.
+   Also, we assume that jumps, moves and sCOND don't affect the condition
+   codes.  All else clobbers the condition codes, by assumption.
 
-static void
-output_pic_addr_const (file, x, code)
-     FILE *file;
-     rtx x;
-     int code;
-{
-  char buf[256];
+   We assume that ALL integer add, minus, etc. instructions effect the
+   condition codes.  This MUST be consistent with i386.md.
 
-  switch (GET_CODE (x))
-    {
-    case PC:
-      if (flag_pic)
-	putc ('.', file);
-      else
-	abort ();
-      break;
+   We don't record any float test or compare - the redundant test &
+   compare check in final.c does not handle stack-like regs correctly. */
 
-    case SYMBOL_REF:
-    case LABEL_REF:
-      if (GET_CODE (x) == SYMBOL_REF)
-	assemble_name (file, XSTR (x, 0));
-      else
+void
+notice_update_cc (exp)
+     rtx exp;
+{
+  if (GET_CODE (exp) == SET)
+    {
+      /* Jumps do not alter the cc's.  */
+      if (SET_DEST (exp) == pc_rtx)
+	return;
+#ifdef IS_STACK_MODE
+      /* intel1 
+         Moving into a memory of stack_mode may have been moved
+         in between the use and set of cc0 by loop_spl(). So
+         old value of cc.status must be retained */
+      if(GET_CODE(SET_DEST(exp))==MEM 
+         && IS_STACK_MODE(GET_MODE(SET_DEST(exp))))
+        {
+          return;
+        }
+#endif
+      /* Moving register or memory into a register:
+	 it doesn't alter the cc's, but it might invalidate
+	 the RTX's which we remember the cc's came from.
+	 (Note that moving a constant 0 or 1 MAY set the cc's).  */
+      if (REG_P (SET_DEST (exp))
+	  && (REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == MEM
+	      || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'))
 	{
-	  ASM_GENERATE_INTERNAL_LABEL (buf, "L",
-				       CODE_LABEL_NUMBER (XEXP (x, 0)));
-	  assemble_name (asm_out_file, buf);
+	  if (cc_status.value1
+	      && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1))
+	    cc_status.value1 = 0;
+	  if (cc_status.value2
+	      && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2))
+	    cc_status.value2 = 0;
+	  return;
 	}
-
-      if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
-	fprintf (file, "@GOTOFF(%%ebx)");
-      else if (code == 'P')
-	fprintf (file, "@PLT");
-      else if (GET_CODE (x) == LABEL_REF)
-	fprintf (file, "@GOTOFF");
-      else if (! SYMBOL_REF_FLAG (x))
-	fprintf (file, "@GOT");
-      else
-	fprintf (file, "@GOTOFF");
-
-      break;
-
-    case CODE_LABEL:
-      ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
-      assemble_name (asm_out_file, buf);
-      break;
-
-    case CONST_INT:
-      fprintf (file, "%d", INTVAL (x));
-      break;
-
-    case CONST:
-      /* This used to output parentheses around the expression,
-	 but that does not work on the 386 (either ATT or BSD assembler).  */
-      output_pic_addr_const (file, XEXP (x, 0), code);
-      break;
-
-    case CONST_DOUBLE:
-      if (GET_MODE (x) == VOIDmode)
+      /* Moving register into memory doesn't alter the cc's.
+	 It may invalidate the RTX's which we remember the cc's came from.  */
+      if (GET_CODE (SET_DEST (exp)) == MEM
+	  && (REG_P (SET_SRC (exp))
+	      || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'))
 	{
-	  /* We can use %d if the number is <32 bits and positive.  */
-	  if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
-	    fprintf (file, "0x%x%08x",
-		     CONST_DOUBLE_HIGH (x), CONST_DOUBLE_LOW (x));
-	  else
-	    fprintf (file, "%d", CONST_DOUBLE_LOW (x));
+	  if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM)
+	    cc_status.value1 = 0;
+	  if (cc_status.value2 && GET_CODE (cc_status.value2) == MEM)
+	    cc_status.value2 = 0;
+	  return;
 	}
-      else
-	/* We can't handle floating point constants;
-	   PRINT_OPERAND must handle them.  */
-	output_operand_lossage ("floating constant misused");
-      break;
-
-    case PLUS:
-      /* Some assemblers need integer constants to appear last (eg masm).  */
-      if (GET_CODE (XEXP (x, 0)) == CONST_INT)
+      /* Function calls clobber the cc's.  */
+      else if (GET_CODE (SET_SRC (exp)) == CALL)
 	{
-	  output_pic_addr_const (file, XEXP (x, 1), code);
-	  if (INTVAL (XEXP (x, 0)) >= 0)
-	    fprintf (file, "+");
-	  output_pic_addr_const (file, XEXP (x, 0), code);
+	  CC_STATUS_INIT;
+	  return;
 	}
-      else
+      /* Tests and compares set the cc's in predictable ways.  */
+      else if (SET_DEST (exp) == cc0_rtx)
 	{
-	  output_pic_addr_const (file, XEXP (x, 0), code);
-	  if (INTVAL (XEXP (x, 1)) >= 0)
-	    fprintf (file, "+");
-	  output_pic_addr_const (file, XEXP (x, 1), code);
+	  CC_STATUS_INIT;
+	  cc_status.value1 = SET_SRC (exp);
+	  return;
 	}
-      break;
+      /* Certain instructions effect the condition codes. */
+      else if (GET_MODE (SET_SRC (exp)) == SImode
+	       || GET_MODE (SET_SRC (exp)) == HImode
+	       || GET_MODE (SET_SRC (exp)) == QImode)
+	switch (GET_CODE (SET_SRC (exp)))
+	  {
+	  case ASHIFTRT: case LSHIFTRT:
+	  case ASHIFT: case LSHIFT:
+	    /* Shifts on the 386 don't set the condition codes if the
+	       shift count is zero. */
+	    if (GET_CODE (XEXP (SET_SRC (exp), 1)) != CONST_INT)
+	      {
+		CC_STATUS_INIT;
+		break;
+	      }
+	    /* We assume that the CONST_INT is non-zero (this rtx would
+	       have been deleted if it were zero. */
 
-    case MINUS:
-      output_pic_addr_const (file, XEXP (x, 0), code);
-      fprintf (file, "-");
-      output_pic_addr_const (file, XEXP (x, 1), code);
-      break;
+	  case PLUS: case MINUS: case NEG:
+	  case AND: case IOR: case XOR:
+	    cc_status.flags = CC_NO_OVERFLOW;
+	    cc_status.value1 = SET_SRC (exp);
+	    cc_status.value2 = SET_DEST (exp);
+	    break;
 
-    default:
-      output_operand_lossage ("invalid expression as operand");
+	  default:
+	    CC_STATUS_INIT;
+	  }
+      else
+	{
+	  CC_STATUS_INIT;
+	}
+    }
+  else if (GET_CODE (exp) == PARALLEL
+	   && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
+    {
+      if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx)
+	return;
+      if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx)
+	{
+	  CC_STATUS_INIT;
+	  if (stack_regs_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0))))
+	    cc_status.flags |= CC_IN_80387;
+	  else
+	    cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0));
+	  return;
+	}
+      CC_STATUS_INIT;
+    }
+  else
+    {
+      CC_STATUS_INIT;
     }
 }
 
-/* Meaning of CODE:
-   f -- float insn (print a CONST_DOUBLE as a float rather than in hex).
-   D,L,W,B,Q,S -- print the opcode suffix for specified size of operand.
-   R -- print the prefix for register names.
-   z -- print the opcode suffix for the size of the current operand.
-   * -- print a star (in certain assembler syntax)
-   w -- print the operand as if it's a "word" (HImode) even if it isn't.
-   c -- don't print special prefixes before constant operands.
-*/
+/* Split one or more DImode RTL references into pairs of SImode
+   references.  The RTL can be REG, offsettable MEM, integer constant, or
+   CONST_DOUBLE.  "operands" is a pointer to an array of DImode RTL to
+   split and "num" is its length.  lo_half and hi_half are output arrays
+   that parallel "operands". */
 
 void
-print_operand (file, x, code)
-     FILE *file;
-     rtx x;
-     int code;
+split_di (operands, num, lo_half, hi_half)
+     rtx operands[];
+     int num;
+     rtx lo_half[], hi_half[];
 {
-  if (code)
+  while (num--)
     {
-      switch (code)
+      if (GET_CODE (operands[num]) == REG)
 	{
-	case '*':
-	  if (USE_STAR)
-	    putc ('*', file);
-	  return;
+	  lo_half[num] = gen_rtx (REG, SImode, REGNO (operands[num]));
+	  hi_half[num] = gen_rtx (REG, SImode, REGNO (operands[num]) + 1);
+	}
+      else if (CONSTANT_P (operands[num]))
+	{
+	  split_double (operands[num], &lo_half[num], &hi_half[num]);
+	}
+      else if (offsettable_memref_p (operands[num]))
+	{
+	  lo_half[num] = operands[num];
+	  hi_half[num] = adj_offsettable_operand (operands[num], 4);
+	}
+      else
+	abort();
+    }
+}
+
+/* Return 1 if this is a valid binary operation on a 387.
+   OP is the expression matched, and MODE is its mode. */
 
-	case 'L':
-	  PUT_OP_SIZE (code, 'l', file);
-	  return;
+int
+binary_387_op (op, mode)
+    register rtx op;
+    enum machine_mode mode;
+{
+  if (mode != VOIDmode && mode != GET_MODE (op))
+    return 0;
 
-	case 'W':
-	  PUT_OP_SIZE (code, 'w', file);
-	  return;
+  switch (GET_CODE (op))
+    {
+    case PLUS:
+    case MINUS:
+    case MULT:
+    case DIV:
+      return GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT;
 
-	case 'B':
-	  PUT_OP_SIZE (code, 'b', file);
-	  return;
+    default:
+      return 0;
+    }
+}
 
-	case 'Q':
-	  PUT_OP_SIZE (code, 'l', file);
-	  return;
+/* Return 1 if this is a valid conversion operation on a 387.
+   OP is the expression matched, and MODE is its mode. */
 
-	case 'S':
-	  PUT_OP_SIZE (code, 's', file);
-	  return;
+int
+convert_387_op (op, mode)
+    register rtx op;
+    enum machine_mode mode;
+{
+  if (mode != VOIDmode && mode != GET_MODE (op))
+    return 0;
 
-	case 'T':
-	  PUT_OP_SIZE (code, 't', file);
-	  return;
+  switch (GET_CODE (op))
+    {
+    case FLOAT:
+      return GET_MODE (XEXP (op, 0)) == SImode;
 
-	case 'z':
-	  /* 387 opcodes don't get size suffixes if the operands are
-	     registers. */
+    case FLOAT_EXTEND:
+      return ((mode == DFmode && GET_MODE (XEXP (op, 0)) == SFmode)
+	      || (mode == XFmode && GET_MODE (XEXP (op, 0)) == DFmode)
+	      || (mode == XFmode && GET_MODE (XEXP (op, 0)) == SFmode));
 
-	  if (STACK_REG_P (x))
-	    return;
+    default:
+      return 0;
+    }
+}
 
-	  /* this is the size of op from size of operand */
-	  switch (GET_MODE_SIZE (GET_MODE (x)))
-	    {
-	    case 1:
-	      PUT_OP_SIZE ('B', 'b', file);
-	      return;
+/* Return 1 if this is a valid shift or rotate operation on a 386.
+   OP is the expression matched, and MODE is its mode. */
 
-	    case 2:
-	      PUT_OP_SIZE ('W', 'w', file);
-	      return;
+int
+shift_op (op, mode)
+    register rtx op;
+    enum machine_mode mode;
+{
+  rtx operand = XEXP (op, 0);
 
-	    case 4:
-	      if (GET_MODE (x) == SFmode)
-		{
-		  PUT_OP_SIZE ('S', 's', file);
-		  return;
-		}
-	      else
-		PUT_OP_SIZE ('L', 'l', file);
-	      return;
+  if (mode != VOIDmode && mode != GET_MODE (op))
+    return 0;
 
-	    case 12:
-		  PUT_OP_SIZE ('T', 't', file);
-		  return;
+  if (GET_MODE (operand) != GET_MODE (op)
+      || GET_MODE_CLASS (GET_MODE (op)) != MODE_INT)
+    return 0;
 
-	    case 8:
-	      if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
-		{
-#ifdef GAS_MNEMONICS
-		  PUT_OP_SIZE ('Q', 'q', file);
-		  return;
-#else
-		  PUT_OP_SIZE ('Q', 'l', file);	/* Fall through */
-#endif
-		}
+  return (GET_CODE (op) == ASHIFT
+	  || GET_CODE (op) == ASHIFTRT
+	  || GET_CODE (op) == LSHIFTRT
+	  || GET_CODE (op) == ROTATE
+	  || GET_CODE (op) == ROTATERT);
+}
 
-	      PUT_OP_SIZE ('Q', 'l', file);
-	      return;
-	    }
+/* Return 1 if OP is COMPARE rtx with mode VOIDmode.
+   MODE is not used.  */
 
-	case 'b':
-	case 'w':
-	case 'k':
-	case 'h':
-	case 'y':
-	case 'P':
-	  break;
+int
+VOIDmode_compare_op (op, mode)
+    register rtx op;
+    enum machine_mode mode;
+{
+  return GET_CODE (op) == COMPARE && GET_MODE (op) == VOIDmode;
+}
+
+/* Output code to perform a 387 binary operation in INSN, one of PLUS,
+   MINUS, MULT or DIV.  OPERANDS are the insn operands, where operands[3]
+   is the expression of the binary operation.  The output may either be
+   emitted here, or returned to the caller, like all output_* functions.
 
-	default:
-	  {
-	    char str[50];
+   There is no guarantee that the operands are the same mode, as they
+   might be within FLOAT or FLOAT_EXTEND expressions. */
 
-	    sprintf (str, "invalid operand code `%c'", code);
-	    output_operand_lossage (str);
-	  }
-	}
-    }
-  if (GET_CODE (x) == REG)
-    {
-      PRINT_REG (x, code, file);
-    }
-  else if (GET_CODE (x) == MEM)
+char *
+output_387_binary_op (insn, operands)
+     rtx insn;
+     rtx *operands;
+{
+  rtx temp;
+  char *base_op;
+  static char buf[100];
+
+  switch (GET_CODE (operands[3]))
     {
-      PRINT_PTR (x, file);
-      if (CONSTANT_ADDRESS_P (XEXP (x, 0)))
-	{
-	  if (flag_pic)
-	    output_pic_addr_const (file, XEXP (x, 0), code);
-	  else
-	    output_addr_const (file, XEXP (x, 0));
-	}
+    case PLUS:
+      if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
+	  || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
+	base_op = "fiadd";
       else
-	output_address (XEXP (x, 0));
-    }
-  else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
-    {
-      REAL_VALUE_TYPE r; long l;
-      REAL_VALUE_FROM_CONST_DOUBLE (r, x);
-      REAL_VALUE_TO_TARGET_SINGLE (r, l);
-      PRINT_IMMED_PREFIX (file);
-      fprintf (file, "0x%x", l);
-    }
- /* These float cases don't actually occur as immediate operands. */
- else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
-    {
-      REAL_VALUE_TYPE r; char dstr[30];
-      REAL_VALUE_FROM_CONST_DOUBLE (r, x);
-      REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
-      fprintf (file, "%s", dstr);
-    }
-  else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == XFmode)
-    {
-      REAL_VALUE_TYPE r; char dstr[30];
-      REAL_VALUE_FROM_CONST_DOUBLE (r, x);
-      REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
-      fprintf (file, "%s", dstr);
-    }
-  else 
-    {
-      if (code != 'P')
-	{
-	  if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
-	    PRINT_IMMED_PREFIX (file);
-	  else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
-		   || GET_CODE (x) == LABEL_REF)
-	    PRINT_OFFSET_PREFIX (file);
-	}
-      if (flag_pic)
-	output_pic_addr_const (file, x, code);
+	base_op = "fadd";
+      break;
+
+    case MINUS:
+      if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
+	  || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
+	base_op = "fisub";
       else
-	output_addr_const (file, x);
-    }
-}
-
-/* Print a memory operand whose address is ADDR.  */
+	base_op = "fsub";
+      break;
 
-void
-print_operand_address (file, addr)
-     FILE *file;
-     register rtx addr;
-{
-  register rtx reg1, reg2, breg, ireg;
-  rtx offset;
+    case MULT:
+      if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
+	  || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
+	base_op = "fimul";
+      else
+	base_op = "fmul";
+      break;
 
-  switch (GET_CODE (addr))
-    {
-    case REG:
-      ADDR_BEG (file);
-      fprintf (file, "%se", RP);
-      fputs (hi_reg_name[REGNO (addr)], file);
-      ADDR_END (file);
+    case DIV:
+      if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
+	  || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
+	base_op = "fidiv";
+      else
+	base_op = "fdiv";
       break;
 
+    default:
+      abort ();
+    }
+
+  strcpy (buf, base_op);
+
+  switch (GET_CODE (operands[3]))
+    {
+    case MULT:
     case PLUS:
-      reg1 = 0;
-      reg2 = 0;
-      ireg = 0;
-      breg = 0;
-      offset = 0;
-      if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))
+      if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
 	{
-	  offset = XEXP (addr, 0);
-	  addr = XEXP (addr, 1);
+	  temp = operands[2];
+	  operands[2] = operands[1];
+	  operands[1] = temp;
 	}
-      else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))
+
+      if (GET_CODE (operands[2]) == MEM)
+	return strcat (buf, AS1 (%z2,%2));
+
+      if (NON_STACK_REG_P (operands[1]))
 	{
-	  offset = XEXP (addr, 1);
-	  addr = XEXP (addr, 0);
+	  output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1)));
+	  RET;
 	}
-      if (GET_CODE (addr) != PLUS) ;
-      else if (GET_CODE (XEXP (addr, 0)) == MULT)
+      else if (NON_STACK_REG_P (operands[2]))
 	{
-	  reg1 = XEXP (addr, 0);
-	  addr = XEXP (addr, 1);
+	  output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1)));
+	  RET;
 	}
-      else if (GET_CODE (XEXP (addr, 1)) == MULT)
-	{
-	  reg1 = XEXP (addr, 1);
-	  addr = XEXP (addr, 0);
-	}
-      else if (GET_CODE (XEXP (addr, 0)) == REG)
-	{
-	  reg1 = XEXP (addr, 0);
-	  addr = XEXP (addr, 1);
-	}
-      else if (GET_CODE (XEXP (addr, 1)) == REG)
-	{
-	  reg1 = XEXP (addr, 1);
-	  addr = XEXP (addr, 0);
-	}
-      if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT)
-	{
-	  if (reg1 == 0) reg1 = addr;
-	  else reg2 = addr;
-	  addr = 0;
-	}
-      if (offset != 0)
+
+      if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
+	return strcat (buf, AS2 (p,%2,%0));
+
+      if (STACK_TOP_P (operands[0]))
+	return strcat (buf, AS2 (,%y2,%0));
+      else
+	return strcat (buf, AS2 (,%2,%0));
+
+    case MINUS:
+    case DIV:
+      if (GET_CODE (operands[1]) == MEM)
+	return strcat (buf, AS1 (r%z1,%1));
+
+      if (GET_CODE (operands[2]) == MEM)
+	return strcat (buf, AS1 (%z2,%2));
+
+      if (NON_STACK_REG_P (operands[1]))
 	{
-	  if (addr != 0) abort ();
-	  addr = offset;
+	  output_op_from_reg (operands[1], strcat (buf, AS1 (r%z0,%1)));
+	  RET;
 	}
-      if ((reg1 && GET_CODE (reg1) == MULT)
-	  || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))
+      else if (NON_STACK_REG_P (operands[2]))
 	{
-	  breg = reg2;
-	  ireg = reg1;
+	  output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1)));
+	  RET;
 	}
-      else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))
+
+      if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2]))
+	abort ();
+
+      if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
+	return strcat (buf, AS2 (rp,%2,%0));
+
+      if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
+	return strcat (buf, AS2 (p,%1,%0));
+
+      if (STACK_TOP_P (operands[0]))
 	{
-	  breg = reg1;
-	  ireg = reg2;
+	  if (STACK_TOP_P (operands[1]))
+	    return strcat (buf, AS2 (,%y2,%0));
+	  else
+	    return strcat (buf, AS2 (r,%y1,%0));
 	}
+      else if (STACK_TOP_P (operands[1]))
+	return strcat (buf, AS2 (,%1,%0));
+      else
+	return strcat (buf, AS2 (r,%2,%0));
 
-      if (ireg != 0 || breg != 0)
-	{
-	  int scale = 1;
+    default:
+      abort ();
+    }
+}
+
+/* Output code for INSN to convert a float to a signed int.  OPERANDS
+   are the insn operands.  The output may be SFmode or DFmode and the
+   input operand may be SImode or DImode.  As a special case, make sure
+   that the 387 stack top dies if the output mode is DImode, because the
+   hardware requires this.  */
 
-	  if (addr != 0)
-	    {
-	      if (flag_pic)
-		output_pic_addr_const (file, addr, 0);
+char *
+output_fix_trunc (insn, operands)
+     rtx insn;
+     rtx *operands;
+{
+  int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
+  rtx xops[2];
 
-	      else if (GET_CODE (addr) == LABEL_REF)
-		output_asm_label (addr);
+  if (! STACK_TOP_P (operands[1]) ||
+      (GET_MODE (operands[0]) == DImode && ! stack_top_dies))
+    abort ();
 
-	      else
-		output_addr_const (file, addr);
-	    }
+  xops[0] = GEN_INT (12);
+  xops[1] = operands[4];
 
-  	  if (ireg != 0 && GET_CODE (ireg) == MULT)
-	    {
-	      scale = INTVAL (XEXP (ireg, 1));
-	      ireg = XEXP (ireg, 0);
-	    }
+  output_asm_insn (AS1 (fnstc%W2,%2), operands);
+  output_asm_insn (AS2 (mov%L2,%2,%4), operands);
+  output_asm_insn (AS2 (mov%B1,%0,%h1), xops);
+  output_asm_insn (AS2 (mov%L4,%4,%3), operands);
+  output_asm_insn (AS1 (fldc%W3,%3), operands);
 
-	  /* The stack pointer can only appear as a base register,
-	     never an index register, so exchange the regs if it is wrong. */
+  if (NON_STACK_REG_P (operands[0]))
+    output_to_reg (operands[0], stack_top_dies);
+  else if (GET_CODE (operands[0]) == MEM)
+    {
+      if (stack_top_dies)
+	output_asm_insn (AS1 (fistp%z0,%0), operands);
+      else
+	output_asm_insn (AS1 (fist%z0,%0), operands);
+    }
+  else
+    abort ();
 
-	  if (scale == 1 && ireg && REGNO (ireg) == STACK_POINTER_REGNUM)
-	    {
-	      rtx tmp;
+  return AS1 (fldc%W2,%2);
+}
+
+/* Output code for INSN to compare OPERANDS.  The two operands might
+   not have the same mode: one might be within a FLOAT or FLOAT_EXTEND
+   expression.  If the compare is in mode CCFPEQmode, use an opcode that
+   will not fault if a qNaN is present. */
 
-	      tmp = breg;
-	      breg = ireg;
-	      ireg = tmp;
-	    }
+char *
+output_float_compare (insn, operands)
+     rtx insn;
+     rtx *operands;
+{
+  int stack_top_dies;
+  rtx body = XVECEXP (PATTERN (insn), 0, 0);
+  int unordered_compare = GET_MODE (SET_SRC (body)) == CCFPEQmode;
 
-	  /* output breg+ireg*scale */
-	  PRINT_B_I_S (breg, ireg, scale, file);
-	  break;
-	}
+  /* intel1 */
+  rtx tmp;
+  if (! STACK_TOP_P (operands[0]))
+    {
+      tmp = operands[0];
+      operands[0] = operands[1];
+      operands[1] = tmp;
+      cc_status.flags |= CC_REVERSED;
+    }
+    
+  if (! STACK_TOP_P (operands[0]))
+    abort ();
 
-    case MULT:
-      {
-	int scale;
-	if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
-	  {
-	    scale = INTVAL (XEXP (addr, 0));
-	    ireg = XEXP (addr, 1);
-	  }
-	else
-	  {
-	    scale = INTVAL (XEXP (addr, 1));
-	    ireg = XEXP (addr, 0);
-	  }
-	output_addr_const (file, const0_rtx);
-	PRINT_B_I_S ((rtx) 0, ireg, scale, file);
-      }
-      break;
+  stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
 
-    default:
-      if (GET_CODE (addr) == CONST_INT
-	  && INTVAL (addr) < 0x8000
-	  && INTVAL (addr) >= -0x8000)
-	fprintf (file, "%d", INTVAL (addr));
+  if (STACK_REG_P (operands[1])
+      && stack_top_dies
+      && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
+      && REGNO (operands[1]) != FIRST_STACK_REG)
+    {
+      /* If both the top of the 387 stack dies, and the other operand
+	 is also a stack register that dies, then this must be a
+	 `fcompp' float compare */
+
+      if (unordered_compare)
+	output_asm_insn ("fucompp", operands);
       else
-	{
-	  if (flag_pic)
-	    output_pic_addr_const (file, addr, 0);
-	  else
-	    output_addr_const (file, addr);
-	}
+	output_asm_insn ("fcompp", operands);
+    }
+  else
+    {
+      static char buf[100];
+
+      /* Decide if this is the integer or float compare opcode, or the
+	 unordered float compare. */
+
+      if (unordered_compare)
+	strcpy (buf, "fucom");
+      else if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_FLOAT)
+	strcpy (buf, "fcom");
+      else
+	strcpy (buf, "ficom");
+
+      /* Modify the opcode if the 387 stack is to be popped. */
+
+      if (stack_top_dies)
+	strcat (buf, "p");
+
+      if (NON_STACK_REG_P (operands[1]))
+	output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1)));
+      else
+        output_asm_insn (strcat (buf, AS1 (%z1,%y1)), operands);
     }
+
+  /* Now retrieve the condition code. */
+
+  return output_fp_cc0_set (insn);
 }
 
-/* Set the cc_status for the results of an insn whose pattern is EXP.
-   On the 80386, we assume that only test and compare insns, as well
-   as SI, HI, & DI mode ADD, SUB, NEG, AND, IOR, XOR, ASHIFT,
-   ASHIFTRT, and LSHIFTRT instructions set the condition codes usefully.
-   Also, we assume that jumps, moves and sCOND don't affect the condition
-   codes.  All else clobbers the condition codes, by assumption.
+/* Output opcodes to transfer the results of FP compare or test INSN
+   from the FPU to the CPU flags.  If TARGET_IEEE_FP, ensure that if the
+   result of the compare or test is unordered, no comparison operator
+   succeeds except NE.  Return an output template, if any.  */
 
-   We assume that ALL integer add, minus, etc. instructions effect the
-   condition codes.  This MUST be consistent with i386.md.
+char *
+output_fp_cc0_set (insn)
+     rtx insn;
+{
+  rtx xops[3];
+  rtx unordered_label;
+  rtx next;
+  enum rtx_code code;
 
-   We don't record any float test or compare - the redundant test &
-   compare check in final.c does not handle stack-like regs correctly. */
+  xops[0] = gen_rtx (REG, HImode, 0);
+  output_asm_insn (AS1 (fnsts%W0,%0), xops);
 
-void
-notice_update_cc (exp)
-     rtx exp;
-{
-  if (GET_CODE (exp) == SET)
+
+  if (! TARGET_IEEE_FP)
     {
-      /* Jumps do not alter the cc's.  */
-      if (SET_DEST (exp) == pc_rtx)
-	return;
-      /* Moving register or memory into a register:
-	 it doesn't alter the cc's, but it might invalidate
-	 the RTX's which we remember the cc's came from.
-	 (Note that moving a constant 0 or 1 MAY set the cc's).  */
-      if (REG_P (SET_DEST (exp))
-	  && (REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == MEM
-	      || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'))
-	{
-	  if (cc_status.value1
-	      && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1))
-	    cc_status.value1 = 0;
-	  if (cc_status.value2
-	      && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2))
-	    cc_status.value2 = 0;
-	  return;
-	}
-      /* Moving register into memory doesn't alter the cc's.
-	 It may invalidate the RTX's which we remember the cc's came from.  */
-      if (GET_CODE (SET_DEST (exp)) == MEM
-	  && (REG_P (SET_SRC (exp))
-	      || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'))
-	{
-	  if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM)
-	    cc_status.value1 = 0;
-	  if (cc_status.value2 && GET_CODE (cc_status.value2) == MEM)
-	    cc_status.value2 = 0;
-	  return;
-	}
-      /* Function calls clobber the cc's.  */
-      else if (GET_CODE (SET_SRC (exp)) == CALL)
-	{
-	  CC_STATUS_INIT;
-	  return;
-	}
-      /* Tests and compares set the cc's in predictable ways.  */
-      else if (SET_DEST (exp) == cc0_rtx)
-	{
-	  CC_STATUS_INIT;
-	  cc_status.value1 = SET_SRC (exp);
-	  return;
-	}
-      /* Certain instructions effect the condition codes. */
-      else if (GET_MODE (SET_SRC (exp)) == SImode
-	       || GET_MODE (SET_SRC (exp)) == HImode
-	       || GET_MODE (SET_SRC (exp)) == QImode)
-	switch (GET_CODE (SET_SRC (exp)))
-	  {
-	  case ASHIFTRT: case LSHIFTRT:
-	  case ASHIFT:
-	    /* Shifts on the 386 don't set the condition codes if the
-	       shift count is zero. */
-	    if (GET_CODE (XEXP (SET_SRC (exp), 1)) != CONST_INT)
-	      {
-		CC_STATUS_INIT;
-		break;
-	      }
-	    /* We assume that the CONST_INT is non-zero (this rtx would
-	       have been deleted if it were zero. */
+      /* intel1 */
+      if (!(cc_status.flags & CC_REVERSED))
+        {
+          next = next_cc0_user (insn);
+        
+          if (GET_CODE (next) == JUMP_INSN
+              && GET_CODE (PATTERN (next)) == SET
+              && SET_DEST (PATTERN (next)) == pc_rtx
+              && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
+            {
+              code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
+            }
+          else if (GET_CODE (PATTERN (next)) == SET)
+            {
+              code = GET_CODE (SET_SRC (PATTERN (next)));
+            }
+          else
+            {
+              return "sahf";
+            }
+          if (code == GT || code == LT || code == EQ || code == NE
+              || code == LE || code == GE)
+            { /* We will test eax directly */
+              cc_status.flags |= CC_TEST_AX;
+              RET;
+            }
+        }
+      return "sahf";
+    }
 
-	  case PLUS: case MINUS: case NEG:
-	  case AND: case IOR: case XOR:
-	    cc_status.flags = CC_NO_OVERFLOW;
-	    cc_status.value1 = SET_SRC (exp);
-	    cc_status.value2 = SET_DEST (exp);
-	    break;
+  next = next_cc0_user (insn);
+  if (next == NULL_RTX)
+    abort ();
 
-	  default:
-	    CC_STATUS_INIT;
-	  }
-      else
-	{
-	  CC_STATUS_INIT;
-	}
+  if (GET_CODE (next) == JUMP_INSN
+      && GET_CODE (PATTERN (next)) == SET
+      && SET_DEST (PATTERN (next)) == pc_rtx
+      && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
+    {
+      code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
     }
-  else if (GET_CODE (exp) == PARALLEL
-	   && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
+  else if (GET_CODE (PATTERN (next)) == SET)
     {
-      if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx)
-	return;
-      if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx)
-	{
-	  CC_STATUS_INIT;
-	  if (stack_regs_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0))))
-	    cc_status.flags |= CC_IN_80387;
-	  else
-	    cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0));
-	  return;
-	}
-      CC_STATUS_INIT;
+      code = GET_CODE (SET_SRC (PATTERN (next)));
     }
   else
+    abort ();
+
+  xops[0] = gen_rtx (REG, QImode, 0);
+
+  switch (code)
     {
-      CC_STATUS_INIT;
+    case GT:
+      xops[1] = GEN_INT (0x45);
+      output_asm_insn (AS2 (and%B0,%1,%h0), xops);
+      /* je label */
+      break;
+
+    case LT:
+      xops[1] = GEN_INT (0x45);
+      xops[2] = GEN_INT (0x01);
+      output_asm_insn (AS2 (and%B0,%1,%h0), xops);
+      output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
+      /* je label */
+      break;
+
+    case GE:
+      xops[1] = GEN_INT (0x05);
+      output_asm_insn (AS2 (and%B0,%1,%h0), xops);
+      /* je label */
+      break;
+
+    case LE:
+      xops[1] = GEN_INT (0x45);
+      xops[2] = GEN_INT (0x40);
+      output_asm_insn (AS2 (and%B0,%1,%h0), xops);
+      output_asm_insn (AS1 (dec%B0,%h0), xops);
+      output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
+      /* jb label */
+      break;
+
+    case EQ:
+      xops[1] = GEN_INT (0x45);
+      xops[2] = GEN_INT (0x40);
+      output_asm_insn (AS2 (and%B0,%1,%h0), xops);
+      output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
+      /* je label */
+      break;
+
+    case NE:
+      xops[1] = GEN_INT (0x44);
+      xops[2] = GEN_INT (0x40);
+      output_asm_insn (AS2 (and%B0,%1,%h0), xops);
+      output_asm_insn (AS2 (xor%B0,%2,%h0), xops);
+      /* jne label */
+      break;
+
+    case GTU:
+    case LTU:
+    case GEU:
+    case LEU:
+    default:
+      abort ();
     }
+  RET;
+}
+
+#define MAX_386_STACK_LOCALS 2
+
+static rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS];
+
+/* Define the structure for the machine field in struct function.  */
+struct machine_function
+{
+  rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS];
+};
+
+/* Functions to save and restore i386_stack_locals.
+   These will be called, via pointer variables,
+   from push_function_context and pop_function_context.  */
+
+void
+save_386_machine_status (p)
+     struct function *p;
+{
+  p->machine = (struct machine_function *) xmalloc (sizeof i386_stack_locals);
+  bcopy (i386_stack_locals, p->machine->i386_stack_locals,
+	 sizeof i386_stack_locals);
 }
-
-/* Split one or more DImode RTL references into pairs of SImode
-   references.  The RTL can be REG, offsettable MEM, integer constant, or
-   CONST_DOUBLE.  "operands" is a pointer to an array of DImode RTL to
-   split and "num" is its length.  lo_half and hi_half are output arrays
-   that parallel "operands". */
 
 void
-split_di (operands, num, lo_half, hi_half)
-     rtx operands[];
-     int num;
-     rtx lo_half[], hi_half[];
+restore_386_machine_status (p)
+     struct function *p;
 {
-  while (num--)
-    {
-      if (GET_CODE (operands[num]) == REG)
-	{
-	  lo_half[num] = gen_rtx (REG, SImode, REGNO (operands[num]));
-	  hi_half[num] = gen_rtx (REG, SImode, REGNO (operands[num]) + 1);
-	}
-      else if (CONSTANT_P (operands[num]))
-	{
-	  split_double (operands[num], &lo_half[num], &hi_half[num]);
-	}
-      else if (offsettable_memref_p (operands[num]))
-	{
-	  lo_half[num] = operands[num];
-	  hi_half[num] = adj_offsettable_operand (operands[num], 4);
-	}
-      else
-	abort();
-    }
+  bcopy (p->machine->i386_stack_locals, i386_stack_locals,
+	 sizeof i386_stack_locals);
+  free (p->machine);
 }
-
-/* Return 1 if this is a valid binary operation on a 387.
-   OP is the expression matched, and MODE is its mode. */
 
-int
-binary_387_op (op, mode)
-    register rtx op;
-    enum machine_mode mode;
+/* Clear stack slot assignments remembered from previous functions.
+   This is called from INIT_EXPANDERS once before RTL is emitted for each
+   function.  */
+
+void
+clear_386_stack_locals ()
 {
-  if (mode != VOIDmode && mode != GET_MODE (op))
-    return 0;
+  enum machine_mode mode;
+  int n;
 
-  switch (GET_CODE (op))
-    {
-    case PLUS:
-    case MINUS:
-    case MULT:
-    case DIV:
-      return GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT;
+  for (mode = VOIDmode; (int) mode < (int) MAX_MACHINE_MODE;
+       mode = (enum machine_mode) ((int) mode + 1))
+    for (n = 0; n < MAX_386_STACK_LOCALS; n++)
+      i386_stack_locals[(int) mode][n] = NULL_RTX;
 
-    default:
-      return 0;
-    }
+  /* Arrange to save and restore i386_stack_locals around nested functions.  */
+  save_machine_status = save_386_machine_status;
+  restore_machine_status = restore_386_machine_status;
 }
 
-
-/* Return 1 if this is a valid shift or rotate operation on a 386.
-   OP is the expression matched, and MODE is its mode. */
+/* Return a MEM corresponding to a stack slot with mode MODE.
+   Allocate a new slot if necessary.
 
-int
-shift_op (op, mode)
-    register rtx op;
-    enum machine_mode mode;
+   The RTL for a function can have several slots available: N is
+   which slot to use.  */
+
+rtx
+assign_386_stack_local (mode, n)
+     enum machine_mode mode;
+     int n;
 {
-  rtx operand = XEXP (op, 0);
+  if (n < 0 || n >= MAX_386_STACK_LOCALS)
+    abort ();
 
-  if (mode != VOIDmode && mode != GET_MODE (op))
-    return 0;
+  if (i386_stack_locals[(int) mode][n] == NULL_RTX)
+  {
+    i386_stack_locals[(int) mode][n]
+      = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
+  }
+  return i386_stack_locals[(int) mode][n];
+}
 
-  if (GET_MODE (operand) != GET_MODE (op)
-      || GET_MODE_CLASS (GET_MODE (op)) != MODE_INT)
-    return 0;
 
-  return (GET_CODE (op) == ASHIFT
-	  || GET_CODE (op) == ASHIFTRT
-	  || GET_CODE (op) == LSHIFTRT
-	  || GET_CODE (op) == ROTATE
-	  || GET_CODE (op) == ROTATERT);
+/* all functions after here added by intel1 */
+/* intel1 */
+int is_mul(op,mode)
+    register rtx op;
+    enum machine_mode mode;
+{
+  return(GET_CODE(op)==MULT);
 }
 
-/* Return 1 if OP is COMPARE rtx with mode VOIDmode.
-   MODE is not used.  */
-
-int
-VOIDmode_compare_op (op, mode)
+/* intel1 */
+int is_div(op,mode)
     register rtx op;
     enum machine_mode mode;
 {
-  return GET_CODE (op) == COMPARE && GET_MODE (op) == VOIDmode;
+  return(GET_CODE(op)==DIV);
 }
-
-/* Output code to perform a 387 binary operation in INSN, one of PLUS,
-   MINUS, MULT or DIV.  OPERANDS are the insn operands, where operands[3]
-   is the expression of the binary operation.  The output may either be
-   emitted here, or returned to the caller, like all output_* functions.
 
-   There is no guarantee that the operands are the same mode, as they
-   might be within FLOAT or FLOAT_EXTEND expressions. */
+/* Create a new copy of an rtx.
+   Recursively copies the operands of the rtx,
+   except for those few rtx codes that are sharable.
+   Doesn't share CONST  */
 
-char *
-output_387_binary_op (insn, operands)
-     rtx insn;
-     rtx *operands;
+rtx
+copy_all_rtx (orig)
+     register rtx orig;
 {
-  rtx temp;
-  char *base_op;
-  static char buf[100];
+  register rtx copy;
+  register int i, j;
+  register RTX_CODE code;
+  register char *format_ptr;
 
-  switch (GET_CODE (operands[3]))
+  code = GET_CODE (orig);
+
+  switch (code)
     {
-    case PLUS:
-      if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
-	  || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
-	base_op = "fiadd";
-      else
-	base_op = "fadd";
-      break;
+    case REG:
+    case QUEUED:
+    case CONST_INT:
+    case CONST_DOUBLE:
+    case SYMBOL_REF:
+    case CODE_LABEL:
+    case PC:
+    case CC0:
+    case SCRATCH:
+      /* SCRATCH must be shared because they represent distinct values. */
+      return orig;
 
-    case MINUS:
-      if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
-	  || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
-	base_op = "fisub";
-      else
-	base_op = "fsub";
+#if 0
+    case CONST:
+      /* CONST can be shared if it contains a SYMBOL_REF.  If it contains
+	 a LABEL_REF, it isn't sharable.  */
+      if (GET_CODE (XEXP (orig, 0)) == PLUS
+	  && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF
+	  && GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT)
+	return orig;
       break;
+#endif
+      /* A MEM with a constant address is not sharable.  The problem is that
+	 the constant address may need to be reloaded.  If the mem is shared,
+	 then reloading one copy of this mem will cause all copies to appear
+	 to have been reloaded.  */
+    }
+
+  copy = rtx_alloc (code);
+  PUT_MODE (copy, GET_MODE (orig));
+  copy->in_struct = orig->in_struct;
+  copy->volatil = orig->volatil;
+  copy->unchanging = orig->unchanging;
+  copy->integrated = orig->integrated;
+  /* intel1 */
+  copy->is_spill_rtx = orig->is_spill_rtx;
+  
+  format_ptr = GET_RTX_FORMAT (GET_CODE (copy));
+
+  for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++)
+    {
+      switch (*format_ptr++)
+	{
+	case 'e':
+	  XEXP (copy, i) = XEXP (orig, i);
+	  if (XEXP (orig, i) != NULL)
+	    XEXP (copy, i) = copy_rtx (XEXP (orig, i));
+	  break;
 
-    case MULT:
-      if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
-	  || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
-	base_op = "fimul";
-      else
-	base_op = "fmul";
-      break;
+	case '0':
+	case 'u':
+	  XEXP (copy, i) = XEXP (orig, i);
+	  break;
 
-    case DIV:
-      if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
-	  || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
-	base_op = "fidiv";
-      else
-	base_op = "fdiv";
-      break;
+	case 'E':
+	case 'V':
+	  XVEC (copy, i) = XVEC (orig, i);
+	  if (XVEC (orig, i) != NULL)
+	    {
+	      XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i));
+	      for (j = 0; j < XVECLEN (copy, i); j++)
+		XVECEXP (copy, i, j) = copy_rtx (XVECEXP (orig, i, j));
+	    }
+	  break;
 
-    default:
-      abort ();
+	case 'w':
+	  XWINT (copy, i) = XWINT (orig, i);
+	  break;
+
+	case 'i':
+	  XINT (copy, i) = XINT (orig, i);
+	  break;
+
+	case 's':
+	case 'S':
+	  XSTR (copy, i) = XSTR (orig, i);
+	  break;
+
+	default:
+	  abort ();
+	}
+    }
+  return copy;
+}
+
+
+/* try to rewrite a memory address to make it valid */
+void 
+rewrite_address (mem_rtx)
+     rtx mem_rtx;
+{
+  rtx index_rtx, base_rtx, offset_rtx, scale_rtx, ret_rtx;
+  int scale = 1;
+  int offset_adjust = 0;
+  int was_only_offset = 0;
+  rtx mem_addr = XEXP (mem_rtx, 0);
+  char *storage = (char *) oballoc (0);
+  int in_struct = 0;
+  int is_spill_rtx = 0;
+
+  in_struct = MEM_IN_STRUCT_P (mem_rtx);
+  is_spill_rtx = RTX_IS_SPILL_P (mem_rtx);
+
+  if (GET_CODE (mem_addr) == PLUS &&
+      GET_CODE (XEXP (mem_addr, 1)) == PLUS &&
+      GET_CODE (XEXP (XEXP (mem_addr, 1), 0)) == REG)
+    {				/* this part is utilized by the combiner */
+      ret_rtx =
+	gen_rtx (PLUS, GET_MODE (mem_addr),
+		 gen_rtx (PLUS, GET_MODE (XEXP (mem_addr, 1)),
+			  XEXP (mem_addr, 0),
+			  XEXP (XEXP (mem_addr, 1), 0)),
+		 XEXP (XEXP (mem_addr, 1), 1));
+      if (memory_address_p (GET_MODE (mem_rtx), ret_rtx))
+	{
+	  XEXP (mem_rtx, 0) = ret_rtx;
+	  RTX_IS_SPILL_P (ret_rtx) = is_spill_rtx;
+	  return;
+	}
+      obfree (storage);
+    }
+
+  /* this part is utilized by loop.c */
+  /* If the address contains PLUS (reg,const) and this pattern is invalid
+     in this case - try to rewrite the address to make it valid  intel1
+  */
+  storage = (char *) oballoc (0);
+  index_rtx = base_rtx = offset_rtx = NULL;
+  /* find the base index and offset elements of the memory address */
+  if (GET_CODE (mem_addr) == PLUS)
+    {
+      if (GET_CODE (XEXP (mem_addr, 0)) == REG)
+	{
+	  if (GET_CODE (XEXP (mem_addr, 1)) == REG)
+	    {
+	      base_rtx = XEXP (mem_addr, 1);
+	      index_rtx = XEXP (mem_addr, 0);
+	    }
+	  else
+	    {
+	      base_rtx = XEXP (mem_addr, 0);
+	      offset_rtx = XEXP (mem_addr, 1);
+	    }
+	}
+      else if (GET_CODE (XEXP (mem_addr, 0)) == MULT)
+	{
+	  index_rtx = XEXP (mem_addr, 0);
+	  if (GET_CODE (XEXP (mem_addr, 1)) == REG)
+	    {
+	      base_rtx = XEXP (mem_addr, 1);
+	    }
+	  else
+	    {
+	      offset_rtx = XEXP (mem_addr, 1);
+	    }
+	}
+      else if (GET_CODE (XEXP (mem_addr, 0)) == PLUS)
+	{
+	  /* intel1 */
+	  if (GET_CODE (XEXP (XEXP (mem_addr, 0), 0)) == PLUS &&
+	      GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0)) == MULT &&
+	      GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 0)) == REG &&
+	      GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 1)) == CONST_INT &&
+	      GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1)) == CONST_INT &&
+	      GET_CODE (XEXP (XEXP (mem_addr, 0), 1)) == REG &&
+	      GET_CODE (XEXP (mem_addr, 1)) == SYMBOL_REF)
+	    {
+	      index_rtx = XEXP (XEXP (XEXP (mem_addr, 0), 0), 0);
+	      offset_rtx = XEXP (mem_addr, 1);
+	      base_rtx = XEXP (XEXP (mem_addr, 0), 1);
+	      offset_adjust = INTVAL (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1));
+	    }
+	  else
+	    {
+	      offset_rtx = XEXP (mem_addr, 1);
+	      index_rtx = XEXP (XEXP (mem_addr, 0), 0);
+	      base_rtx = XEXP (XEXP (mem_addr, 0), 1);
+	    }
+	}
+      else if (GET_CODE (XEXP (mem_addr, 0)) == CONST_INT)
+	{
+	  was_only_offset = 1;
+	  index_rtx = NULL;
+	  base_rtx = NULL;
+	  offset_rtx = XEXP (mem_addr, 1);
+	  offset_adjust = INTVAL (XEXP (mem_addr, 0));
+	  if (offset_adjust == 0)
+	    {
+	      XEXP (mem_rtx, 0) = offset_rtx;
+	      RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
+	      return;
+	    }
+	}
+      else
+	{
+	  obfree (storage);
+	  return;
+	}
+    }
+  else if (GET_CODE (mem_addr) == MULT)
+    {
+      index_rtx = mem_addr;
+    }
+  else
+    {
+      obfree (storage);
+      return;
+    }
+  if (index_rtx && GET_CODE (index_rtx) == MULT)
+    {
+      if (GET_CODE (XEXP (index_rtx, 1)) != CONST_INT)
+	{
+	  obfree (storage);
+	  return;
+	}
+      scale_rtx = XEXP (index_rtx, 1);
+      scale = INTVAL (scale_rtx);
+      index_rtx = copy_all_rtx (XEXP (index_rtx, 0));
+    }
+  /* now find which of the elements are invalid and try to fix them */
+  if (index_rtx && GET_CODE (index_rtx) == CONST_INT && base_rtx == NULL)
+    {
+      offset_adjust = INTVAL (index_rtx) * scale;
+      if (offset_rtx && GET_CODE (offset_rtx) == CONST &&
+	  GET_CODE (XEXP (offset_rtx, 0)) == PLUS)
+	{
+	  if (GET_CODE (XEXP (XEXP (offset_rtx, 0), 0)) == SYMBOL_REF &&
+	      GET_CODE (XEXP (XEXP (offset_rtx, 0), 1)) == CONST_INT)
+	    {
+	      offset_rtx = copy_all_rtx (offset_rtx);
+	      XEXP (XEXP (offset_rtx, 0), 1) =
+		gen_rtx (CONST_INT, 0, INTVAL (XEXP (XEXP (offset_rtx, 0), 1)) + offset_adjust);
+	      if (!CONSTANT_P (offset_rtx))
+		{
+		  obfree (storage);
+		  return;
+		}
+	    }
+	}
+      else if (offset_rtx && GET_CODE (offset_rtx) == SYMBOL_REF)
+	{
+	  offset_rtx =
+	    gen_rtx (CONST, GET_MODE (offset_rtx),
+		     gen_rtx (PLUS, GET_MODE (offset_rtx),
+			      offset_rtx,
+			      gen_rtx (CONST_INT, 0, offset_adjust)));
+	  if (!CONSTANT_P (offset_rtx))
+	    {
+	      obfree (storage);
+	      return;
+	    }
+	}
+      else if (offset_rtx && GET_CODE (offset_rtx) == CONST_INT)
+	{
+	  offset_rtx = gen_rtx (CONST_INT, 0, INTVAL (offset_rtx) + offset_adjust);
+	}
+      else if (!offset_rtx)
+	{
+	  offset_rtx = gen_rtx (CONST_INT, 0, 0);
+	}
+      RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
+      XEXP (mem_rtx, 0) = offset_rtx;
+      return;
     }
-
-  strcpy (buf, base_op);
-
-  switch (GET_CODE (operands[3]))
+  if (base_rtx && GET_CODE (base_rtx) == PLUS &&
+      GET_CODE (XEXP (base_rtx, 0)) == REG &&
+      GET_CODE (XEXP (base_rtx, 1)) == CONST_INT)
     {
-    case MULT:
-    case PLUS:
-      if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
+      offset_adjust += INTVAL (XEXP (base_rtx, 1));
+      base_rtx = copy_all_rtx (XEXP (base_rtx, 0));
+    }
+  else if (base_rtx && GET_CODE (base_rtx) == CONST_INT)
+    {
+      offset_adjust += INTVAL (base_rtx);
+      base_rtx = NULL;
+    }
+  if (index_rtx && GET_CODE (index_rtx) == PLUS &&
+      GET_CODE (XEXP (index_rtx, 0)) == REG &&
+      GET_CODE (XEXP (index_rtx, 1)) == CONST_INT)
+    {
+      offset_adjust += INTVAL (XEXP (index_rtx, 1)) * scale;
+      index_rtx = copy_all_rtx (XEXP (index_rtx, 0));
+    }
+  if (index_rtx)
+    {
+      if (!LEGITIMATE_INDEX_P (index_rtx)
+      && !(index_rtx == stack_pointer_rtx && scale == 1 && base_rtx == NULL))
 	{
-	  temp = operands[2];
-	  operands[2] = operands[1];
-	  operands[1] = temp;
+	  obfree (storage);
+	  return;
 	}
-
-      if (GET_CODE (operands[2]) == MEM)
-	return strcat (buf, AS1 (%z2,%2));
-
-      if (NON_STACK_REG_P (operands[1]))
+    }
+  if (base_rtx)
+    {
+      if (!LEGITIMATE_INDEX_P (base_rtx) && GET_CODE (base_rtx) != REG)
 	{
-	  output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1)));
-	  RET;
+	  obfree (storage);
+	  return;
 	}
-      else if (NON_STACK_REG_P (operands[2]))
+    }
+  if (offset_adjust != 0)
+    {
+      if (offset_rtx)
 	{
-	  output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1)));
-	  RET;
+	  if (GET_CODE (offset_rtx) == CONST &&
+	      GET_CODE (XEXP (offset_rtx, 0)) == PLUS)
+	    {
+	      if (GET_CODE (XEXP (XEXP (offset_rtx, 0), 0)) == SYMBOL_REF &&
+		  GET_CODE (XEXP (XEXP (offset_rtx, 0), 1)) == CONST_INT)
+		{
+		  offset_rtx = copy_all_rtx (offset_rtx);
+		  XEXP (XEXP (offset_rtx, 0), 1) =
+		    gen_rtx (CONST_INT, 0, INTVAL (XEXP (XEXP (offset_rtx, 0), 1)) + offset_adjust);
+		  if (!CONSTANT_P (offset_rtx))
+		    {
+		      obfree (storage);
+		      return;
+		    }
+		}
+	    }
+	  else if (GET_CODE (offset_rtx) == SYMBOL_REF)
+	    {
+	      offset_rtx =
+		gen_rtx (CONST, GET_MODE (offset_rtx),
+			 gen_rtx (PLUS, GET_MODE (offset_rtx),
+				  offset_rtx,
+				  gen_rtx (CONST_INT, 0, offset_adjust)));
+	      if (!CONSTANT_P (offset_rtx))
+		{
+		  obfree (storage);
+		  return;
+		}
+	    }
+	  else if (GET_CODE (offset_rtx) == CONST_INT)
+	    {
+	      offset_rtx = gen_rtx (CONST_INT, 0, INTVAL (offset_rtx) + offset_adjust);
+	    }
+	  else
+	    {
+	      obfree (storage);
+	      return;
+	    }
 	}
-
-      if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
-	return strcat (buf, AS2 (p,%2,%0));
-
-      if (STACK_TOP_P (operands[0]))
-	return strcat (buf, AS2C (%y2,%0));
       else
-	return strcat (buf, AS2C (%2,%0));
-
-    case MINUS:
-    case DIV:
-      if (GET_CODE (operands[1]) == MEM)
-	return strcat (buf, AS1 (r%z1,%1));
-
-      if (GET_CODE (operands[2]) == MEM)
-	return strcat (buf, AS1 (%z2,%2));
-
-      if (NON_STACK_REG_P (operands[1]))
 	{
-	  output_op_from_reg (operands[1], strcat (buf, AS1 (r%z0,%1)));
-	  RET;
+	  offset_rtx = gen_rtx (CONST_INT, 0, offset_adjust);
 	}
-      else if (NON_STACK_REG_P (operands[2]))
+      if (index_rtx)
 	{
-	  output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1)));
-	  RET;
+	  if (base_rtx)
+	    {
+	      if (scale != 1)
+		{
+		  if (GET_CODE (offset_rtx) == CONST_INT &&
+		      INTVAL (offset_rtx) == 0)
+		    {
+		      ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx),
+			     gen_rtx (MULT, GET_MODE (index_rtx), index_rtx,
+				      scale_rtx),
+					 base_rtx);
+		    }
+		  else
+		    {
+		      ret_rtx = gen_rtx (PLUS, GET_MODE (offset_rtx),
+					 gen_rtx (PLUS, GET_MODE (base_rtx),
+			     gen_rtx (MULT, GET_MODE (index_rtx), index_rtx,
+				      scale_rtx),
+						  base_rtx),
+					 offset_rtx);
+		    }
+		}
+	      else
+		{
+		  if (GET_CODE (offset_rtx) == CONST_INT &&
+		      INTVAL (offset_rtx) == 0)
+		    {
+		      ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx), index_rtx, base_rtx);
+		    }
+		  else
+		    {
+		      ret_rtx = gen_rtx (PLUS, GET_MODE (offset_rtx),
+			     gen_rtx (PLUS, GET_MODE (index_rtx), index_rtx,
+				      base_rtx),
+					 offset_rtx);
+		    }
+		}
+	    }
+	  else
+	    {
+	      if (scale != 1)
+		{
+		  if (GET_CODE (offset_rtx) == CONST_INT &&
+		      INTVAL (offset_rtx) == 0)
+		    {
+		      ret_rtx = gen_rtx (MULT, GET_MODE (index_rtx), index_rtx, scale_rtx);
+		    }
+		  else
+		    {
+		      ret_rtx =
+			gen_rtx (PLUS, GET_MODE (offset_rtx),
+			     gen_rtx (MULT, GET_MODE (index_rtx), index_rtx,
+				      scale_rtx),
+				 offset_rtx);
+		    }
+		}
+	      else
+		{
+		  if (GET_CODE (offset_rtx) == CONST_INT &&
+		      INTVAL (offset_rtx) == 0)
+		    {
+		      ret_rtx = index_rtx;
+		    }
+		  else
+		    {
+		      ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx), index_rtx, offset_rtx);
+		    }
+		}
+	    }
 	}
-
-      if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2]))
-	abort ();
-
-      if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
-	return strcat (buf, AS2 (rp,%2,%0));
-
-      if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
-	return strcat (buf, AS2 (p,%1,%0));
-
-      if (STACK_TOP_P (operands[0]))
+      else
 	{
-	  if (STACK_TOP_P (operands[1]))
-	    return strcat (buf, AS2C (%y2,%0));
+	  if (base_rtx)
+	    {
+	      if (GET_CODE (offset_rtx) == CONST_INT &&
+		  INTVAL (offset_rtx) == 0)
+		{
+		  ret_rtx = base_rtx;
+		}
+	      else
+		{
+		  ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx), base_rtx, offset_rtx);
+		}
+	    }
+	  else if (was_only_offset)
+	    {
+	      ret_rtx = offset_rtx;
+	    }
 	  else
-	    return strcat (buf, AS2 (r,%y1,%0));
+	    {
+	      obfree (storage);
+	      return;
+	    }
 	}
-      else if (STACK_TOP_P (operands[1]))
-	return strcat (buf, AS2C (%1,%0));
-      else
-	return strcat (buf, AS2 (r,%2,%0));
-
-    default:
-      abort ();
+      XEXP (mem_rtx, 0) = ret_rtx;
+      RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
+      return;
     }
-}
-
-/* Output code for INSN to convert a float to a signed int.  OPERANDS
-   are the insn operands.  The output may be SFmode or DFmode and the
-   input operand may be SImode or DImode.  As a special case, make sure
-   that the 387 stack top dies if the output mode is DImode, because the
-   hardware requires this.  */
-
-char *
-output_fix_trunc (insn, operands)
-     rtx insn;
-     rtx *operands;
-{
-  int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
-  rtx xops[2];
-
-  if (! STACK_TOP_P (operands[1]) ||
-      (GET_MODE (operands[0]) == DImode && ! stack_top_dies))
-    abort ();
-
-  xops[0] = GEN_INT (12);
-  xops[1] = operands[4];
-
-  output_asm_insn (AS1 (fnstc%W2,%2), operands);
-  output_asm_insn (AS2 (mov%L2,%2,%4), operands);
-  output_asm_insn (AS2 (mov%B1,%0,%h1), xops);
-  output_asm_insn (AS2 (mov%L4,%4,%3), operands);
-  output_asm_insn (AS1 (fldc%W3,%3), operands);
-
-  if (NON_STACK_REG_P (operands[0]))
-    output_to_reg (operands[0], stack_top_dies);
-  else if (GET_CODE (operands[0]) == MEM)
+  else
     {
-      if (stack_top_dies)
-	output_asm_insn (AS1 (fistp%z0,%0), operands);
-      else
-	output_asm_insn (AS1 (fist%z0,%0), operands);
+      obfree (storage);
+      return;
     }
-  else
-    abort ();
-
-  return AS1 (fldc%W2,%2);
 }
-
-/* Output code for INSN to compare OPERANDS.  The two operands might
-   not have the same mode: one might be within a FLOAT or FLOAT_EXTEND
-   expression.  If the compare is in mode CCFPEQmode, use an opcode that
-   will not fault if a qNaN is present. */
 
-char *
-output_float_compare (insn, operands)
-     rtx insn;
-     rtx *operands;
+/* return 1 if the first insn to set cc before insn also sets the register
+   reg_rtx - otherwise return 0
+*/
+int
+last_to_set_cc (reg_rtx, insn)
+     rtx reg_rtx, insn;
 {
-  int stack_top_dies;
-  rtx body = XVECEXP (PATTERN (insn), 0, 0);
-  int unordered_compare = GET_MODE (SET_SRC (body)) == CCFPEQmode;
-
-  if (! STACK_TOP_P (operands[0]))
-    abort ();
+  rtx prev_insn = PREV_INSN (insn);
 
-  stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
-
-  if (STACK_REG_P (operands[1])
-      && stack_top_dies
-      && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
-      && REGNO (operands[1]) != FIRST_STACK_REG)
+  while (prev_insn)
     {
-      /* If both the top of the 387 stack dies, and the other operand
-	 is also a stack register that dies, then this must be a
-	 `fcompp' float compare */
-
-      if (unordered_compare)
-	output_asm_insn ("fucompp", operands);
+      if (GET_CODE (prev_insn) == NOTE)
+	{
+	  ;
+	}
+      else if (GET_CODE (prev_insn) == INSN)
+	{
+	  if (GET_CODE (PATTERN (prev_insn)) != SET)
+	    {
+	      return (0);
+	    }
+	  if (rtx_equal_p (SET_DEST (PATTERN (prev_insn)), reg_rtx))
+	    {
+	      if (sets_condition_code (SET_SRC (PATTERN (prev_insn))))
+		{
+		  return (1);
+		}
+	      else
+		{
+		  return (0);
+		}
+	    }
+	  else if (!doesnt_set_condition_code (SET_SRC (PATTERN (prev_insn))))
+	    {
+	      return (0);
+	    }
+	}
       else
-	output_asm_insn ("fcompp", operands);
+	{
+	  return (0);
+	}
+      prev_insn = PREV_INSN (prev_insn);
     }
-  else
-    {
-      static char buf[100];
-
-      /* Decide if this is the integer or float compare opcode, or the
-	 unordered float compare. */
-
-      if (unordered_compare)
-	strcpy (buf, "fucom");
-      else if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_FLOAT)
-	strcpy (buf, "fcom");
-      else
-	strcpy (buf, "ficom");
-
-      /* Modify the opcode if the 387 stack is to be popped. */
-
-      if (stack_top_dies)
-	strcat (buf, "p");
+  return (0);
+}
 
-      if (NON_STACK_REG_P (operands[1]))
-	output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1)));
-      else
-        output_asm_insn (strcat (buf, AS1 (%z1,%y1)), operands);
-    }
+int
+doesnt_set_condition_code (pat)
+     rtx pat;
+{
+  switch (GET_CODE (pat))
+    {
+    case MEM:
+    case REG:
+      return (1);
 
-  /* Now retrieve the condition code. */
+    default:
+      return (0);
 
-  return output_fp_cc0_set (insn);
+    }
 }
-
-/* Output opcodes to transfer the results of FP compare or test INSN
-   from the FPU to the CPU flags.  If TARGET_IEEE_FP, ensure that if the
-   result of the compare or test is unordered, no comparison operator
-   succeeds except NE.  Return an output template, if any.  */
 
-char *
-output_fp_cc0_set (insn)
-     rtx insn;
+int
+sets_condition_code (pat)
+     rtx pat;
 {
-  rtx xops[3];
-  rtx unordered_label;
-  rtx next;
-  enum rtx_code code;
+  switch (GET_CODE (pat))
+    {
+    case PLUS:
+    case MINUS:
+    case AND:
+    case IOR:
+    case XOR:
+    case NOT:
+    case NEG:
+    case MULT:
+    case DIV:
+    case MOD:
+    case UDIV:
+    case UMOD:
+      return (1);
 
-  xops[0] = gen_rtx (REG, HImode, 0);
-  output_asm_insn (AS1 (fnsts%W0,%0), xops);
+    default:
+      return (0);
 
-  if (! TARGET_IEEE_FP)
-    return "sahf";
+    }
+}
 
-  next = next_cc0_user (insn);
-  if (next == NULL_RTX)
-    abort ();
 
-  if (GET_CODE (next) == JUMP_INSN
-      && GET_CODE (PATTERN (next)) == SET
-      && SET_DEST (PATTERN (next)) == pc_rtx
-      && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
-    {
-      code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
-    }
-  else if (GET_CODE (PATTERN (next)) == SET)
+/* intel1 */
+int
+str_immediate_operand (op, mode)
+     register rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) == CONST_INT && INTVAL (op) <= 32 && INTVAL (op) >= 0)
     {
-      code = GET_CODE (SET_SRC (PATTERN (next)));
+      return (1);
     }
-  else
-    abort ();
+  return (0);
+}
 
-  xops[0] = gen_rtx (REG, QImode, 0);
+/* intel1 */
+void
+override_options ()
+{
+  register int i, start;
+  register int regno;
+  register enum machine_mode mode;
+#if 0
+  int blend = 0;
+#endif
 
-  switch (code)
+  /* only one `-mcpu' allowed */
+  if (TARGET_X && (TARGET_X != TARGET_386) && (TARGET_X != TARGET_486) && (TARGET_X != TARGET_PENTIUM))
+    fatal ("multilple `-mcpu' definitions .\n");
+
+ /* if `-mcpu' use it, otherwise take default */
+ target_flags |= USE_CPU;
+
+  if (TARGET_PENTIUM)
+    x86_cpu = PROCESSOR_PENTIUM;
+  else if (TARGET_486)
+    x86_cpu = PROCESSOR_486;
+  else if (TARGET_386)
+    x86_cpu = PROCESSOR_386;
+  else /* no processor type ? */
+    fatal ("no processor type.\n");
+  
+#if 0 /* what happens if we have few -mcpu's, I don't think it's needed */
+  /* Identify the processor type */
+  if (!(TARGET_PENTIUM) && !(TARGET_486) && !(TARGET_386))
+    {
+      x86_cpu = PROCESSOR_PENTIUM;
+      target_flags |= (TARGET_486_SWITCH);
+      blend = 1;
+    }
+
+  else
     {
-    case GT:
-      xops[1] = GEN_INT (0x45);
-      output_asm_insn (AS2 (and%B0,%1,%h0), xops);
-      /* je label */
-      break;
+      x86_cpu = PROCESSOR_DEFAULT;
+      if (TARGET_PENTIUM)
+	{
+	  x86_cpu = PROCESSOR_PENTIUM;
+	}
+      if (TARGET_486)
+	{
+	  if (x86_cpu != PROCESSOR_DEFAULT)
+	    {
+	      error ("conflicting -mX86 : using blend");
+	      blend = 1;
+	      x86_cpu = PROCESSOR_PENTIUM;
+	      target_flags &= ~(TARGET_386_SWITCH);
+	      target_flags &= ~(TARGET_PENTIUM_SWITCH);
+	    }
+	  else
+	    {
+	      x86_cpu = PROCESSOR_486;
+	    }
+	}
+      if (TARGET_386)
+	{
+	  if (x86_cpu != PROCESSOR_DEFAULT)
+	    {
+	      error ("conflicting -mX86 : using blend");
+	      blend = 1;
+	      x86_cpu = PROCESSOR_486;
+	      target_flags &= ~(TARGET_386_SWITCH);
+	      target_flags &= ~(TARGET_PENTIUM_SWITCH);
+	      target_flags |= (TARGET_486_SWITCH);
+	    }
+	  else
+	    {
+	      x86_cpu = PROCESSOR_386;
+	    }
+	}
 
-    case LT:
-      xops[1] = GEN_INT (0x45);
-      xops[2] = GEN_INT (0x01);
-      output_asm_insn (AS2 (and%B0,%1,%h0), xops);
-      output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
-      /* je label */
-      break;
 
-    case GE:
-      xops[1] = GEN_INT (0x05);
-      output_asm_insn (AS2 (and%B0,%1,%h0), xops);
-      /* je label */
-      break;
+    }
+#endif
+  if (opt_level >= 4)
+    {
+      if (TARGET_486)
+        {
+	  if (opt_level == 4
+	      && !flag_no_interleave_stack_non_stack)
+	    {
+	      flag_interleave_stack_non_stack = 1;
+	      flag_schedule_insns = 1;
+	    }
+        }
+#if 0
+      if(TARGET_BLEND)
+        {
+          if (!flag_no_risc)
+            flag_risc = 1;
+          if (!flag_no_risc_const)
+            flag_risc_const = 1;
+          if (!flag_no_recombine)
+            flag_recombine = 1;
+        }
+#endif
+      if (TARGET_PENTIUM)
+        {
+          if (!flag_no_risc)
+            flag_risc = 1;
+          if (!flag_no_risc_const)
+            flag_risc_const = 1;
+          /*if (!flag_no_recombine)
+            flag_recombine = 1;*/
+	  if (opt_level == 4
+	      && !flag_no_schedule_stack_reg_insns)
+	    {
+	      flag_schedule_stack_reg_insns = 1;
+	      flag_schedule_insns = 1;
+	    }
+	  if (opt_level == 4
+	      && !flag_no_interleave_stack_non_stack)
+	    {
+	      flag_interleave_stack_non_stack = 1;
+	      flag_schedule_insns = 1;
+	    }
+        }
+    }
+}
 
-    case LE:
-      xops[1] = GEN_INT (0x45);
-      xops[2] = GEN_INT (0x40);
-      output_asm_insn (AS2 (and%B0,%1,%h0), xops);
-      output_asm_insn (AS1 (dec%B0,%h0), xops);
-      output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
-      /* jb label */
-      break;
 
-    case EQ:
-      xops[1] = GEN_INT (0x45);
-      xops[2] = GEN_INT (0x40);
-      output_asm_insn (AS2 (and%B0,%1,%h0), xops);
-      output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
-      /* je label */
-      break;
 
-    case NE:
-      xops[1] = GEN_INT (0x44);
-      xops[2] = GEN_INT (0x40);
-      output_asm_insn (AS2 (and%B0,%1,%h0), xops);
-      output_asm_insn (AS2 (xor%B0,%2,%h0), xops);
-      /* jne label */
-      break;
 
-    case GTU:
-    case LTU:
-    case GEU:
-    case LEU:
-    default:
-      abort ();
+optimization_options (level)
+     int level;
+{
+  opt_level = level;
+  if (level > 0)
+    {
+      flag_opt_reg_use = 1;
+      flag_reduce_index_givs = 1;
     }
-  RET;
+  if (level >= 2)
+    {
+#ifdef INSN_SCHEDULING
+      flag_schedule_insns = 0;
+      flag_schedule_insns_after_reload = 0;
+#endif
+    }
+  if (level >= 3)
+    {
+      flag_inline_functions = 1;
+      flag_jump_back = 1;
+      flag_copy_prop = 1;
+      flag_compare_elim = 1;
+      flag_sftwr_pipe = 1;
+      flag_omit_frame_pointer = 1;
+      flag_reg_reg_copy_opt = 1;
+      flag_opt_reg_stack = 1;
+      flag_loop_after_global = 1;
+      flag_peep_spills = 1;
+      flag_replace_stack_mem = 1;
+      flag_opt_jumps_out = 1;
+      flag_replace_mem = 1;
+      flag_correct_cse_mistakes = 1;
+      flag_push_load_into_loop = 1;
+      flag_replace_reload_regs = 1;
+      flag_sign_extension_elim = 1;
+      flag_lift_stores = 1;
+      flag_runtime_lift_stores = 1;
+    }
+  if (level >= 4)
+    {
+#ifdef INSN_SCHEDULING
+      flag_schedule_insns_after_reload = 1;
+      flag_swap_for_agi = 1;
+      if (TARGET_PENTIUM)
+	{
+	  flag_risc = 1;
+	  flag_risc_const = 1;
+	  /*flag_recombine = 1;*/
+	  if (level == 4)
+	    {
+	      flag_schedule_stack_reg_insns = 1;
+	      flag_schedule_insns = 1;
+	    }
+	}
+#endif
+    }
+  if (level >= 5)
+    {
+#ifdef INSN_SCHEDULING
+      flag_schedule_insns = 1;
+#endif
+    }
+  if (flag_no_risc)
+    flag_risc = 0;
+  if (flag_no_risc_const)
+    flag_risc_const = 0;
+  if (flag_no_recombine)
+    flag_recombine = 0;
+  if (flag_no_risc_mem_dest)
+    flag_risc_mem_dest = 0;
 }
-
-#define MAX_386_STACK_LOCALS 2
 
-static rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS];
+/* intel1 */
 
-/* Define the structure for the machine field in struct function.  */
-struct machine_function
+int
+is_fp_insn (insn)
+     rtx insn;
 {
-  rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS];
-};
+  if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
+      && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
+	  || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode))
+    {
+      return (1);
+    }
+  return (0);
+}
 
-/* Functions to save and restore i386_stack_locals.
-   These will be called, via pointer variables,
-   from push_function_context and pop_function_context.  */
 
-void
-save_386_machine_status (p)
-     struct function *p;
+/*
+  Return 1 if the mode of the SET_DEST of insn is floating point
+  and it is not an fld or a move from memory to memory.
+  Otherwise return 0
+*/
+int
+is_fp_dest (insn)
+     rtx insn;
 {
-  p->machine = (struct machine_function *) xmalloc (sizeof i386_stack_locals);
-  bcopy ((char *) i386_stack_locals, (char *) p->machine->i386_stack_locals,
-	 sizeof i386_stack_locals);
+  if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
+      && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
+	  || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode)
+      && GET_CODE (SET_DEST (PATTERN (insn))) == REG
+      && REGNO (SET_DEST (PATTERN (insn))) >= FIRST_FLOAT_REG
+      && GET_CODE (SET_SRC (insn)) != MEM
+     )
+    {
+      return (1);
+    }
+  return (0);
 }
 
-void
-restore_386_machine_status (p)
-     struct function *p;
+/*
+  Return 1 if the mode of the SET_DEST floating point and is memory
+  and the source is a register.  
+*/
+int
+is_fp_store (insn)
+     rtx insn;
 {
-  bcopy ((char *) p->machine->i386_stack_locals, (char *) i386_stack_locals,
-	 sizeof i386_stack_locals);
-  free (p->machine);
+  if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
+      && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
+	  || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode)
+      && GET_CODE (SET_DEST (PATTERN (insn))) == MEM
+      && GET_CODE (SET_SRC (PATTERN (insn))) == REG
+     )
+    {
+      return (1);
+    }
+  return (0);
 }
 
-/* Clear stack slot assignments remembered from previous functions.
-   This is called from INIT_EXPANDERS once before RTL is emitted for each
-   function.  */
 
-void
-clear_386_stack_locals ()
+/*
+  Return 1 if dep_insn sets a register which insn uses as a base
+  or index to reference memory.
+  otherwise return 0
+*/
+int
+agi_dependent (insn, dep_insn)
+     rtx insn, dep_insn;
 {
-  enum machine_mode mode;
-  int n;
+  if (GET_CODE (dep_insn) == INSN && GET_CODE (PATTERN (dep_insn)) == SET
+      && GET_CODE (SET_DEST (PATTERN (dep_insn))) == REG)
+    {
+      return (reg_mentioned_in_mem (SET_DEST (PATTERN (dep_insn)), insn));
+    }
+  if (GET_CODE (dep_insn) == INSN && GET_CODE (PATTERN (dep_insn)) == SET
+      && GET_CODE (SET_DEST (PATTERN (dep_insn))) == MEM
+      && push_operand (SET_DEST (PATTERN (dep_insn)),
+                       GET_MODE (SET_DEST (PATTERN (dep_insn))))
+     )
+    {
+      return (reg_mentioned_in_mem (stack_pointer_rtx, insn));
+    }
+  
+  return (0);
+}
 
-  for (mode = VOIDmode; (int) mode < (int) MAX_MACHINE_MODE;
-       mode = (enum machine_mode) ((int) mode + 1))
-    for (n = 0; n < MAX_386_STACK_LOCALS; n++)
-      i386_stack_locals[(int) mode][n] = NULL_RTX;
+/*
+  Return 1 if reg is used in rtl as a base or index for a memory ref
+  otherwise return 0.
+*/
+int
+reg_mentioned_in_mem (reg, rtl)
+     rtx reg, rtl;
+{
+  register char *fmt;
+  register int i;
+  register enum rtx_code code;
 
-  /* Arrange to save and restore i386_stack_locals around nested functions.  */
-  save_machine_status = save_386_machine_status;
-  restore_machine_status = restore_386_machine_status;
-}
+  if (rtl == NULL)
+    return (0);
 
-/* Return a MEM corresponding to a stack slot with mode MODE.
-   Allocate a new slot if necessary.
+  code = GET_CODE (rtl);
 
-   The RTL for a function can have several slots available: N is
-   which slot to use.  */
+  switch (code)
+    {
+    case HIGH:
+    case CONST_INT:
+    case CONST:
+    case CONST_DOUBLE:
+    case SYMBOL_REF:
+    case LABEL_REF:
+    case PC:
+    case CC0:
+    case SUBREG:
+      return (0);
 
-rtx
-assign_386_stack_local (mode, n)
-     enum machine_mode mode;
-     int n;
-{
-  if (n < 0 || n >= MAX_386_STACK_LOCALS)
-    abort ();
 
-  if (i386_stack_locals[(int) mode][n] == NULL_RTX)
-    i386_stack_locals[(int) mode][n]
-      = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
+    }
 
-  return i386_stack_locals[(int) mode][n];
+  if (code == MEM && reg_mentioned_p (reg, rtl))
+    {
+      return (1);
+    }
+
+  fmt = GET_RTX_FORMAT (code);
+
+  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+    {
+      if (fmt[i] == 'E')
+	{
+	  register int j;
+	  for (j = XVECLEN (rtl, i) - 1; j >= 0; j--)
+	    if (reg_mentioned_in_mem (reg, XVECEXP (rtl, i, j)))
+	      return 1;
+	}
+      else if (fmt[i] == 'e'
+	       && reg_mentioned_in_mem (reg, XEXP (rtl, i)))
+	return 1;
+    }
+  return (0);
 }
+
diff -r -u -H -N gcc-2.6.3/config/i386/i386.c.old gcc-i2.6.3/config/i386/i386.c.old
--- gcc-2.6.3/config/i386/i386.c.old	Wed Dec 31 19:00:00 1969
+++ gcc-i2.6.3/config/i386/i386.c.old	Thu Feb 16 12:42:13 1995
@@ -0,0 +1,3864 @@
+/* Subroutines for insn-output.c for Intel X86.
+   Copyright (C) 1988, 1992, 1994 Free Software Foundation, Inc.
+
+   Pentium cpu support and other enhancements by Tevi Devor Intel Corp.
+   (tevi@iil.intel.com).
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+#include <stdio.h>
+#include <setjmp.h>
+#include "config.h"
+#include "rtl.h"
+#include "regs.h"
+
+/* HACK */
+#ifndef REG_ALLOC_ORDER
+#define REG_ALLOC_ORDER
+#endif
+
+#include "hard-reg-set.h"
+#include "real.h"
+#include "insn-config.h"
+#include "conditions.h"
+#include "insn-flags.h"
+#include "output.h"
+#include "insn-attr.h"
+#include "tree.h"
+#include "flags.h"
+#include "function.h"
+
+/* intel1 Need the EXTRA_CONSTRAINT - changed s to */
+#if 0
+#ifdef EXTRA_CONSTRAINT
+/* If EXTRA_CONSTRAINT is defined, then the 'S'
+   constraint in REG_CLASS_FROM_LETTER will no longer work, and various
+   asm statements that need 'S' for class SIREG will break.  */
+ error EXTRA_CONSTRAINT conflicts with S constraint letter
+/* The previous line used to be #error, but some compilers barf
+   even if the conditional was untrue.  */
+#endif
+#endif
+
+/* which cpu are we scheduling for intel1*/
+enum processor_type x86_cpu;
+
+#define AT_BP(mode) (gen_rtx (MEM, (mode), frame_pointer_rtx))
+
+extern FILE *asm_out_file;
+extern char *strcat ();
+
+char *singlemove_string ();
+char *output_move_const_single ();
+char *output_fp_cc0_set ();
+
+/* intel1 */
+static int opt_level=0;
+
+char *hi_reg_name[] = HI_REGISTER_NAMES;
+char *qi_reg_name[] = QI_REGISTER_NAMES;
+char *qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
+
+/* Array of the smallest class containing reg number REGNO, indexed by
+   REGNO.  Used by REGNO_REG_CLASS in i386.h. */
+
+enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
+{
+  /* ax, dx, cx, bx */
+  AREG, DREG, CREG, BREG,
+  /* si, di, bp, sp */
+  SIREG, DIREG, INDEX_REGS, GENERAL_REGS,
+  /* FP registers */
+  FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
+  FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,       
+  /* arg pointer */
+  INDEX_REGS
+};
+
+/* Test and compare insns in i386.md store the information needed to
+   generate branch and scc insns here.  */
+
+struct rtx_def *i386_compare_op0 = NULL_RTX;
+struct rtx_def *i386_compare_op1 = NULL_RTX;
+struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)();
+
+/* Register allocation order */
+char *i386_reg_alloc_order = (char *)0;
+static char regs_allocated[FIRST_PSEUDO_REGISTER];
+
+
+/* Sometimes certain combinations of command options do not make
+   sense on a particular target machine.  You can define a macro
+   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
+   defined, is executed once just after all the command options have
+   been parsed.
+
+   Don't use this macro to turn on various extra optimizations for
+   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */
+
+void
+override_options ()
+{
+  int ch, i, regno;
+
+#ifdef SUBTARGET_OVERRIDE_OPTIONS
+  SUBTARGET_OVERRIDE_OPTIONS;
+#endif
+
+  /* Validate registers in register allocation order */
+  if (i386_reg_alloc_order)
+    {
+      for (i = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++)
+	{
+	  switch (ch)
+	    {
+	    case 'a':	regno = 0;	break;
+	    case 'd':	regno = 1;	break;
+	    case 'c':	regno = 2;	break;
+	    case 'b':	regno = 3;	break;
+	    case 'S':	regno = 4;	break;
+	    case 'D':	regno = 5;	break;
+	    case 'B':	regno = 6;	break;
+
+	    default:	fatal ("Register '%c' is unknown", ch);
+	    }
+
+	  if (regs_allocated[regno])
+	    fatal ("Register '%c' was already specified in the allocation order", ch);
+
+	  regs_allocated[regno] = 1;
+	}
+    }
+}
+
+/* A C statement (sans semicolon) to choose the order in which to
+   allocate hard registers for pseudo-registers local to a basic
+   block.
+
+   Store the desired register order in the array `reg_alloc_order'.
+   Element 0 should be the register to allocate first; element 1, the
+   next register; and so on.
+
+   The macro body should not assume anything about the contents of
+   `reg_alloc_order' before execution of the macro.
+
+   On most machines, it is not necessary to define this macro.  */
+
+void
+order_regs_for_local_alloc ()
+{
+  int i, ch, order, regno;
+
+  /* User specified the register allocation order */
+  if (i386_reg_alloc_order)
+    {
+      for (i = order = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++)
+	{
+	  switch (ch)
+	    {
+	    case 'a':	regno = 0;	break;
+	    case 'd':	regno = 1;	break;
+	    case 'c':	regno = 2;	break;
+	    case 'b':	regno = 3;	break;
+	    case 'S':	regno = 4;	break;
+	    case 'D':	regno = 5;	break;
+	    case 'B':	regno = 6;	break;
+	    }
+
+	  reg_alloc_order[order++] = regno;
+	}
+
+      for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+	{
+	  if (!regs_allocated[i])
+	    reg_alloc_order[order++] = i;
+	}
+    }
+
+  /* If users did not specify a register allocation order, favor eax
+     normally except if DImode variables are used, in which case
+     favor edx before eax, which seems to cause less spill register
+     not found messages.  */
+  else
+    {
+      rtx insn;
+
+      for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+	reg_alloc_order[i] = i;
+
+      if (optimize)
+	{
+	  int use_dca = FALSE;
+
+	  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
+	    {
+	      if (GET_CODE (insn) == INSN)
+		{
+		  rtx set = NULL_RTX;
+		  rtx pattern = PATTERN (insn);
+
+		  if (GET_CODE (pattern) == SET)
+		    set = pattern;
+
+		  else if ((GET_CODE (pattern) == PARALLEL
+			    || GET_CODE (pattern) == SEQUENCE)
+			   && GET_CODE (XVECEXP (pattern, 0, 0)) == SET)
+		    set = XVECEXP (pattern, 0, 0);
+
+		  if (set && GET_MODE (SET_SRC (set)) == DImode)
+		    {
+		      use_dca = TRUE;
+		      break;
+		    }
+		}
+	    }
+
+	  if (use_dca)
+	    {
+	      reg_alloc_order[0] = 1;	/* edx */
+	      reg_alloc_order[1] = 2;	/* ecx */
+	      reg_alloc_order[2] = 0;	/* eax */
+	    }
+	}
+    }
+}
+
+
+/* Output an insn whose source is a 386 integer register.  SRC is the
+   rtx for the register, and TEMPLATE is the op-code template.  SRC may
+   be either SImode or DImode.
+
+   The template will be output with operands[0] as SRC, and operands[1]
+   as a pointer to the top of the 386 stack.  So a call from floatsidf2
+   would look like this:
+
+      output_op_from_reg (operands[1], AS1 (fild%z0,%1));
+
+   where %z0 corresponds to the caller's operands[1], and is used to
+   emit the proper size suffix.
+
+   ??? Extend this to handle HImode - a 387 can load and store HImode
+   values directly. */
+
+void
+output_op_from_reg (src, template)
+     rtx src;
+     char *template;
+{
+  rtx xops[4];
+  int size = GET_MODE_SIZE (GET_MODE (src));
+
+  xops[0] = src;
+  xops[1] = AT_SP (Pmode);
+  xops[2] = GEN_INT (size);
+  xops[3] = stack_pointer_rtx;
+
+  if (size > UNITS_PER_WORD)
+    {
+      rtx high;
+      if (size > 2 * UNITS_PER_WORD)
+	{
+	  high = gen_rtx (REG, SImode, REGNO (src) + 2);
+	  output_asm_insn (AS1 (push%L0,%0), &high);
+	}
+      high = gen_rtx (REG, SImode, REGNO (src) + 1);
+      output_asm_insn (AS1 (push%L0,%0), &high);
+    }
+  output_asm_insn (AS1 (push%L0,%0), &src);
+
+  output_asm_insn (template, xops);
+
+  output_asm_insn (AS2 (add%L3,%2,%3), xops);
+}
+
+/* Output an insn to pop an value from the 387 top-of-stack to 386
+   register DEST. The 387 register stack is popped if DIES is true.  If
+   the mode of DEST is an integer mode, a `fist' integer store is done,
+   otherwise a `fst' float store is done. */
+
+void
+output_to_reg (dest, dies)
+     rtx dest;
+     int dies;
+{
+  rtx xops[4];
+  int size = GET_MODE_SIZE (GET_MODE (dest));
+
+  xops[0] = AT_SP (Pmode);
+  xops[1] = stack_pointer_rtx;
+  xops[2] = GEN_INT (size);
+  xops[3] = dest;
+
+  output_asm_insn (AS2 (sub%L1,%2,%1), xops);
+
+  if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_INT)
+    {
+      if (dies)
+	output_asm_insn (AS1 (fistp%z3,%y0), xops);
+      else
+	output_asm_insn (AS1 (fist%z3,%y0), xops);
+    }
+  else if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_FLOAT)
+    {
+      if (dies)
+	output_asm_insn (AS1 (fstp%z3,%y0), xops);
+      else
+	{
+	  if (GET_MODE (dest) == XFmode)
+	    {
+	      output_asm_insn (AS1 (fstp%z3,%y0), xops);
+	      output_asm_insn (AS1 (fld%z3,%y0), xops);
+	    }
+	  else
+	    output_asm_insn (AS1 (fst%z3,%y0), xops);
+	}
+    }
+  else
+    abort ();
+
+  output_asm_insn (AS1 (pop%L0,%0), &dest);
+
+  if (size > UNITS_PER_WORD)
+    {
+      dest = gen_rtx (REG, SImode, REGNO (dest) + 1);
+      output_asm_insn (AS1 (pop%L0,%0), &dest);
+      if (size > 2 * UNITS_PER_WORD)
+	{
+	  dest = gen_rtx (REG, SImode, REGNO (dest) + 1);
+	  output_asm_insn (AS1 (pop%L0,%0), &dest);
+	}
+    }
+}
+
+char *
+singlemove_string (operands)
+     rtx *operands;
+{
+  rtx x;
+  if (GET_CODE (operands[0]) == MEM
+      && GET_CODE (x = XEXP (operands[0], 0)) == PRE_DEC)
+    {
+      if (XEXP (x, 0) != stack_pointer_rtx)
+	abort ();
+      return "push%L1 %1";
+    }
+  else if (GET_CODE (operands[1]) == CONST_DOUBLE)
+    {
+      return output_move_const_single (operands);
+    }
+  else if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == REG)
+    return AS2 (mov%L0,%1,%0);
+  else if (CONSTANT_P (operands[1]))
+    return AS2 (mov%L0,%1,%0);
+  else
+    {
+      output_asm_insn ("push%L1 %1", operands);
+      return "pop%L0 %0";
+    }
+}
+
+/* Return a REG that occurs in ADDR with coefficient 1.
+   ADDR can be effectively incremented by incrementing REG.  */
+
+static rtx
+find_addr_reg (addr)
+     rtx addr;
+{
+  while (GET_CODE (addr) == PLUS)
+    {
+      if (GET_CODE (XEXP (addr, 0)) == REG)
+	addr = XEXP (addr, 0);
+      else if (GET_CODE (XEXP (addr, 1)) == REG)
+	addr = XEXP (addr, 1);
+      else if (CONSTANT_P (XEXP (addr, 0)))
+	addr = XEXP (addr, 1);
+      else if (CONSTANT_P (XEXP (addr, 1)))
+	addr = XEXP (addr, 0);
+      else
+	abort ();
+    }
+  if (GET_CODE (addr) == REG)
+    return addr;
+  abort ();
+}
+
+
+/* Output an insn to add the constant N to the register X.  */
+
+static void
+asm_add (n, x)
+     int n;
+     rtx x;
+{
+  rtx xops[2];
+  xops[0] = x;
+
+  if (n == -1)
+    output_asm_insn (AS1 (dec%L0,%0), xops);
+  else if (n == 1)
+    output_asm_insn (AS1 (inc%L0,%0), xops);
+  else if (n < 0)
+    {
+      xops[1] = GEN_INT (-n);
+      output_asm_insn (AS2 (sub%L0,%1,%0), xops);
+    }
+  else if (n > 0)
+    {
+      xops[1] = GEN_INT (n);
+      output_asm_insn (AS2 (add%L0,%1,%0), xops);
+    }
+}
+
+
+/* Output assembler code to perform a doubleword move insn
+   with operands OPERANDS.  */
+
+char *
+output_move_double (operands)
+     rtx *operands;
+{
+  enum {REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
+  rtx latehalf[2];
+  rtx middlehalf[2];
+  rtx xops[2];
+  rtx addreg0 = 0, addreg1 = 0;
+  int dest_overlapped_low = 0;
+  int size = GET_MODE_SIZE (GET_MODE (operands[1]));
+
+  middlehalf[0] = 0;
+  middlehalf[1] = 0;
+
+  /* First classify both operands.  */
+
+  if (REG_P (operands[0]))
+    optype0 = REGOP;
+  else if (offsettable_memref_p (operands[0]))
+    optype0 = OFFSOP;
+  else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
+    optype0 = POPOP;
+  else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
+    optype0 = PUSHOP;
+  else if (GET_CODE (operands[0]) == MEM)
+    optype0 = MEMOP;
+  else
+    optype0 = RNDOP;
+
+  if (REG_P (operands[1]))
+    optype1 = REGOP;
+  else if (CONSTANT_P (operands[1]))
+    optype1 = CNSTOP;
+  else if (offsettable_memref_p (operands[1]))
+    optype1 = OFFSOP;
+  else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
+    optype1 = POPOP;
+  else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
+    optype1 = PUSHOP;
+  else if (GET_CODE (operands[1]) == MEM)
+    optype1 = MEMOP;
+  else
+    optype1 = RNDOP;
+
+  /* Check for the cases that the operand constraints are not
+     supposed to allow to happen.  Abort if we get one,
+     because generating code for these cases is painful.  */
+
+  if (optype0 == RNDOP || optype1 == RNDOP)
+    abort ();
+
+  /* If one operand is decrementing and one is incrementing
+     decrement the former register explicitly
+     and change that operand into ordinary indexing.  */
+
+  if (optype0 == PUSHOP && optype1 == POPOP)
+    {
+      /* ??? Can this ever happen on i386? */
+      operands[0] = XEXP (XEXP (operands[0], 0), 0);
+      asm_add (-size, operands[0]);
+      if (GET_MODE (operands[1]) == XFmode)
+        operands[0] = gen_rtx (MEM, XFmode, operands[0]);
+      else if (GET_MODE (operands[0]) == DFmode)
+        operands[0] = gen_rtx (MEM, DFmode, operands[0]);
+      else
+        operands[0] = gen_rtx (MEM, DImode, operands[0]);
+      optype0 = OFFSOP;
+    }
+
+  if (optype0 == POPOP && optype1 == PUSHOP)
+    {
+      /* ??? Can this ever happen on i386? */
+      operands[1] = XEXP (XEXP (operands[1], 0), 0);
+      asm_add (-size, operands[1]);
+      if (GET_MODE (operands[1]) == XFmode)
+        operands[1] = gen_rtx (MEM, XFmode, operands[1]);
+      else if (GET_MODE (operands[1]) == DFmode)
+        operands[1] = gen_rtx (MEM, DFmode, operands[1]);
+      else
+        operands[1] = gen_rtx (MEM, DImode, operands[1]);
+      optype1 = OFFSOP;
+    }
+
+  /* If an operand is an unoffsettable memory ref, find a register
+     we can increment temporarily to make it refer to the second word.  */
+
+  if (optype0 == MEMOP)
+    addreg0 = find_addr_reg (XEXP (operands[0], 0));
+
+  if (optype1 == MEMOP)
+    addreg1 = find_addr_reg (XEXP (operands[1], 0));
+
+  /* Ok, we can do one word at a time.
+     Normally we do the low-numbered word first,
+     but if either operand is autodecrementing then we
+     do the high-numbered word first.
+
+     In either case, set up in LATEHALF the operands to use
+     for the high-numbered word and in some cases alter the
+     operands in OPERANDS to be suitable for the low-numbered word.  */
+
+  if (size == 12)
+    {
+      if (optype0 == REGOP)
+	{
+	  middlehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
+	  latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2);
+	}
+      else if (optype0 == OFFSOP)
+	{
+	  middlehalf[0] = adj_offsettable_operand (operands[0], 4);
+	  latehalf[0] = adj_offsettable_operand (operands[0], 8);
+	}
+      else
+	{
+         middlehalf[0] = operands[0];
+         latehalf[0] = operands[0];
+	}
+    
+      if (optype1 == REGOP)
+	{
+          middlehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
+          latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
+	}
+      else if (optype1 == OFFSOP)
+	{
+          middlehalf[1] = adj_offsettable_operand (operands[1], 4);
+          latehalf[1] = adj_offsettable_operand (operands[1], 8);
+	}
+      else if (optype1 == CNSTOP)
+	{
+	  if (GET_CODE (operands[1]) == CONST_DOUBLE)
+	    {
+	      REAL_VALUE_TYPE r; long l[3];
+
+	      REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
+	      REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
+	      operands[1] = GEN_INT (l[0]);
+	      middlehalf[1] = GEN_INT (l[1]);
+	      latehalf[1] = GEN_INT (l[2]);
+	    }
+	  else if (CONSTANT_P (operands[1]))
+	    /* No non-CONST_DOUBLE constant should ever appear here.  */
+	    abort ();
+        }
+      else
+	{
+	  middlehalf[1] = operands[1];
+	  latehalf[1] = operands[1];
+	}
+    }
+  else /* size is not 12: */
+    {
+      if (optype0 == REGOP)
+	latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
+      else if (optype0 == OFFSOP)
+	latehalf[0] = adj_offsettable_operand (operands[0], 4);
+      else
+	latehalf[0] = operands[0];
+
+      if (optype1 == REGOP)
+	latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
+      else if (optype1 == OFFSOP)
+	latehalf[1] = adj_offsettable_operand (operands[1], 4);
+      else if (optype1 == CNSTOP)
+	{
+	  if (GET_CODE (operands[1]) == CONST_DOUBLE)
+	    split_double (operands[1], &operands[1], &latehalf[1]);
+	  else if (CONSTANT_P (operands[1]))
+	    {
+	      /* ??? jrv: Can this really happen?  A DImode constant
+		 that isn't a CONST_DOUBLE? */
+	      if (GET_CODE (operands[1]) == CONST_INT
+		  && INTVAL (operands[1]) < 0)
+	        latehalf[1] = constm1_rtx;
+	      else
+	        latehalf[1] = const0_rtx;
+	    }
+	}
+      else
+	latehalf[1] = operands[1];
+    }
+
+  /* If insn is effectively movd N (sp),-(sp) then we will do the
+     high word first.  We should use the adjusted operand 1
+     (which is N+4 (sp) or N+8 (sp))
+     for the low word and middle word as well,
+     to compensate for the first decrement of sp.  */
+  if (optype0 == PUSHOP
+      && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
+      && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
+    middlehalf[1] = operands[1] = latehalf[1];
+
+  /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
+     if the upper part of reg N does not appear in the MEM, arrange to
+     emit the move late-half first.  Otherwise, compute the MEM address
+     into the upper part of N and use that as a pointer to the memory
+     operand.  */
+  if (optype0 == REGOP
+      && (optype1 == OFFSOP || optype1 == MEMOP))
+    {
+      if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
+	  && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
+	{
+	  /* If both halves of dest are used in the src memory address,
+	     compute the address into latehalf of dest.  */
+compadr:
+	  xops[0] = latehalf[0];
+	  xops[1] = XEXP (operands[1], 0);
+	  output_asm_insn (AS2 (lea%L0,%a1,%0), xops);
+	  if( GET_MODE (operands[1]) == XFmode )
+	    {
+/*	    abort (); */
+	      operands[1] = gen_rtx (MEM, XFmode, latehalf[0]);
+	      middlehalf[1] = adj_offsettable_operand (operands[1], size-8);
+	      latehalf[1] = adj_offsettable_operand (operands[1], size-4);
+	    }
+	  else
+	    {
+	      operands[1] = gen_rtx (MEM, DImode, latehalf[0]);
+	      latehalf[1] = adj_offsettable_operand (operands[1], size-4);
+	    }
+	}
+      else if (size == 12
+		 && reg_mentioned_p (middlehalf[0], XEXP (operands[1], 0)))
+	{
+	  /* Check for two regs used by both source and dest. */
+	  if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
+		|| reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
+		goto compadr;
+
+	  /* JRV says this can't happen: */
+	  if (addreg0 || addreg1)
+	      abort();
+
+	  /* Only the middle reg conflicts; simply put it last. */
+	  output_asm_insn (singlemove_string (operands), operands);
+	  output_asm_insn (singlemove_string (latehalf), latehalf);
+	  output_asm_insn (singlemove_string (middlehalf), middlehalf);
+	  return "";
+	}
+      else if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)))
+	/* If the low half of dest is mentioned in the source memory
+	   address, the arrange to emit the move late half first.  */
+	dest_overlapped_low = 1;
+    }
+
+  /* If one or both operands autodecrementing,
+     do the two words, high-numbered first.  */
+
+  /* Likewise,  the first move would clobber the source of the second one,
+     do them in the other order.  This happens only for registers;
+     such overlap can't happen in memory unless the user explicitly
+     sets it up, and that is an undefined circumstance.  */
+
+/*
+  if (optype0 == PUSHOP || optype1 == PUSHOP
+      || (optype0 == REGOP && optype1 == REGOP
+	  && REGNO (operands[0]) == REGNO (latehalf[1]))
+      || dest_overlapped_low)
+*/
+  if (optype0 == PUSHOP || optype1 == PUSHOP
+      || (optype0 == REGOP && optype1 == REGOP
+	  && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
+	      || REGNO (operands[0]) == REGNO (latehalf[1])))
+      || dest_overlapped_low)
+    {
+      /* Make any unoffsettable addresses point at high-numbered word.  */
+      if (addreg0)
+	asm_add (size-4, addreg0);
+      if (addreg1)
+	asm_add (size-4, addreg1);
+
+      /* Do that word.  */
+      output_asm_insn (singlemove_string (latehalf), latehalf);
+
+      /* Undo the adds we just did.  */
+      if (addreg0)
+         asm_add (-4, addreg0);
+      if (addreg1)
+	asm_add (-4, addreg1);
+
+      if (size == 12)
+        {
+        output_asm_insn (singlemove_string (middlehalf), middlehalf);
+        if (addreg0)
+           asm_add (-4, addreg0);
+        if (addreg1)
+	   asm_add (-4, addreg1);
+	}
+
+      /* Do low-numbered word.  */
+      return singlemove_string (operands);
+    }
+
+  /* Normal case: do the two words, low-numbered first.  */
+
+  output_asm_insn (singlemove_string (operands), operands);
+
+  /* Do the middle one of the three words for long double */
+  if (size == 12)
+    {
+      if (addreg0)
+        asm_add (4, addreg0);
+      if (addreg1)
+        asm_add (4, addreg1);
+
+      output_asm_insn (singlemove_string (middlehalf), middlehalf);
+    }
+
+  /* Make any unoffsettable addresses point at high-numbered word.  */
+  if (addreg0)
+    asm_add (4, addreg0);
+  if (addreg1)
+    asm_add (4, addreg1);
+
+  /* Do that word.  */
+  output_asm_insn (singlemove_string (latehalf), latehalf);
+
+  /* Undo the adds we just did.  */
+  if (addreg0)
+    asm_add (4-size, addreg0);
+  if (addreg1)
+    asm_add (4-size, addreg1);
+
+  return "";
+}
+
+
+#define MAX_TMPS 2		/* max temporary registers used */
+
+/* Output the appropriate code to move push memory on the stack */
+
+char *
+output_move_pushmem (operands, insn, length, tmp_start, n_operands)
+     rtx operands[];
+     rtx insn;
+     int length;
+     int tmp_start;
+     int n_operands;
+{
+
+  struct {
+    char *load;
+    char *push;
+    rtx   xops[2];
+  } tmp_info[MAX_TMPS];
+
+  rtx src = operands[1];
+  int max_tmps = 0;
+  int offset = 0;
+  int stack_p = reg_overlap_mentioned_p (stack_pointer_rtx, src);
+  int stack_offset = 0;
+  int i, num_tmps;
+  rtx xops[1];
+
+  if (!offsettable_memref_p (src))
+    fatal_insn ("Source is not offsettable", insn);
+
+  if ((length & 3) != 0)
+    fatal_insn ("Pushing non-word aligned size", insn);
+
+  /* Figure out which temporary registers we have available */
+  for (i = tmp_start; i < n_operands; i++)
+    {
+      if (GET_CODE (operands[i]) == REG)
+	{
+	  if (reg_overlap_mentioned_p (operands[i], src))
+	    continue;
+
+	  tmp_info[ max_tmps++ ].xops[1] = operands[i];
+	  if (max_tmps == MAX_TMPS)
+	    break;
+	}
+    }
+
+  if (max_tmps == 0)
+    for (offset = length - 4; offset >= 0; offset -= 4)
+      {
+	xops[0] = adj_offsettable_operand (src, offset + stack_offset);
+	output_asm_insn (AS1(push%L0,%0), xops);
+	if (stack_p)
+	  stack_offset += 4;
+      }
+
+  else
+    for (offset = length - 4; offset >= 0; )
+      {
+	for (num_tmps = 0; num_tmps < max_tmps && offset >= 0; num_tmps++)
+	  {
+	    tmp_info[num_tmps].load    = AS2(mov%L0,%0,%1);
+	    tmp_info[num_tmps].push    = AS1(push%L0,%1);
+	    tmp_info[num_tmps].xops[0] = adj_offsettable_operand (src, offset + stack_offset);
+	    offset -= 4;
+	  }
+
+	for (i = 0; i < num_tmps; i++)
+	  output_asm_insn (tmp_info[i].load, tmp_info[i].xops);
+
+	for (i = 0; i < num_tmps; i++)
+	  output_asm_insn (tmp_info[i].push, tmp_info[i].xops);
+
+	if (stack_p)
+	  stack_offset += 4*num_tmps;
+      }
+
+  return "";
+}
+
+
+
+/* Output the appropriate code to move data between two memory locations */
+
+char *
+output_move_memory (operands, insn, length, tmp_start, n_operands)
+     rtx operands[];
+     rtx insn;
+     int length;
+     int tmp_start;
+     int n_operands;
+{
+  struct {
+    char *load;
+    char *store;
+    rtx   xops[3];
+  } tmp_info[MAX_TMPS];
+
+  rtx dest = operands[0];
+  rtx src  = operands[1];
+  rtx qi_tmp = NULL_RTX;
+  int max_tmps = 0;
+  int offset = 0;
+  int i, num_tmps;
+  rtx xops[3];
+
+  if (GET_CODE (dest) == MEM
+      && GET_CODE (XEXP (dest, 0)) == PRE_INC
+      && XEXP (XEXP (dest, 0), 0) == stack_pointer_rtx)
+    return output_move_pushmem (operands, insn, length, tmp_start, n_operands);
+
+  if (!offsettable_memref_p (src))
+    fatal_insn ("Source is not offsettable", insn);
+
+  if (!offsettable_memref_p (dest))
+    fatal_insn ("Destination is not offsettable", insn);
+
+  /* Figure out which temporary registers we have available */
+  for (i = tmp_start; i < n_operands; i++)
+    {
+      if (GET_CODE (operands[i]) == REG)
+	{
+	  if ((length & 1) != 0 && !qi_tmp && QI_REG_P (operands[i]))
+	    qi_tmp = operands[i];
+
+	  if (reg_overlap_mentioned_p (operands[i], dest))
+	    fatal_insn ("Temporary register overlaps the destination", insn);
+
+	  if (reg_overlap_mentioned_p (operands[i], src))
+	    fatal_insn ("Temporary register overlaps the source", insn);
+
+	  tmp_info[ max_tmps++ ].xops[2] = operands[i];
+	  if (max_tmps == MAX_TMPS)
+	    break;
+	}
+    }
+
+  if (max_tmps == 0)
+    fatal_insn ("No scratch registers were found to do memory->memory moves", insn);
+
+  if ((length & 1) != 0)
+    {
+      if (!qi_tmp)
+	fatal_insn ("No byte register found when moving odd # of bytes.", insn);
+    }
+
+  while (length > 1)
+    {
+      for (num_tmps = 0; num_tmps < max_tmps; num_tmps++)
+	{
+	  if (length >= 4)
+	    {
+	      tmp_info[num_tmps].load    = AS2(mov%L0,%1,%2);
+	      tmp_info[num_tmps].store   = AS2(mov%L0,%2,%0);
+	      tmp_info[num_tmps].xops[0] = adj_offsettable_operand (dest, offset);
+	      tmp_info[num_tmps].xops[1] = adj_offsettable_operand (src, offset);
+	      offset += 4;
+	      length -= 4;
+	    }
+	  else if (length >= 2)
+	    {
+	      tmp_info[num_tmps].load    = AS2(mov%W0,%1,%2);
+	      tmp_info[num_tmps].store   = AS2(mov%W0,%2,%0);
+	      tmp_info[num_tmps].xops[0] = adj_offsettable_operand (dest, offset);
+	      tmp_info[num_tmps].xops[1] = adj_offsettable_operand (src, offset);
+	      offset += 2;
+	      length -= 2;
+	    }
+	  else
+	    break;
+	}
+
+      for (i = 0; i < num_tmps; i++)
+	output_asm_insn (tmp_info[i].load, tmp_info[i].xops);
+
+      for (i = 0; i < num_tmps; i++)
+	output_asm_insn (tmp_info[i].store, tmp_info[i].xops);
+    }
+
+  if (length == 1)
+    {
+      xops[0] = adj_offsettable_operand (dest, offset);
+      xops[1] = adj_offsettable_operand (src, offset);
+      xops[2] = qi_tmp;
+      output_asm_insn (AS2(mov%B0,%1,%2), xops);
+      output_asm_insn (AS2(mov%B0,%2,%0), xops);
+    }
+
+  return "";
+}
+
+
+int
+standard_80387_constant_p (x)
+     rtx x;
+{
+#if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC)
+  REAL_VALUE_TYPE d;
+  jmp_buf handler;
+  int is0, is1;
+
+  if (setjmp (handler))
+    return 0;
+
+  set_float_handler (handler);
+  REAL_VALUE_FROM_CONST_DOUBLE (d, x);
+  is0 = REAL_VALUES_EQUAL (d, dconst0);
+  is1 = REAL_VALUES_EQUAL (d, dconst1);
+  set_float_handler (NULL_PTR);
+
+  if (is0)
+    return 1;
+
+  if (is1)
+    return 2;
+
+  /* Note that on the 80387, other constants, such as pi,
+     are much slower to load as standard constants
+     than to load from doubles in memory!  */
+#endif
+
+  return 0;
+}
+
+char *
+output_move_const_single (operands)
+     rtx *operands;
+{
+  if (FP_REG_P (operands[0]))
+    {
+      int conval = standard_80387_constant_p (operands[1]);
+
+      if (conval == 1)
+	return "fldz";
+
+      if (conval == 2)
+	return "fld1";
+    }
+  if (GET_CODE (operands[1]) == CONST_DOUBLE)
+    {
+      REAL_VALUE_TYPE r; long l;
+
+      if (GET_MODE (operands[1]) == XFmode)
+	abort ();
+
+      REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
+      REAL_VALUE_TO_TARGET_SINGLE (r, l);
+      operands[1] = GEN_INT (l);
+    }
+  return singlemove_string (operands);
+}
+
+/* Returns 1 if OP is either a symbol reference or a sum of a symbol
+   reference and a constant.  */
+
+int
+symbolic_operand (op, mode)
+     register rtx op;
+     enum machine_mode mode;
+{
+  switch (GET_CODE (op))
+    {
+    case SYMBOL_REF:
+    case LABEL_REF:
+      return 1;
+    case CONST:
+      op = XEXP (op, 0);
+      return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
+	       || GET_CODE (XEXP (op, 0)) == LABEL_REF)
+	      && GET_CODE (XEXP (op, 1)) == CONST_INT);
+    default:
+      return 0;
+    }
+}
+
+/* Test for a valid operand for a call instruction.
+   Don't allow the arg pointer register or virtual regs
+   since they may change into reg + const, which the patterns
+   can't handle yet.  */
+
+int
+call_insn_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) == MEM
+      && ((CONSTANT_ADDRESS_P (XEXP (op, 0))
+	   /* This makes a difference for PIC.  */
+	   && general_operand (XEXP (op, 0), Pmode))
+	  || (GET_CODE (XEXP (op, 0)) == REG
+	      && XEXP (op, 0) != arg_pointer_rtx
+	      && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
+		   && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
+    return 1;
+  return 0;
+}
+
+/* Like call_insn_operand but allow (mem (symbol_ref ...))
+   even if pic.  */
+
+int
+expander_call_insn_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) == MEM
+      && (CONSTANT_ADDRESS_P (XEXP (op, 0))
+	  || (GET_CODE (XEXP (op, 0)) == REG
+	      && XEXP (op, 0) != arg_pointer_rtx
+	      && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
+		   && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
+    return 1;
+  return 0;
+}
+
+/* Returns 1 if OP contains a symbol reference */
+
+int
+symbolic_reference_mentioned_p (op)
+     rtx op;
+{
+  register char *fmt;
+  register int i;
+
+  if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
+    return 1;
+
+  fmt = GET_RTX_FORMAT (GET_CODE (op));
+  for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
+    {
+      if (fmt[i] == 'E')
+	{
+	  register int j;
+
+	  for (j = XVECLEN (op, i) - 1; j >= 0; j--)
+	    if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
+	      return 1;
+	}
+      else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
+	return 1;
+    }
+
+  return 0;
+}
+
+/* This function generates the assembly code for function entry.
+   FILE is an stdio stream to output the code to.
+   SIZE is an int: how many units of temporary storage to allocate. */
+
+void
+function_prologue (file, size)
+     FILE *file;
+     int size;
+{
+  register int regno;
+  int limit;
+  rtx xops[4];
+  int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
+				  || current_function_uses_const_pool);
+
+  xops[0] = stack_pointer_rtx;
+  xops[1] = frame_pointer_rtx;
+  xops[2] = GEN_INT (size);
+  if (frame_pointer_needed)
+    {
+      output_asm_insn ("push%L1 %1", xops);
+      output_asm_insn (AS2 (mov%L0,%0,%1), xops);
+    }
+
+  if (size)
+    output_asm_insn (AS2 (sub%L0,%2,%0), xops);
+
+  /* Note If use enter it is NOT reversed args.
+     This one is not reversed from intel!!
+     I think enter is slower.  Also sdb doesn't like it.
+     But if you want it the code is:
+     {
+     xops[3] = const0_rtx;
+     output_asm_insn ("enter %2,%3", xops);
+     }
+     */
+  limit = (frame_pointer_needed ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
+  for (regno = limit - 1; regno >= 0; regno--)
+    if ((regs_ever_live[regno] && ! call_used_regs[regno])
+	|| (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
+      {
+	xops[0] = gen_rtx (REG, SImode, regno);
+	output_asm_insn ("push%L0 %0", xops);
+      }
+
+  if (pic_reg_used)
+    {
+      xops[0] = pic_offset_table_rtx;
+      xops[1] = (rtx) gen_label_rtx ();
+
+      output_asm_insn (AS1 (call,%P1), xops);
+      ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (xops[1]));
+      output_asm_insn (AS1 (pop%L0,%0), xops);
+      output_asm_insn ("addl $_GLOBAL_OFFSET_TABLE_+[.-%P1],%0", xops);
+    }
+}
+
+/* Return 1 if it is appropriate to emit `ret' instructions in the
+   body of a function.  Do this only if the epilogue is simple, needing a
+   couple of insns.  Prior to reloading, we can't tell how many registers
+   must be saved, so return 0 then.
+
+   If NON_SAVING_SETJMP is defined and true, then it is not possible
+   for the epilogue to be simple, so return 0.  This is a special case
+   since NON_SAVING_SETJMP will not cause regs_ever_live to change until
+   final, but jump_optimize may need to know sooner if a `return' is OK.  */
+
+int
+simple_386_epilogue ()
+{
+  int regno;
+  int nregs = 0;
+  int reglimit = (frame_pointer_needed
+		  ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
+  int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
+				  || current_function_uses_const_pool);
+
+#ifdef NON_SAVING_SETJMP
+  if (NON_SAVING_SETJMP && current_function_calls_setjmp)
+    return 0;
+#endif
+
+  if (! reload_completed)
+    return 0;
+
+  for (regno = reglimit - 1; regno >= 0; regno--)
+    if ((regs_ever_live[regno] && ! call_used_regs[regno])
+	|| (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
+      nregs++;
+
+  return nregs == 0 || ! frame_pointer_needed;
+}
+
+
+/* This function generates the assembly code for function exit.
+   FILE is an stdio stream to output the code to.
+   SIZE is an int: how many units of temporary storage to deallocate. */
+
+void
+function_epilogue (file, size)
+     FILE *file;
+     int size;
+{
+  register int regno;
+  register int nregs, limit;
+  int offset;
+  rtx xops[3];
+  int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
+				  || current_function_uses_const_pool);
+
+  /* Compute the number of registers to pop */
+
+  limit = (frame_pointer_needed
+	   ? FRAME_POINTER_REGNUM
+	   : STACK_POINTER_REGNUM);
+
+  nregs = 0;
+
+  for (regno = limit - 1; regno >= 0; regno--)
+    if ((regs_ever_live[regno] && ! call_used_regs[regno])
+	|| (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
+      nregs++;
+
+  /* sp is often  unreliable so we must go off the frame pointer,
+   */
+
+  /* In reality, we may not care if sp is unreliable, because we can
+     restore the register relative to the frame pointer.  In theory,
+     since each move is the same speed as a pop, and we don't need the
+     leal, this is faster.  For now restore multiple registers the old
+     way. */
+
+  offset = -size - (nregs * UNITS_PER_WORD);
+
+  xops[2] = stack_pointer_rtx;
+
+  if (nregs > 1 || ! frame_pointer_needed)
+    {
+      if (frame_pointer_needed)
+	{
+	  xops[0] = adj_offsettable_operand (AT_BP (Pmode), offset);
+	  output_asm_insn (AS2 (lea%L2,%0,%2), xops);
+	}
+
+      for (regno = 0; regno < limit; regno++)
+	if ((regs_ever_live[regno] && ! call_used_regs[regno])
+	    || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
+	  {
+	    xops[0] = gen_rtx (REG, SImode, regno);
+	    output_asm_insn ("pop%L0 %0", xops);
+	  }
+    }
+  else
+    for (regno = 0; regno < limit; regno++)
+      if ((regs_ever_live[regno] && ! call_used_regs[regno])
+	  || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
+	{
+	  xops[0] = gen_rtx (REG, SImode, regno);
+	  xops[1] = adj_offsettable_operand (AT_BP (Pmode), offset);
+	  output_asm_insn (AS2 (mov%L0,%1,%0), xops);
+	  offset += 4;
+	}
+
+  if (frame_pointer_needed)
+    {
+      /* On i486, mov & pop is faster than "leave". */
+
+      if (!TARGET_386)
+	{
+	  xops[0] = frame_pointer_rtx;
+	  output_asm_insn (AS2 (mov%L2,%0,%2), xops);
+	  output_asm_insn ("pop%L0 %0", xops);
+	}
+      else
+	output_asm_insn ("leave", xops);
+    }
+  else if (size)
+    {
+      /* If there is no frame pointer, we must still release the frame. */
+
+      xops[0] = GEN_INT (size);
+      output_asm_insn (AS2 (add%L2,%0,%2), xops);
+    }
+
+  if (current_function_pops_args && current_function_args_size)
+    {
+      xops[1] = GEN_INT (current_function_pops_args);
+
+      /* i386 can only pop 32K bytes (maybe 64K?  Is it signed?).  If
+	 asked to pop more, pop return address, do explicit add, and jump
+	 indirectly to the caller. */
+
+      if (current_function_pops_args >= 32768)
+	{
+	  /* ??? Which register to use here? */
+	  xops[0] = gen_rtx (REG, SImode, 2);
+	  output_asm_insn ("pop%L0 %0", xops);
+	  output_asm_insn (AS2 (add%L2,%1,%2), xops);
+	  output_asm_insn ("jmp %*%0", xops);
+	}
+      else
+	  output_asm_insn ("ret %1", xops);
+    }
+  else
+    output_asm_insn ("ret", xops);
+}
+
+
+/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
+   that is a valid memory address for an instruction.
+   The MODE argument is the machine mode for the MEM expression
+   that wants to use this address.
+
+   On x86, legitimate addresses are:
+	base				movl (base),reg
+	displacement			movl disp,reg
+	base + displacement		movl disp(base),reg
+	index + base			movl (base,index),reg
+	(index + base) + displacement	movl disp(base,index),reg
+	index*scale			movl (,index,scale),reg
+	index*scale + disp		movl disp(,index,scale),reg
+	index*scale + base 		movl (base,index,scale),reg
+	(index*scale + base) + disp	movl disp(base,index,scale),reg
+
+	In each case, scale can be 1, 2, 4, 8.  */
+
+/* This is exactly the same as print_operand_addr, except that
+   it recognizes addresses instead of printing them.
+
+   It only recognizes address in canonical form.  LEGITIMIZE_ADDRESS should
+   convert common non-canonical forms to canonical form so that they will
+   be recognized.  */
+
+#define ADDR_INVALID(msg,insn)						\
+do {									\
+  if (TARGET_DEBUG_ADDR)						\
+    {									\
+      fprintf (stderr, msg);						\
+      debug_rtx (insn);							\
+    }									\
+} while (0)
+
+int
+legitimate_address_p (mode, addr, strict)
+     enum machine_mode mode;
+     register rtx addr;
+     int strict;
+{
+  rtx base  = NULL_RTX;
+  rtx indx  = NULL_RTX;
+  rtx scale = NULL_RTX;
+  rtx disp  = NULL_RTX;
+
+  if (TARGET_DEBUG_ADDR)
+    {
+      fprintf (stderr,
+	       "\n==========\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n",
+	       GET_MODE_NAME (mode), strict);
+
+      debug_rtx (addr);
+    }
+
+  if (GET_CODE (addr) == REG || GET_CODE (addr) == SUBREG)
+      base = addr;				/* base reg */
+
+  else if (GET_CODE (addr) == PLUS)
+    {
+      rtx op0 = XEXP (addr, 0);
+      rtx op1 = XEXP (addr, 1);
+      enum rtx_code code0 = GET_CODE (op0);
+      enum rtx_code code1 = GET_CODE (op1);
+
+      if (code0 == REG || code0 == SUBREG)
+	{
+	  if (code1 == REG || code1 == SUBREG)
+	    {
+	      indx = op0;			/* index + base */
+	      base = op1;
+	    }
+
+	  else
+	    {
+	      base = op0;			/* base + displacement */
+	      disp = op1;
+	    }
+	}
+
+      else if (code0 == MULT)
+	{
+	  indx  = XEXP (op0, 0);
+	  scale = XEXP (op0, 1);
+
+	  if (code1 == REG || code1 == SUBREG)
+	    base = op1;				/* index*scale + base */
+
+	  else
+	    disp = op1;				/* index*scale + disp */
+	}
+
+      else if (code0 == PLUS && GET_CODE (XEXP (op0, 0)) == MULT)
+	{
+	  indx  = XEXP (XEXP (op0, 0), 0);	/* index*scale + base + disp */
+	  scale = XEXP (XEXP (op0, 0), 1);
+	  base  = XEXP (op0, 1);
+	  disp  = op1;
+	}
+
+      else if (code0 == PLUS)
+	{
+	  indx = XEXP (op0, 0);			/* index + base + disp */
+	  base = XEXP (op0, 1);
+	  disp = op1;
+	}
+
+      else
+	{
+	  ADDR_INVALID ("PLUS subcode is not valid.\n", op0);
+	  return FALSE;
+	}
+    }
+
+  else if (GET_CODE (addr) == MULT)
+    {
+      indx  = XEXP (addr, 0);			/* index*scale */
+      scale = XEXP (addr, 1);
+    }
+
+  else
+    disp = addr;				/* displacement */
+
+  /* Allow arg pointer and stack pointer as index if there is not scaling */
+  if (base && indx && !scale
+      && (indx == arg_pointer_rtx || indx == stack_pointer_rtx))
+    {
+      rtx tmp = base;
+      base = indx;
+      indx = tmp;
+    }
+
+  /* Validate base register */
+  /* Don't allow SUBREG's here, it can lead to spill failures when the base
+     is one word out of a two word structure, which is represented internally
+     as a DImode int.  */
+  if (base)
+    {
+      if (GET_CODE (base) != REG)
+	{
+	  ADDR_INVALID ("Base is not a register.\n", base);
+	  return FALSE;
+	}
+
+      if ((strict && !REG_OK_FOR_BASE_STRICT_P (base))
+	  || (!strict && !REG_OK_FOR_BASE_NONSTRICT_P (base)))
+	{
+	  ADDR_INVALID ("Base is not valid.\n", base);
+	  return FALSE;
+	}
+    }
+
+  /* Validate index register */
+  /* Don't allow SUBREG's here, it can lead to spill failures when the index
+     is one word out of a two word structure, which is represented internally
+     as a DImode int.  */
+  if (indx)
+    {
+      if (GET_CODE (indx) != REG)
+	{
+	  ADDR_INVALID ("Index is not a register.\n", indx);
+	  return FALSE;
+	}
+
+      if ((strict && !REG_OK_FOR_INDEX_STRICT_P (indx))
+	  || (!strict && !REG_OK_FOR_INDEX_NONSTRICT_P (indx)))
+	{
+	  ADDR_INVALID ("Index is not valid.\n", indx);
+	  return FALSE;
+	}
+    }
+  else if (scale)
+    abort ();					/* scale w/o index illegal */
+
+  /* Validate scale factor */
+  if (scale)
+    {
+      HOST_WIDE_INT value;
+
+      if (GET_CODE (scale) != CONST_INT)
+	{
+	  ADDR_INVALID ("Scale is not valid.\n", scale);
+	  return FALSE;
+	}
+
+      value = INTVAL (scale);
+      if (value != 1 && value != 2 && value != 4 && value != 8)
+	{
+	  ADDR_INVALID ("Scale is not a good multiplier.\n", scale);
+	  return FALSE;
+	}
+    }
+
+  /* Validate displacement */
+  if (disp)
+    {
+      if (!CONSTANT_ADDRESS_P (disp))
+	{
+	  ADDR_INVALID ("Displacement is not valid.\n", disp);
+	  return FALSE;
+	}
+
+      if (GET_CODE (disp) == CONST_DOUBLE)
+	{
+	  ADDR_INVALID ("Displacement is a const_double.\n", disp);
+	  return FALSE;
+	}
+
+      if (flag_pic && SYMBOLIC_CONST (disp) && base != pic_offset_table_rtx
+	  && (indx != pic_offset_table_rtx || scale != NULL_RTX))
+	{
+	  ADDR_INVALID ("Displacement is an invalid pic reference.\n", disp);
+	  return FALSE;
+	}
+
+      if (HALF_PIC_P () && HALF_PIC_ADDRESS_P (disp)
+	  && (base != NULL_RTX || indx != NULL_RTX))
+	{
+	  ADDR_INVALID ("Displacement is an invalid half-pic reference.\n", disp);
+	  return FALSE;
+	}
+    }
+
+  if (TARGET_DEBUG_ADDR)
+    fprintf (stderr, "Address is valid.\n");
+
+  /* Everything looks valid, return true */
+  return TRUE;
+}
+
+
+/* Return a legitimate reference for ORIG (an address) using the
+   register REG.  If REG is 0, a new pseudo is generated.
+
+   There are three types of references that must be handled:
+
+   1. Global data references must load the address from the GOT, via
+      the PIC reg.  An insn is emitted to do this load, and the reg is
+      returned.
+
+   2. Static data references must compute the address as an offset
+      from the GOT, whose base is in the PIC reg.  An insn is emitted to
+      compute the address into a reg, and the reg is returned.  Static
+      data objects have SYMBOL_REF_FLAG set to differentiate them from
+      global data objects.
+
+   3. Constant pool addresses must be handled special.  They are
+      considered legitimate addresses, but only if not used with regs.
+      When printed, the output routines know to print the reference with the
+      PIC reg, even though the PIC reg doesn't appear in the RTL.
+
+   GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
+   reg also appears in the address (except for constant pool references,
+   noted above).
+
+   "switch" statements also require special handling when generating
+   PIC code.  See comments by the `casesi' insn in i386.md for details.  */
+
+rtx
+legitimize_pic_address (orig, reg)
+     rtx orig;
+     rtx reg;
+{
+  rtx addr = orig;
+  rtx new = orig;
+
+  if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
+    {
+      if (GET_CODE (addr) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (addr))
+	reg = new = orig;
+      else
+	{
+	  if (reg == 0)
+	    reg = gen_reg_rtx (Pmode);
+
+	  if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_FLAG (addr))
+	      || GET_CODE (addr) == LABEL_REF)
+	    new = gen_rtx (PLUS, Pmode, pic_offset_table_rtx, orig);
+	  else
+	    new = gen_rtx (MEM, Pmode,
+			   gen_rtx (PLUS, Pmode,
+				    pic_offset_table_rtx, orig));
+
+	  emit_move_insn (reg, new);
+	}
+      current_function_uses_pic_offset_table = 1;
+      return reg;
+    }
+  else if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS)
+    {
+      rtx base;
+
+      if (GET_CODE (addr) == CONST)
+	{
+	  addr = XEXP (addr, 0);
+	  if (GET_CODE (addr) != PLUS)
+	    abort ();
+	}
+
+      if (XEXP (addr, 0) == pic_offset_table_rtx)
+	return orig;
+
+      if (reg == 0)
+	reg = gen_reg_rtx (Pmode);
+
+      base = legitimize_pic_address (XEXP (addr, 0), reg);
+      addr = legitimize_pic_address (XEXP (addr, 1),
+				     base == reg ? NULL_RTX : reg);
+
+      if (GET_CODE (addr) == CONST_INT)
+	return plus_constant (base, INTVAL (addr));
+
+      if (GET_CODE (addr) == PLUS && CONSTANT_P (XEXP (addr, 1)))
+	{
+	  base = gen_rtx (PLUS, Pmode, base, XEXP (addr, 0));
+	  addr = XEXP (addr, 1);
+	}
+	return gen_rtx (PLUS, Pmode, base, addr);
+    }
+  return new;
+}
+
+
+/* Emit insns to move operands[1] into operands[0].  */
+
+void
+emit_pic_move (operands, mode)
+     rtx *operands;
+     enum machine_mode mode;
+{
+  rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
+
+  if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1]))
+    operands[1] = (rtx) force_reg (SImode, operands[1]);
+  else
+    operands[1] = legitimize_pic_address (operands[1], temp);
+}
+
+
+/* Try machine-dependent ways of modifying an illegitimate address
+   to be legitimate.  If we find one, return the new, valid address.
+   This macro is used in only one place: `memory_address' in explow.c.
+
+   OLDX is the address as it was before break_out_memory_refs was called.
+   In some cases it is useful to look at this to decide what needs to be done.
+
+   MODE and WIN are passed so that this macro can use
+   GO_IF_LEGITIMATE_ADDRESS.
+
+   It is always safe for this macro to do nothing.  It exists to recognize
+   opportunities to optimize the output.
+
+   For the 80386, we handle X+REG by loading X into a register R and
+   using R+REG.  R will go in a general reg and indexing will be used.
+   However, if REG is a broken-out memory address or multiplication,
+   nothing needs to be done because REG can certainly go in a general reg.
+
+   When -fpic is used, special handling is needed for symbolic references.
+   See comments by legitimize_pic_address in i386.c for details.  */
+
+rtx
+legitimize_address (x, oldx, mode)
+     register rtx x;
+     register rtx oldx;
+     enum machine_mode mode;
+{
+  int changed = 0;
+  unsigned log;
+
+  if (TARGET_DEBUG_ADDR)
+    {
+      fprintf (stderr, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n", GET_MODE_NAME (mode));
+      debug_rtx (x);
+    }
+
+  if (flag_pic && SYMBOLIC_CONST (x))
+    return legitimize_pic_address (x, 0);
+
+  /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
+  if (GET_CODE (x) == ASHIFT
+      && GET_CODE (XEXP (x, 1)) == CONST_INT
+      && (log = (unsigned)exact_log2 (INTVAL (XEXP (x, 1)))) < 4)
+    {
+      changed = 1;
+      x = gen_rtx (MULT, Pmode,
+		   force_reg (Pmode, XEXP (x, 0)),
+		   GEN_INT (1 << log));
+    }
+
+  if (GET_CODE (x) == PLUS)
+    {
+      /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
+      if (GET_CODE (XEXP (x, 0)) == ASHIFT
+	  && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
+	  && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) < 4)
+	{
+	  changed = 1;
+	  XEXP (x, 0) = gen_rtx (MULT, Pmode,
+				 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
+				 GEN_INT (1 << log));
+	}
+
+      if (GET_CODE (XEXP (x, 1)) == ASHIFT
+	  && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
+	  && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1)))) < 4)
+	{
+	  changed = 1;
+	  XEXP (x, 1) = gen_rtx (MULT, Pmode,
+				 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
+				 GEN_INT (1 << log));
+	}
+
+      /* Put multiply first if it isn't already */
+      if (GET_CODE (XEXP (x, 1)) == MULT)
+	{
+	  rtx tmp = XEXP (x, 0);
+	  XEXP (x, 0) = XEXP (x, 1);
+	  XEXP (x, 1) = tmp;
+	  changed = 1;
+	}
+
+      /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
+	 into (plus (plus (mult (reg) (const)) (reg)) (const)).  This can be
+	 created by virtual register instantiation, register elimination, and
+	 similar optimizations.  */
+      if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
+	{
+	  changed = 1;
+	  x = gen_rtx (PLUS, Pmode,
+		       gen_rtx (PLUS, Pmode, XEXP (x, 0), XEXP (XEXP (x, 1), 0)),
+		       XEXP (XEXP (x, 1), 1));
+	}
+
+      /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
+	 into (plus (plus (mult (reg) (const)) (reg)) (const)).  */
+      else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
+	       && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
+	       && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
+	       && CONSTANT_P (XEXP (x, 1)))
+	{
+	  rtx constant, other;
+
+	  if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+	    {
+	      constant = XEXP (x, 1);
+	      other = XEXP (XEXP (XEXP (x, 0), 1), 1);
+	    }
+	  else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
+	    {
+	      constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
+	      other = XEXP (x, 1);
+	    }
+	  else
+	    constant = 0;
+
+	  if (constant)
+	    {
+	      changed = 1;
+	      x = gen_rtx (PLUS, Pmode,
+			   gen_rtx (PLUS, Pmode, XEXP (XEXP (x, 0), 0),
+				    XEXP (XEXP (XEXP (x, 0), 1), 0)),
+			   plus_constant (other, INTVAL (constant)));
+	    }
+	}
+
+      if (changed && legitimate_address_p (mode, x, FALSE))
+	return x;
+
+      if (GET_CODE (XEXP (x, 0)) == MULT)
+	{
+	  changed = 1;
+	  XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
+	}
+
+      if (GET_CODE (XEXP (x, 1)) == MULT)
+	{
+	  changed = 1;
+	  XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
+	}
+
+      if (changed
+	  && GET_CODE (XEXP (x, 1)) == REG
+	  && GET_CODE (XEXP (x, 0)) == REG)
+	return x;
+
+      if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
+	{
+	  changed = 1;
+	  x = legitimize_pic_address (x, 0);
+	}
+
+      if (changed && legitimate_address_p (mode, x, FALSE))
+	return x;
+
+      if (GET_CODE (XEXP (x, 0)) == REG)
+	{
+	  register rtx temp = gen_reg_rtx (Pmode);
+	  register rtx val  = force_operand (XEXP (x, 1), temp);
+	  if (val != temp)
+	    emit_move_insn (temp, val);
+
+	  XEXP (x, 1) = temp;
+	  return x;
+	}
+
+      else if (GET_CODE (XEXP (x, 1)) == REG)
+	{
+	  register rtx temp = gen_reg_rtx (Pmode);
+	  register rtx val  = force_operand (XEXP (x, 0), temp);
+	  if (val != temp)
+	    emit_move_insn (temp, val);
+
+	  XEXP (x, 0) = temp;
+	  return x;
+	}
+    }
+
+  return x;
+}
+
+
+/* Print an integer constant expression in assembler syntax.  Addition
+   and subtraction are the only arithmetic that may appear in these
+   expressions.  FILE is the stdio stream to write to, X is the rtx, and
+   CODE is the operand print code from the output string.  */
+
+static void
+output_pic_addr_const (file, x, code)
+     FILE *file;
+     rtx x;
+     int code;
+{
+  char buf[256];
+
+  switch (GET_CODE (x))
+    {
+    case PC:
+      if (flag_pic)
+	putc ('.', file);
+      else
+	abort ();
+      break;
+
+    case SYMBOL_REF:
+    case LABEL_REF:
+      if (GET_CODE (x) == SYMBOL_REF)
+	assemble_name (file, XSTR (x, 0));
+      else
+	{
+	  ASM_GENERATE_INTERNAL_LABEL (buf, "L",
+				       CODE_LABEL_NUMBER (XEXP (x, 0)));
+	  assemble_name (asm_out_file, buf);
+	}
+
+      if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
+	fprintf (file, "@GOTOFF(%%ebx)");
+      else if (code == 'P')
+	fprintf (file, "@PLT");
+      else if (GET_CODE (x) == LABEL_REF)
+	fprintf (file, "@GOTOFF");
+      else if (! SYMBOL_REF_FLAG (x))
+	fprintf (file, "@GOT");
+      else
+	fprintf (file, "@GOTOFF");
+
+      break;
+
+    case CODE_LABEL:
+      ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
+      assemble_name (asm_out_file, buf);
+      break;
+
+    case CONST_INT:
+      fprintf (file, "%d", INTVAL (x));
+      break;
+
+    case CONST:
+      /* This used to output parentheses around the expression,
+	 but that does not work on the 386 (either ATT or BSD assembler).  */
+      output_pic_addr_const (file, XEXP (x, 0), code);
+      break;
+
+    case CONST_DOUBLE:
+      if (GET_MODE (x) == VOIDmode)
+	{
+	  /* We can use %d if the number is <32 bits and positive.  */
+	  if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
+	    fprintf (file, "0x%x%08x",
+		     CONST_DOUBLE_HIGH (x), CONST_DOUBLE_LOW (x));
+	  else
+	    fprintf (file, "%d", CONST_DOUBLE_LOW (x));
+	}
+      else
+	/* We can't handle floating point constants;
+	   PRINT_OPERAND must handle them.  */
+	output_operand_lossage ("floating constant misused");
+      break;
+
+    case PLUS:
+      /* Some assemblers need integer constants to appear last (eg masm).  */
+      if (GET_CODE (XEXP (x, 0)) == CONST_INT)
+	{
+	  output_pic_addr_const (file, XEXP (x, 1), code);
+	  if (INTVAL (XEXP (x, 0)) >= 0)
+	    fprintf (file, "+");
+	  output_pic_addr_const (file, XEXP (x, 0), code);
+	}
+      else
+	{
+	  output_pic_addr_const (file, XEXP (x, 0), code);
+	  if (INTVAL (XEXP (x, 1)) >= 0)
+	    fprintf (file, "+");
+	  output_pic_addr_const (file, XEXP (x, 1), code);
+	}
+      break;
+
+    case MINUS:
+      output_pic_addr_const (file, XEXP (x, 0), code);
+      fprintf (file, "-");
+      output_pic_addr_const (file, XEXP (x, 1), code);
+      break;
+
+    default:
+      output_operand_lossage ("invalid expression as operand");
+    }
+}
+
+/* Meaning of CODE:
+   f -- float insn (print a CONST_DOUBLE as a float rather than in hex).
+   D,L,W,B,Q,S -- print the opcode suffix for specified size of operand.
+   R -- print the prefix for register names.
+   z -- print the opcode suffix for the size of the current operand.
+   * -- print a star (in certain assembler syntax)
+   w -- print the operand as if it's a "word" (HImode) even if it isn't.
+   c -- don't print special prefixes before constant operands.
+*/
+
+void
+print_operand (file, x, code)
+     FILE *file;
+     rtx x;
+     int code;
+{
+  if (code)
+    {
+      switch (code)
+	{
+	case '*':
+	  if (USE_STAR)
+	    putc ('*', file);
+	  return;
+
+	case 'L':
+	  PUT_OP_SIZE (code, 'l', file);
+	  return;
+
+	case 'W':
+	  PUT_OP_SIZE (code, 'w', file);
+	  return;
+
+	case 'B':
+	  PUT_OP_SIZE (code, 'b', file);
+	  return;
+
+	case 'Q':
+	  PUT_OP_SIZE (code, 'l', file);
+	  return;
+
+	case 'S':
+	  PUT_OP_SIZE (code, 's', file);
+	  return;
+
+	case 'T':
+	  PUT_OP_SIZE (code, 't', file);
+	  return;
+
+	case 'z':
+	  /* 387 opcodes don't get size suffixes if the operands are
+	     registers. */
+
+	  if (STACK_REG_P (x))
+	    return;
+
+	  /* this is the size of op from size of operand */
+	  switch (GET_MODE_SIZE (GET_MODE (x)))
+	    {
+	    case 1:
+	      PUT_OP_SIZE ('B', 'b', file);
+	      return;
+
+	    case 2:
+	      PUT_OP_SIZE ('W', 'w', file);
+	      return;
+
+	    case 4:
+	      if (GET_MODE (x) == SFmode)
+		{
+		  PUT_OP_SIZE ('S', 's', file);
+		  return;
+		}
+	      else
+		PUT_OP_SIZE ('L', 'l', file);
+	      return;
+
+	    case 12:
+		  PUT_OP_SIZE ('T', 't', file);
+		  return;
+
+	    case 8:
+	      if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
+		{
+#ifdef GAS_MNEMONICS
+		  PUT_OP_SIZE ('Q', 'q', file);
+		  return;
+#else
+		  PUT_OP_SIZE ('Q', 'l', file);	/* Fall through */
+#endif
+		}
+
+	      PUT_OP_SIZE ('Q', 'l', file);
+	      return;
+	    }
+
+	case 'b':
+	case 'w':
+	case 'k':
+	case 'h':
+	case 'y':
+	case 'P':
+	  break;
+
+	default:
+	  {
+	    char str[50];
+
+	    sprintf (str, "invalid operand code `%c'", code);
+	    output_operand_lossage (str);
+	  }
+	}
+    }
+  if (GET_CODE (x) == REG)
+    {
+      PRINT_REG (x, code, file);
+    }
+  else if (GET_CODE (x) == MEM)
+    {
+      PRINT_PTR (x, file);
+      if (CONSTANT_ADDRESS_P (XEXP (x, 0)))
+	{
+	  if (flag_pic)
+	    output_pic_addr_const (file, XEXP (x, 0), code);
+	  else
+	    output_addr_const (file, XEXP (x, 0));
+	}
+      else
+	output_address (XEXP (x, 0));
+    }
+  else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
+    {
+      REAL_VALUE_TYPE r; long l;
+      REAL_VALUE_FROM_CONST_DOUBLE (r, x);
+      REAL_VALUE_TO_TARGET_SINGLE (r, l);
+      PRINT_IMMED_PREFIX (file);
+      fprintf (file, "0x%x", l);
+    }
+ /* These float cases don't actually occur as immediate operands. */
+ else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
+    {
+      REAL_VALUE_TYPE r; char dstr[30];
+      REAL_VALUE_FROM_CONST_DOUBLE (r, x);
+      REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
+      fprintf (file, "%s", dstr);
+    }
+  else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == XFmode)
+    {
+      REAL_VALUE_TYPE r; char dstr[30];
+      REAL_VALUE_FROM_CONST_DOUBLE (r, x);
+      REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
+      fprintf (file, "%s", dstr);
+    }
+  else 
+    {
+      if (code != 'P')
+	{
+	  if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
+	    PRINT_IMMED_PREFIX (file);
+	  else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
+		   || GET_CODE (x) == LABEL_REF)
+	    PRINT_OFFSET_PREFIX (file);
+	}
+      if (flag_pic)
+	output_pic_addr_const (file, x, code);
+      else
+	output_addr_const (file, x);
+    }
+}
+
+/* Print a memory operand whose address is ADDR.  */
+
+void
+print_operand_address (file, addr)
+     FILE *file;
+     register rtx addr;
+{
+  register rtx reg1, reg2, breg, ireg;
+  rtx offset;
+
+  switch (GET_CODE (addr))
+    {
+    case REG:
+      ADDR_BEG (file);
+      fprintf (file, "%se", RP);
+      fputs (hi_reg_name[REGNO (addr)], file);
+      ADDR_END (file);
+      break;
+
+    case PLUS:
+      reg1 = 0;
+      reg2 = 0;
+      ireg = 0;
+      breg = 0;
+      offset = 0;
+      if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))
+	{
+	  offset = XEXP (addr, 0);
+	  addr = XEXP (addr, 1);
+	}
+      else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))
+	{
+	  offset = XEXP (addr, 1);
+	  addr = XEXP (addr, 0);
+	}
+      if (GET_CODE (addr) != PLUS) ;
+      else if (GET_CODE (XEXP (addr, 0)) == MULT)
+	{
+	  reg1 = XEXP (addr, 0);
+	  addr = XEXP (addr, 1);
+	}
+      else if (GET_CODE (XEXP (addr, 1)) == MULT)
+	{
+	  reg1 = XEXP (addr, 1);
+	  addr = XEXP (addr, 0);
+	}
+      else if (GET_CODE (XEXP (addr, 0)) == REG)
+	{
+	  reg1 = XEXP (addr, 0);
+	  addr = XEXP (addr, 1);
+	}
+      else if (GET_CODE (XEXP (addr, 1)) == REG)
+	{
+	  reg1 = XEXP (addr, 1);
+	  addr = XEXP (addr, 0);
+	}
+      if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT)
+	{
+	  if (reg1 == 0) reg1 = addr;
+	  else reg2 = addr;
+	  addr = 0;
+	}
+      if (offset != 0)
+	{
+	  if (addr != 0) abort ();
+	  addr = offset;
+	}
+      if ((reg1 && GET_CODE (reg1) == MULT)
+	  || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))
+	{
+	  breg = reg2;
+	  ireg = reg1;
+	}
+      else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))
+	{
+	  breg = reg1;
+	  ireg = reg2;
+	}
+
+      if (ireg != 0 || breg != 0)
+	{
+	  int scale = 1;
+
+	  if (addr != 0)
+	    {
+	      if (flag_pic)
+		output_pic_addr_const (file, addr, 0);
+
+	      else if (GET_CODE (addr) == LABEL_REF)
+		output_asm_label (addr);
+
+	      else
+		output_addr_const (file, addr);
+	    }
+
+  	  if (ireg != 0 && GET_CODE (ireg) == MULT)
+	    {
+	      scale = INTVAL (XEXP (ireg, 1));
+	      ireg = XEXP (ireg, 0);
+	    }
+
+	  /* The stack pointer can only appear as a base register,
+	     never an index register, so exchange the regs if it is wrong. */
+
+	  if (scale == 1 && ireg && REGNO (ireg) == STACK_POINTER_REGNUM)
+	    {
+	      rtx tmp;
+
+	      tmp = breg;
+	      breg = ireg;
+	      ireg = tmp;
+	    }
+
+	  /* output breg+ireg*scale */
+	  PRINT_B_I_S (breg, ireg, scale, file);
+	  break;
+	}
+
+    case MULT:
+      {
+	int scale;
+	if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
+	  {
+	    scale = INTVAL (XEXP (addr, 0));
+	    ireg = XEXP (addr, 1);
+	  }
+	else
+	  {
+	    scale = INTVAL (XEXP (addr, 1));
+	    ireg = XEXP (addr, 0);
+	  }
+	output_addr_const (file, const0_rtx);
+	PRINT_B_I_S ((rtx) 0, ireg, scale, file);
+      }
+      break;
+
+    default:
+      if (GET_CODE (addr) == CONST_INT
+	  && INTVAL (addr) < 0x8000
+	  && INTVAL (addr) >= -0x8000)
+	fprintf (file, "%d", INTVAL (addr));
+      else
+	{
+	  if (flag_pic)
+	    output_pic_addr_const (file, addr, 0);
+	  else
+	    output_addr_const (file, addr);
+	}
+    }
+}
+
+/* Set the cc_status for the results of an insn whose pattern is EXP.
+   On the 80386, we assume that only test and compare insns, as well
+   as SI, HI, & DI mode ADD, SUB, NEG, AND, IOR, XOR, ASHIFT,
+   ASHIFTRT, and LSHIFTRT instructions set the condition codes usefully.
+   Also, we assume that jumps, moves and sCOND don't affect the condition
+   codes.  All else clobbers the condition codes, by assumption.
+
+   We assume that ALL integer add, minus, etc. instructions effect the
+   condition codes.  This MUST be consistent with i386.md.
+
+   We don't record any float test or compare - the redundant test &
+   compare check in final.c does not handle stack-like regs correctly. */
+
+void
+notice_update_cc (exp)
+     rtx exp;
+{
+  if (GET_CODE (exp) == SET)
+    {
+      /* Jumps do not alter the cc's.  */
+      if (SET_DEST (exp) == pc_rtx)
+	return;
+#ifdef IS_STACK_MODE
+      /* intel1 
+         Moving into a memory of stack_mode may have been moved
+         in between the use and set of cc0 by loop_spl(). So
+         old value of cc.status must be retained */
+      if(GET_CODE(SET_DEST(exp))==MEM 
+         && IS_STACK_MODE(GET_MODE(SET_DEST(exp))))
+        {
+          return;
+        }
+#endif
+      /* Moving register or memory into a register:
+	 it doesn't alter the cc's, but it might invalidate
+	 the RTX's which we remember the cc's came from.
+	 (Note that moving a constant 0 or 1 MAY set the cc's).  */
+      if (REG_P (SET_DEST (exp))
+	  && (REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == MEM
+	      || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'))
+	{
+	  if (cc_status.value1
+	      && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1))
+	    cc_status.value1 = 0;
+	  if (cc_status.value2
+	      && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2))
+	    cc_status.value2 = 0;
+	  return;
+	}
+      /* Moving register into memory doesn't alter the cc's.
+	 It may invalidate the RTX's which we remember the cc's came from.  */
+      if (GET_CODE (SET_DEST (exp)) == MEM
+	  && (REG_P (SET_SRC (exp))
+	      || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'))
+	{
+	  if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM)
+	    cc_status.value1 = 0;
+	  if (cc_status.value2 && GET_CODE (cc_status.value2) == MEM)
+	    cc_status.value2 = 0;
+	  return;
+	}
+      /* Function calls clobber the cc's.  */
+      else if (GET_CODE (SET_SRC (exp)) == CALL)
+	{
+	  CC_STATUS_INIT;
+	  return;
+	}
+      /* Tests and compares set the cc's in predictable ways.  */
+      else if (SET_DEST (exp) == cc0_rtx)
+	{
+	  CC_STATUS_INIT;
+	  cc_status.value1 = SET_SRC (exp);
+	  return;
+	}
+      /* Certain instructions effect the condition codes. */
+      else if (GET_MODE (SET_SRC (exp)) == SImode
+	       || GET_MODE (SET_SRC (exp)) == HImode
+	       || GET_MODE (SET_SRC (exp)) == QImode)
+	switch (GET_CODE (SET_SRC (exp)))
+	  {
+	  case ASHIFTRT: case LSHIFTRT:
+	  case ASHIFT:
+	    /* Shifts on the 386 don't set the condition codes if the
+	       shift count is zero. */
+	    if (GET_CODE (XEXP (SET_SRC (exp), 1)) != CONST_INT)
+	      {
+		CC_STATUS_INIT;
+		break;
+	      }
+	    /* We assume that the CONST_INT is non-zero (this rtx would
+	       have been deleted if it were zero. */
+
+	  case PLUS: case MINUS: case NEG:
+	  case AND: case IOR: case XOR:
+	    cc_status.flags = CC_NO_OVERFLOW;
+	    cc_status.value1 = SET_SRC (exp);
+	    cc_status.value2 = SET_DEST (exp);
+	    break;
+
+	  default:
+	    CC_STATUS_INIT;
+	  }
+      else
+	{
+	  CC_STATUS_INIT;
+	}
+    }
+  else if (GET_CODE (exp) == PARALLEL
+	   && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
+    {
+      if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx)
+	return;
+      if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx)
+	{
+	  CC_STATUS_INIT;
+	  if (stack_regs_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0))))
+	    cc_status.flags |= CC_IN_80387;
+	  else
+	    cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0));
+	  return;
+	}
+      CC_STATUS_INIT;
+    }
+  else
+    {
+      CC_STATUS_INIT;
+    }
+}
+
+/* Split one or more DImode RTL references into pairs of SImode
+   references.  The RTL can be REG, offsettable MEM, integer constant, or
+   CONST_DOUBLE.  "operands" is a pointer to an array of DImode RTL to
+   split and "num" is its length.  lo_half and hi_half are output arrays
+   that parallel "operands". */
+
+void
+split_di (operands, num, lo_half, hi_half)
+     rtx operands[];
+     int num;
+     rtx lo_half[], hi_half[];
+{
+  while (num--)
+    {
+      if (GET_CODE (operands[num]) == REG)
+	{
+	  lo_half[num] = gen_rtx (REG, SImode, REGNO (operands[num]));
+	  hi_half[num] = gen_rtx (REG, SImode, REGNO (operands[num]) + 1);
+	}
+      else if (CONSTANT_P (operands[num]))
+	{
+	  split_double (operands[num], &lo_half[num], &hi_half[num]);
+	}
+      else if (offsettable_memref_p (operands[num]))
+	{
+	  lo_half[num] = operands[num];
+	  hi_half[num] = adj_offsettable_operand (operands[num], 4);
+	}
+      else
+	abort();
+    }
+}
+
+/* Return 1 if this is a valid binary operation on a 387.
+   OP is the expression matched, and MODE is its mode. */
+
+int
+binary_387_op (op, mode)
+    register rtx op;
+    enum machine_mode mode;
+{
+  if (mode != VOIDmode && mode != GET_MODE (op))
+    return 0;
+
+  switch (GET_CODE (op))
+    {
+    case PLUS:
+    case MINUS:
+    case MULT:
+    case DIV:
+      return GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT;
+
+    default:
+      return 0;
+    }
+}
+
+
+/* Return 1 if this is a valid shift or rotate operation on a 386.
+   OP is the expression matched, and MODE is its mode. */
+
+int
+shift_op (op, mode)
+    register rtx op;
+    enum machine_mode mode;
+{
+  rtx operand = XEXP (op, 0);
+
+  if (mode != VOIDmode && mode != GET_MODE (op))
+    return 0;
+
+  if (GET_MODE (operand) != GET_MODE (op)
+      || GET_MODE_CLASS (GET_MODE (op)) != MODE_INT)
+    return 0;
+
+  return (GET_CODE (op) == ASHIFT
+	  || GET_CODE (op) == ASHIFTRT
+	  || GET_CODE (op) == LSHIFTRT
+	  || GET_CODE (op) == ROTATE
+	  || GET_CODE (op) == ROTATERT);
+}
+
+/* Return 1 if OP is COMPARE rtx with mode VOIDmode.
+   MODE is not used.  */
+
+int
+VOIDmode_compare_op (op, mode)
+    register rtx op;
+    enum machine_mode mode;
+{
+  return GET_CODE (op) == COMPARE && GET_MODE (op) == VOIDmode;
+}
+
+/* Output code to perform a 387 binary operation in INSN, one of PLUS,
+   MINUS, MULT or DIV.  OPERANDS are the insn operands, where operands[3]
+   is the expression of the binary operation.  The output may either be
+   emitted here, or returned to the caller, like all output_* functions.
+
+   There is no guarantee that the operands are the same mode, as they
+   might be within FLOAT or FLOAT_EXTEND expressions. */
+
+char *
+output_387_binary_op (insn, operands)
+     rtx insn;
+     rtx *operands;
+{
+  rtx temp;
+  char *base_op;
+  static char buf[100];
+
+  switch (GET_CODE (operands[3]))
+    {
+    case PLUS:
+      if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
+	  || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
+	base_op = "fiadd";
+      else
+	base_op = "fadd";
+      break;
+
+    case MINUS:
+      if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
+	  || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
+	base_op = "fisub";
+      else
+	base_op = "fsub";
+      break;
+
+    case MULT:
+      if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
+	  || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
+	base_op = "fimul";
+      else
+	base_op = "fmul";
+      break;
+
+    case DIV:
+      if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
+	  || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
+	base_op = "fidiv";
+      else
+	base_op = "fdiv";
+      break;
+
+    default:
+      abort ();
+    }
+
+  strcpy (buf, base_op);
+
+  switch (GET_CODE (operands[3]))
+    {
+    case MULT:
+    case PLUS:
+      if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
+	{
+	  temp = operands[2];
+	  operands[2] = operands[1];
+	  operands[1] = temp;
+	}
+
+      if (GET_CODE (operands[2]) == MEM)
+	return strcat (buf, AS1 (%z2,%2));
+
+      if (NON_STACK_REG_P (operands[1]))
+	{
+	  output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1)));
+	  RET;
+	}
+      else if (NON_STACK_REG_P (operands[2]))
+	{
+	  output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1)));
+	  RET;
+	}
+
+      if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
+	return strcat (buf, AS2 (p,%2,%0));
+
+      if (STACK_TOP_P (operands[0]))
+	return strcat (buf, AS2C (%y2,%0));
+      else
+	return strcat (buf, AS2C (%2,%0));
+
+    case MINUS:
+    case DIV:
+      if (GET_CODE (operands[1]) == MEM)
+	return strcat (buf, AS1 (r%z1,%1));
+
+      if (GET_CODE (operands[2]) == MEM)
+	return strcat (buf, AS1 (%z2,%2));
+
+      if (NON_STACK_REG_P (operands[1]))
+	{
+	  output_op_from_reg (operands[1], strcat (buf, AS1 (r%z0,%1)));
+	  RET;
+	}
+      else if (NON_STACK_REG_P (operands[2]))
+	{
+	  output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1)));
+	  RET;
+	}
+
+      if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2]))
+	abort ();
+
+      if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
+	return strcat (buf, AS2 (rp,%2,%0));
+
+      if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
+	return strcat (buf, AS2 (p,%1,%0));
+
+      if (STACK_TOP_P (operands[0]))
+	{
+	  if (STACK_TOP_P (operands[1]))
+	    return strcat (buf, AS2C (%y2,%0));
+	  else
+	    return strcat (buf, AS2 (r,%y1,%0));
+	}
+      else if (STACK_TOP_P (operands[1]))
+	return strcat (buf, AS2C (%1,%0));
+      else
+	return strcat (buf, AS2 (r,%2,%0));
+
+    default:
+      abort ();
+    }
+}
+
+/* Output code for INSN to convert a float to a signed int.  OPERANDS
+   are the insn operands.  The output may be SFmode or DFmode and the
+   input operand may be SImode or DImode.  As a special case, make sure
+   that the 387 stack top dies if the output mode is DImode, because the
+   hardware requires this.  */
+
+char *
+output_fix_trunc (insn, operands)
+     rtx insn;
+     rtx *operands;
+{
+  int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
+  rtx xops[2];
+
+  if (! STACK_TOP_P (operands[1]) ||
+      (GET_MODE (operands[0]) == DImode && ! stack_top_dies))
+    abort ();
+
+  xops[0] = GEN_INT (12);
+  xops[1] = operands[4];
+
+  output_asm_insn (AS1 (fnstc%W2,%2), operands);
+  output_asm_insn (AS2 (mov%L2,%2,%4), operands);
+  output_asm_insn (AS2 (mov%B1,%0,%h1), xops);
+  output_asm_insn (AS2 (mov%L4,%4,%3), operands);
+  output_asm_insn (AS1 (fldc%W3,%3), operands);
+
+  if (NON_STACK_REG_P (operands[0]))
+    output_to_reg (operands[0], stack_top_dies);
+  else if (GET_CODE (operands[0]) == MEM)
+    {
+      if (stack_top_dies)
+	output_asm_insn (AS1 (fistp%z0,%0), operands);
+      else
+	output_asm_insn (AS1 (fist%z0,%0), operands);
+    }
+  else
+    abort ();
+
+  return AS1 (fldc%W2,%2);
+}
+
+/* Output code for INSN to compare OPERANDS.  The two operands might
+   not have the same mode: one might be within a FLOAT or FLOAT_EXTEND
+   expression.  If the compare is in mode CCFPEQmode, use an opcode that
+   will not fault if a qNaN is present. */
+
+char *
+output_float_compare (insn, operands)
+     rtx insn;
+     rtx *operands;
+{
+  int stack_top_dies;
+  rtx body = XVECEXP (PATTERN (insn), 0, 0);
+  int unordered_compare = GET_MODE (SET_SRC (body)) == CCFPEQmode;
+
+  /* intel1 */
+  rtx tmp;
+  if (! STACK_TOP_P (operands[0]))
+    {
+      tmp = operands[0];
+      operands[0] = operands[1];
+      operands[1] = tmp;
+      cc_status.flags |= CC_REVERSED;
+    }
+    
+  if (! STACK_TOP_P (operands[0]))
+    abort ();
+
+  stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
+
+  if (STACK_REG_P (operands[1])
+      && stack_top_dies
+      && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
+      && REGNO (operands[1]) != FIRST_STACK_REG)
+    {
+      /* If both the top of the 387 stack dies, and the other operand
+	 is also a stack register that dies, then this must be a
+	 `fcompp' float compare */
+
+      if (unordered_compare)
+	output_asm_insn ("fucompp", operands);
+      else
+	output_asm_insn ("fcompp", operands);
+    }
+  else
+    {
+      static char buf[100];
+
+      /* Decide if this is the integer or float compare opcode, or the
+	 unordered float compare. */
+
+      if (unordered_compare)
+	strcpy (buf, "fucom");
+      else if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_FLOAT)
+	strcpy (buf, "fcom");
+      else
+	strcpy (buf, "ficom");
+
+      /* Modify the opcode if the 387 stack is to be popped. */
+
+      if (stack_top_dies)
+	strcat (buf, "p");
+
+      if (NON_STACK_REG_P (operands[1]))
+	output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1)));
+      else
+        output_asm_insn (strcat (buf, AS1 (%z1,%y1)), operands);
+    }
+
+  /* Now retrieve the condition code. */
+
+  return output_fp_cc0_set (insn);
+}
+
+/* Output opcodes to transfer the results of FP compare or test INSN
+   from the FPU to the CPU flags.  If TARGET_IEEE_FP, ensure that if the
+   result of the compare or test is unordered, no comparison operator
+   succeeds except NE.  Return an output template, if any.  */
+
+char *
+output_fp_cc0_set (insn)
+     rtx insn;
+{
+  rtx xops[3];
+  rtx unordered_label;
+  rtx next;
+  enum rtx_code code;
+
+  xops[0] = gen_rtx (REG, HImode, 0);
+  output_asm_insn (AS1 (fnsts%W0,%0), xops);
+
+
+  if (! TARGET_IEEE_FP)
+    {
+      /* intel1 */
+      if (!(cc_status.flags & CC_REVERSED))
+        {
+          next = next_cc0_user (insn);
+        
+          if (GET_CODE (next) == JUMP_INSN
+              && GET_CODE (PATTERN (next)) == SET
+              && SET_DEST (PATTERN (next)) == pc_rtx
+              && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
+            {
+              code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
+            }
+          else if (GET_CODE (PATTERN (next)) == SET)
+            {
+              code = GET_CODE (SET_SRC (PATTERN (next)));
+            }
+          else
+            {
+              return "sahf";
+            }
+          if (code == GT || code == LT || code == EQ || code == NE
+              || code == LE || code == GE)
+            { /* We will test eax directly */
+              cc_status.flags |= CC_TEST_AX;
+              RET;
+            }
+        }
+      return "sahf";
+    }
+
+  next = next_cc0_user (insn);
+  if (next == NULL_RTX)
+    abort ();
+
+  if (GET_CODE (next) == JUMP_INSN
+      && GET_CODE (PATTERN (next)) == SET
+      && SET_DEST (PATTERN (next)) == pc_rtx
+      && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
+    {
+      code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
+    }
+  else if (GET_CODE (PATTERN (next)) == SET)
+    {
+      code = GET_CODE (SET_SRC (PATTERN (next)));
+    }
+  else
+    abort ();
+
+  xops[0] = gen_rtx (REG, QImode, 0);
+
+  switch (code)
+    {
+    case GT:
+      xops[1] = GEN_INT (0x45);
+      output_asm_insn (AS2 (and%B0,%1,%h0), xops);
+      /* je label */
+      break;
+
+    case LT:
+      xops[1] = GEN_INT (0x45);
+      xops[2] = GEN_INT (0x01);
+      output_asm_insn (AS2 (and%B0,%1,%h0), xops);
+      output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
+      /* je label */
+      break;
+
+    case GE:
+      xops[1] = GEN_INT (0x05);
+      output_asm_insn (AS2 (and%B0,%1,%h0), xops);
+      /* je label */
+      break;
+
+    case LE:
+      xops[1] = GEN_INT (0x45);
+      xops[2] = GEN_INT (0x40);
+      output_asm_insn (AS2 (and%B0,%1,%h0), xops);
+      output_asm_insn (AS1 (dec%B0,%h0), xops);
+      output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
+      /* jb label */
+      break;
+
+    case EQ:
+      xops[1] = GEN_INT (0x45);
+      xops[2] = GEN_INT (0x40);
+      output_asm_insn (AS2 (and%B0,%1,%h0), xops);
+      output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
+      /* je label */
+      break;
+
+    case NE:
+      xops[1] = GEN_INT (0x44);
+      xops[2] = GEN_INT (0x40);
+      output_asm_insn (AS2 (and%B0,%1,%h0), xops);
+      output_asm_insn (AS2 (xor%B0,%2,%h0), xops);
+      /* jne label */
+      break;
+
+    case GTU:
+    case LTU:
+    case GEU:
+    case LEU:
+    default:
+      abort ();
+    }
+  RET;
+}
+
+#define MAX_386_STACK_LOCALS 2
+
+static rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS];
+
+/* Define the structure for the machine field in struct function.  */
+struct machine_function
+{
+  rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS];
+};
+
+/* Functions to save and restore i386_stack_locals.
+   These will be called, via pointer variables,
+   from push_function_context and pop_function_context.  */
+
+void
+save_386_machine_status (p)
+     struct function *p;
+{
+  p->machine = (struct machine_function *) xmalloc (sizeof i386_stack_locals);
+  bcopy ((char *) i386_stack_locals, (char *) p->machine->i386_stack_locals,
+	 sizeof i386_stack_locals);
+}
+
+void
+restore_386_machine_status (p)
+     struct function *p;
+{
+  bcopy ((char *) p->machine->i386_stack_locals, (char *) i386_stack_locals,
+	 sizeof i386_stack_locals);
+  free (p->machine);
+}
+
+/* Clear stack slot assignments remembered from previous functions.
+   This is called from INIT_EXPANDERS once before RTL is emitted for each
+   function.  */
+
+void
+clear_386_stack_locals ()
+{
+  enum machine_mode mode;
+  int n;
+
+  for (mode = VOIDmode; (int) mode < (int) MAX_MACHINE_MODE;
+       mode = (enum machine_mode) ((int) mode + 1))
+    for (n = 0; n < MAX_386_STACK_LOCALS; n++)
+      i386_stack_locals[(int) mode][n] = NULL_RTX;
+
+  /* Arrange to save and restore i386_stack_locals around nested functions.  */
+  save_machine_status = save_386_machine_status;
+  restore_machine_status = restore_386_machine_status;
+}
+
+/* Return a MEM corresponding to a stack slot with mode MODE.
+   Allocate a new slot if necessary.
+
+   The RTL for a function can have several slots available: N is
+   which slot to use.  */
+
+rtx
+assign_386_stack_local (mode, n)
+     enum machine_mode mode;
+     int n;
+{
+  if (n < 0 || n >= MAX_386_STACK_LOCALS)
+    abort ();
+
+  if (i386_stack_locals[(int) mode][n] == NULL_RTX)
+  {
+    i386_stack_locals[(int) mode][n]
+      = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
+  }
+  return i386_stack_locals[(int) mode][n];
+}
+
+
+/* all functions after here added by intel1 */
+/* intel1 */
+int is_mul(op,mode)
+    register rtx op;
+    enum machine_mode mode;
+{
+  return(GET_CODE(op)==MULT);
+}
+
+/* intel1 */
+int is_div(op,mode)
+    register rtx op;
+    enum machine_mode mode;
+{
+  return(GET_CODE(op)==DIV);
+}
+
+/* Create a new copy of an rtx.
+   Recursively copies the operands of the rtx,
+   except for those few rtx codes that are sharable.
+   Doesn't share CONST  */
+
+rtx
+copy_all_rtx (orig)
+     register rtx orig;
+{
+  register rtx copy;
+  register int i, j;
+  register RTX_CODE code;
+  register char *format_ptr;
+
+  code = GET_CODE (orig);
+
+  switch (code)
+    {
+    case REG:
+    case QUEUED:
+    case CONST_INT:
+    case CONST_DOUBLE:
+    case SYMBOL_REF:
+    case CODE_LABEL:
+    case PC:
+    case CC0:
+    case SCRATCH:
+      /* SCRATCH must be shared because they represent distinct values. */
+      return orig;
+
+#if 0
+    case CONST:
+      /* CONST can be shared if it contains a SYMBOL_REF.  If it contains
+	 a LABEL_REF, it isn't sharable.  */
+      if (GET_CODE (XEXP (orig, 0)) == PLUS
+	  && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF
+	  && GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT)
+	return orig;
+      break;
+#endif
+      /* A MEM with a constant address is not sharable.  The problem is that
+	 the constant address may need to be reloaded.  If the mem is shared,
+	 then reloading one copy of this mem will cause all copies to appear
+	 to have been reloaded.  */
+    }
+
+  copy = rtx_alloc (code);
+  PUT_MODE (copy, GET_MODE (orig));
+  copy->in_struct = orig->in_struct;
+  copy->volatil = orig->volatil;
+  copy->unchanging = orig->unchanging;
+  copy->integrated = orig->integrated;
+  /* intel1 */
+  copy->is_spill_rtx = orig->is_spill_rtx;
+  
+  format_ptr = GET_RTX_FORMAT (GET_CODE (copy));
+
+  for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++)
+    {
+      switch (*format_ptr++)
+	{
+	case 'e':
+	  XEXP (copy, i) = XEXP (orig, i);
+	  if (XEXP (orig, i) != NULL)
+	    XEXP (copy, i) = copy_rtx (XEXP (orig, i));
+	  break;
+
+	case '0':
+	case 'u':
+	  XEXP (copy, i) = XEXP (orig, i);
+	  break;
+
+	case 'E':
+	case 'V':
+	  XVEC (copy, i) = XVEC (orig, i);
+	  if (XVEC (orig, i) != NULL)
+	    {
+	      XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i));
+	      for (j = 0; j < XVECLEN (copy, i); j++)
+		XVECEXP (copy, i, j) = copy_rtx (XVECEXP (orig, i, j));
+	    }
+	  break;
+
+	case 'w':
+	  XWINT (copy, i) = XWINT (orig, i);
+	  break;
+
+	case 'i':
+	  XINT (copy, i) = XINT (orig, i);
+	  break;
+
+	case 's':
+	case 'S':
+	  XSTR (copy, i) = XSTR (orig, i);
+	  break;
+
+	default:
+	  abort ();
+	}
+    }
+  return copy;
+}
+
+
+/* try to rewrite a memory address to make it valid */
+void 
+rewrite_address (mem_rtx)
+     rtx mem_rtx;
+{
+  rtx index_rtx, base_rtx, offset_rtx, scale_rtx, ret_rtx;
+  int scale = 1;
+  int offset_adjust = 0;
+  int was_only_offset = 0;
+  rtx mem_addr = XEXP (mem_rtx, 0);
+  char *storage = (char *) oballoc (0);
+  int in_struct = 0;
+  int is_spill_rtx = 0;
+
+  in_struct = MEM_IN_STRUCT_P (mem_rtx);
+  is_spill_rtx = RTX_IS_SPILL_P (mem_rtx);
+
+  if (GET_CODE (mem_addr) == PLUS &&
+      GET_CODE (XEXP (mem_addr, 1)) == PLUS &&
+      GET_CODE (XEXP (XEXP (mem_addr, 1), 0)) == REG)
+    {				/* this part is utilized by the combiner */
+      ret_rtx =
+	gen_rtx (PLUS, GET_MODE (mem_addr),
+		 gen_rtx (PLUS, GET_MODE (XEXP (mem_addr, 1)),
+			  XEXP (mem_addr, 0),
+			  XEXP (XEXP (mem_addr, 1), 0)),
+		 XEXP (XEXP (mem_addr, 1), 1));
+      if (memory_address_p (GET_MODE (mem_rtx), ret_rtx))
+	{
+	  XEXP (mem_rtx, 0) = ret_rtx;
+	  RTX_IS_SPILL_P (ret_rtx) = is_spill_rtx;
+	  return;
+	}
+      obfree (storage);
+    }
+
+  /* this part is utilized by loop.c */
+  /* If the address contains PLUS (reg,const) and this pattern is invalid
+     in this case - try to rewrite the address to make it valid  intel1
+  */
+  storage = (char *) oballoc (0);
+  index_rtx = base_rtx = offset_rtx = NULL;
+  /* find the base index and offset elements of the memory address */
+  if (GET_CODE (mem_addr) == PLUS)
+    {
+      if (GET_CODE (XEXP (mem_addr, 0)) == REG)
+	{
+	  if (GET_CODE (XEXP (mem_addr, 1)) == REG)
+	    {
+	      base_rtx = XEXP (mem_addr, 1);
+	      index_rtx = XEXP (mem_addr, 0);
+	    }
+	  else
+	    {
+	      base_rtx = XEXP (mem_addr, 0);
+	      offset_rtx = XEXP (mem_addr, 1);
+	    }
+	}
+      else if (GET_CODE (XEXP (mem_addr, 0)) == MULT)
+	{
+	  index_rtx = XEXP (mem_addr, 0);
+	  if (GET_CODE (XEXP (mem_addr, 1)) == REG)
+	    {
+	      base_rtx = XEXP (mem_addr, 1);
+	    }
+	  else
+	    {
+	      offset_rtx = XEXP (mem_addr, 1);
+	    }
+	}
+      else if (GET_CODE (XEXP (mem_addr, 0)) == PLUS)
+	{
+	  /* intel1 */
+	  if (GET_CODE (XEXP (XEXP (mem_addr, 0), 0)) == PLUS &&
+	      GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0)) == MULT &&
+	      GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 0)) == REG &&
+	      GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 1)) == CONST_INT &&
+	      GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1)) == CONST_INT &&
+	      GET_CODE (XEXP (XEXP (mem_addr, 0), 1)) == REG &&
+	      GET_CODE (XEXP (mem_addr, 1)) == SYMBOL_REF)
+	    {
+	      index_rtx = XEXP (XEXP (XEXP (mem_addr, 0), 0), 0);
+	      offset_rtx = XEXP (mem_addr, 1);
+	      base_rtx = XEXP (XEXP (mem_addr, 0), 1);
+	      offset_adjust = INTVAL (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1));
+	    }
+	  else
+	    {
+	      offset_rtx = XEXP (mem_addr, 1);
+	      index_rtx = XEXP (XEXP (mem_addr, 0), 0);
+	      base_rtx = XEXP (XEXP (mem_addr, 0), 1);
+	    }
+	}
+      else if (GET_CODE (XEXP (mem_addr, 0)) == CONST_INT)
+	{
+	  was_only_offset = 1;
+	  index_rtx = NULL;
+	  base_rtx = NULL;
+	  offset_rtx = XEXP (mem_addr, 1);
+	  offset_adjust = INTVAL (XEXP (mem_addr, 0));
+	  if (offset_adjust == 0)
+	    {
+	      XEXP (mem_rtx, 0) = offset_rtx;
+	      RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
+	      return;
+	    }
+	}
+      else
+	{
+	  obfree (storage);
+	  return;
+	}
+    }
+  else if (GET_CODE (mem_addr) == MULT)
+    {
+      index_rtx = mem_addr;
+    }
+  else
+    {
+      obfree (storage);
+      return;
+    }
+  if (index_rtx && GET_CODE (index_rtx) == MULT)
+    {
+      if (GET_CODE (XEXP (index_rtx, 1)) != CONST_INT)
+	{
+	  obfree (storage);
+	  return;
+	}
+      scale_rtx = XEXP (index_rtx, 1);
+      scale = INTVAL (scale_rtx);
+      index_rtx = copy_all_rtx (XEXP (index_rtx, 0));
+    }
+  /* now find which of the elements are invalid and try to fix them */
+  if (index_rtx && GET_CODE (index_rtx) == CONST_INT && base_rtx == NULL)
+    {
+      offset_adjust = INTVAL (index_rtx) * scale;
+      if (offset_rtx && GET_CODE (offset_rtx) == CONST &&
+	  GET_CODE (XEXP (offset_rtx, 0)) == PLUS)
+	{
+	  if (GET_CODE (XEXP (XEXP (offset_rtx, 0), 0)) == SYMBOL_REF &&
+	      GET_CODE (XEXP (XEXP (offset_rtx, 0), 1)) == CONST_INT)
+	    {
+	      offset_rtx = copy_all_rtx (offset_rtx);
+	      XEXP (XEXP (offset_rtx, 0), 1) =
+		gen_rtx (CONST_INT, 0, INTVAL (XEXP (XEXP (offset_rtx, 0), 1)) + offset_adjust);
+	      if (!CONSTANT_P (offset_rtx))
+		{
+		  obfree (storage);
+		  return;
+		}
+	    }
+	}
+      else if (offset_rtx && GET_CODE (offset_rtx) == SYMBOL_REF)
+	{
+	  offset_rtx =
+	    gen_rtx (CONST, GET_MODE (offset_rtx),
+		     gen_rtx (PLUS, GET_MODE (offset_rtx),
+			      offset_rtx,
+			      gen_rtx (CONST_INT, 0, offset_adjust)));
+	  if (!CONSTANT_P (offset_rtx))
+	    {
+	      obfree (storage);
+	      return;
+	    }
+	}
+      else if (offset_rtx && GET_CODE (offset_rtx) == CONST_INT)
+	{
+	  offset_rtx = gen_rtx (CONST_INT, 0, INTVAL (offset_rtx) + offset_adjust);
+	}
+      else if (!offset_rtx)
+	{
+	  offset_rtx = gen_rtx (CONST_INT, 0, 0);
+	}
+      RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
+      XEXP (mem_rtx, 0) = offset_rtx;
+      return;
+    }
+  if (base_rtx && GET_CODE (base_rtx) == PLUS &&
+      GET_CODE (XEXP (base_rtx, 0)) == REG &&
+      GET_CODE (XEXP (base_rtx, 1)) == CONST_INT)
+    {
+      offset_adjust += INTVAL (XEXP (base_rtx, 1));
+      base_rtx = copy_all_rtx (XEXP (base_rtx, 0));
+    }
+  else if (base_rtx && GET_CODE (base_rtx) == CONST_INT)
+    {
+      offset_adjust += INTVAL (base_rtx);
+      base_rtx = NULL;
+    }
+  if (index_rtx && GET_CODE (index_rtx) == PLUS &&
+      GET_CODE (XEXP (index_rtx, 0)) == REG &&
+      GET_CODE (XEXP (index_rtx, 1)) == CONST_INT)
+    {
+      offset_adjust += INTVAL (XEXP (index_rtx, 1)) * scale;
+      index_rtx = copy_all_rtx (XEXP (index_rtx, 0));
+    }
+  if (index_rtx)
+    {
+      if (!LEGITIMATE_INDEX_P (index_rtx)
+      && !(index_rtx == stack_pointer_rtx && scale == 1 && base_rtx == NULL))
+	{
+	  obfree (storage);
+	  return;
+	}
+    }
+  if (base_rtx)
+    {
+      if (!LEGITIMATE_INDEX_P (base_rtx) && GET_CODE (base_rtx) != REG)
+	{
+	  obfree (storage);
+	  return;
+	}
+    }
+  if (offset_adjust != 0)
+    {
+      if (offset_rtx)
+	{
+	  if (GET_CODE (offset_rtx) == CONST &&
+	      GET_CODE (XEXP (offset_rtx, 0)) == PLUS)
+	    {
+	      if (GET_CODE (XEXP (XEXP (offset_rtx, 0), 0)) == SYMBOL_REF &&
+		  GET_CODE (XEXP (XEXP (offset_rtx, 0), 1)) == CONST_INT)
+		{
+		  offset_rtx = copy_all_rtx (offset_rtx);
+		  XEXP (XEXP (offset_rtx, 0), 1) =
+		    gen_rtx (CONST_INT, 0, INTVAL (XEXP (XEXP (offset_rtx, 0), 1)) + offset_adjust);
+		  if (!CONSTANT_P (offset_rtx))
+		    {
+		      obfree (storage);
+		      return;
+		    }
+		}
+	    }
+	  else if (GET_CODE (offset_rtx) == SYMBOL_REF)
+	    {
+	      offset_rtx =
+		gen_rtx (CONST, GET_MODE (offset_rtx),
+			 gen_rtx (PLUS, GET_MODE (offset_rtx),
+				  offset_rtx,
+				  gen_rtx (CONST_INT, 0, offset_adjust)));
+	      if (!CONSTANT_P (offset_rtx))
+		{
+		  obfree (storage);
+		  return;
+		}
+	    }
+	  else if (GET_CODE (offset_rtx) == CONST_INT)
+	    {
+	      offset_rtx = gen_rtx (CONST_INT, 0, INTVAL (offset_rtx) + offset_adjust);
+	    }
+	  else
+	    {
+	      obfree (storage);
+	      return;
+	    }
+	}
+      else
+	{
+	  offset_rtx = gen_rtx (CONST_INT, 0, offset_adjust);
+	}
+      if (index_rtx)
+	{
+	  if (base_rtx)
+	    {
+	      if (scale != 1)
+		{
+		  if (GET_CODE (offset_rtx) == CONST_INT &&
+		      INTVAL (offset_rtx) == 0)
+		    {
+		      ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx),
+			     gen_rtx (MULT, GET_MODE (index_rtx), index_rtx,
+				      scale_rtx),
+					 base_rtx);
+		    }
+		  else
+		    {
+		      ret_rtx = gen_rtx (PLUS, GET_MODE (offset_rtx),
+					 gen_rtx (PLUS, GET_MODE (base_rtx),
+			     gen_rtx (MULT, GET_MODE (index_rtx), index_rtx,
+				      scale_rtx),
+						  base_rtx),
+					 offset_rtx);
+		    }
+		}
+	      else
+		{
+		  if (GET_CODE (offset_rtx) == CONST_INT &&
+		      INTVAL (offset_rtx) == 0)
+		    {
+		      ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx), index_rtx, base_rtx);
+		    }
+		  else
+		    {
+		      ret_rtx = gen_rtx (PLUS, GET_MODE (offset_rtx),
+			     gen_rtx (PLUS, GET_MODE (index_rtx), index_rtx,
+				      base_rtx),
+					 offset_rtx);
+		    }
+		}
+	    }
+	  else
+	    {
+	      if (scale != 1)
+		{
+		  if (GET_CODE (offset_rtx) == CONST_INT &&
+		      INTVAL (offset_rtx) == 0)
+		    {
+		      ret_rtx = gen_rtx (MULT, GET_MODE (index_rtx), index_rtx, scale_rtx);
+		    }
+		  else
+		    {
+		      ret_rtx =
+			gen_rtx (PLUS, GET_MODE (offset_rtx),
+			     gen_rtx (MULT, GET_MODE (index_rtx), index_rtx,
+				      scale_rtx),
+				 offset_rtx);
+		    }
+		}
+	      else
+		{
+		  if (GET_CODE (offset_rtx) == CONST_INT &&
+		      INTVAL (offset_rtx) == 0)
+		    {
+		      ret_rtx = index_rtx;
+		    }
+		  else
+		    {
+		      ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx), index_rtx, offset_rtx);
+		    }
+		}
+	    }
+	}
+      else
+	{
+	  if (base_rtx)
+	    {
+	      if (GET_CODE (offset_rtx) == CONST_INT &&
+		  INTVAL (offset_rtx) == 0)
+		{
+		  ret_rtx = base_rtx;
+		}
+	      else
+		{
+		  ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx), base_rtx, offset_rtx);
+		}
+	    }
+	  else if (was_only_offset)
+	    {
+	      ret_rtx = offset_rtx;
+	    }
+	  else
+	    {
+	      obfree (storage);
+	      return;
+	    }
+	}
+      XEXP (mem_rtx, 0) = ret_rtx;
+      RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
+      return;
+    }
+  else
+    {
+      obfree (storage);
+      return;
+    }
+}
+
+/* return 1 if the first insn to set cc before insn also sets the register
+   reg_rtx - otherwise return 0
+*/
+int
+last_to_set_cc (reg_rtx, insn)
+     rtx reg_rtx, insn;
+{
+  rtx prev_insn = PREV_INSN (insn);
+
+  while (prev_insn)
+    {
+      if (GET_CODE (prev_insn) == NOTE)
+	{
+	  ;
+	}
+      else if (GET_CODE (prev_insn) == INSN)
+	{
+	  if (GET_CODE (PATTERN (prev_insn)) != SET)
+	    {
+	      return (0);
+	    }
+	  if (rtx_equal_p (SET_DEST (PATTERN (prev_insn)), reg_rtx))
+	    {
+	      if (sets_condition_code (SET_SRC (PATTERN (prev_insn))))
+		{
+		  return (1);
+		}
+	      else
+		{
+		  return (0);
+		}
+	    }
+	  else if (!doesnt_set_condition_code (SET_SRC (PATTERN (prev_insn))))
+	    {
+	      return (0);
+	    }
+	}
+      else
+	{
+	  return (0);
+	}
+      prev_insn = PREV_INSN (prev_insn);
+    }
+  return (0);
+}
+
+int
+doesnt_set_condition_code (pat)
+     rtx pat;
+{
+  switch (GET_CODE (pat))
+    {
+    case MEM:
+    case REG:
+      return (1);
+
+    default:
+      return (0);
+
+    }
+}
+
+int
+sets_condition_code (pat)
+     rtx pat;
+{
+  switch (GET_CODE (pat))
+    {
+    case PLUS:
+    case MINUS:
+    case AND:
+    case IOR:
+    case XOR:
+    case NOT:
+    case NEG:
+    case MULT:
+    case DIV:
+    case MOD:
+    case UDIV:
+    case UMOD:
+      return (1);
+
+    default:
+      return (0);
+
+    }
+}
+
+
+/* intel1 */
+int
+str_immediate_operand (op, mode)
+     register rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) == CONST_INT && INTVAL (op) <= 32 && INTVAL (op) >= 0)
+    {
+      return (1);
+    }
+  return (0);
+}
+
+/* intel1 */
+void
+override_options ()
+{
+  register int i, start;
+  register int regno;
+  register enum machine_mode mode;
+#if 0
+  int blend = 0;
+#endif
+
+  /* only one `-mcpu' allowed */
+  if (TARGET_X && (TARGET_X != TARGET_386) && (TARGET_X != TARGET_486) && (TARGET_X != TARGET_PENTIUM))
+    fatal ("multilple `-mcpu' definitions .\n");
+
+ /* if `-mcpu' use it, otherwise take default */
+ target_flags |= USE_CPU;
+
+  if (TARGET_PENTIUM)
+    x86_cpu = PROCESSOR_PENTIUM;
+  else if (TARGET_486)
+    x86_cpu = PROCESSOR_486;
+  else if (TARGET_386)
+    x86_cpu = PROCESSOR_386;
+  else /* no processor type ? */
+    fatal ("no processor type.\n");
+  
+#if 0 /* what happens if we have few -mcpu's, I don't think it's needed */
+  /* Identify the processor type */
+  if (!(TARGET_PENTIUM) && !(TARGET_486) && !(TARGET_386))
+    {
+      x86_cpu = PROCESSOR_PENTIUM;
+      target_flags |= (TARGET_486_SWITCH);
+      blend = 1;
+    }
+
+  else
+    {
+      x86_cpu = PROCESSOR_DEFAULT;
+      if (TARGET_PENTIUM)
+	{
+	  x86_cpu = PROCESSOR_PENTIUM;
+	}
+      if (TARGET_486)
+	{
+	  if (x86_cpu != PROCESSOR_DEFAULT)
+	    {
+	      error ("conflicting -mX86 : using blend");
+	      blend = 1;
+	      x86_cpu = PROCESSOR_PENTIUM;
+	      target_flags &= ~(TARGET_386_SWITCH);
+	      target_flags &= ~(TARGET_PENTIUM_SWITCH);
+	    }
+	  else
+	    {
+	      x86_cpu = PROCESSOR_486;
+	    }
+	}
+      if (TARGET_386)
+	{
+	  if (x86_cpu != PROCESSOR_DEFAULT)
+	    {
+	      error ("conflicting -mX86 : using blend");
+	      blend = 1;
+	      x86_cpu = PROCESSOR_486;
+	      target_flags &= ~(TARGET_386_SWITCH);
+	      target_flags &= ~(TARGET_PENTIUM_SWITCH);
+	      target_flags |= (TARGET_486_SWITCH);
+	    }
+	  else
+	    {
+	      x86_cpu = PROCESSOR_386;
+	    }
+	}
+
+
+    }
+#endif
+  if (opt_level >= 4)
+    {
+      if (TARGET_486)
+        {
+	  if (opt_level == 4
+	      && !flag_no_interleave_stack_non_stack)
+	    {
+	      flag_interleave_stack_non_stack = 1;
+	      flag_schedule_insns = 1;
+	    }
+        }
+#if 0
+      if(TARGET_BLEND)
+        {
+          if (!flag_no_risc)
+            flag_risc = 1;
+          if (!flag_no_risc_const)
+            flag_risc_const = 1;
+          if (!flag_no_recombine)
+            flag_recombine = 1;
+        }
+#endif
+      if (TARGET_PENTIUM)
+        {
+          if (!flag_no_risc)
+            flag_risc = 1;
+          if (!flag_no_risc_const)
+            flag_risc_const = 1;
+          /*if (!flag_no_recombine)
+            flag_recombine = 1;*/
+	  if (opt_level == 4
+	      && !flag_no_schedule_stack_reg_insns)
+	    {
+	      flag_schedule_stack_reg_insns = 1;
+	      flag_schedule_insns = 1;
+	    }
+	  if (opt_level == 4
+	      && !flag_no_interleave_stack_non_stack)
+	    {
+	      flag_interleave_stack_non_stack = 1;
+	      flag_schedule_insns = 1;
+	    }
+        }
+    }
+}
+
+
+
+
+optimization_options (level)
+     int level;
+{
+  opt_level = level;
+  if (level > 0)
+    {
+      flag_opt_reg_use = 1;
+      flag_reduce_index_givs = 1;
+    }
+  if (level >= 2)
+    {
+#ifdef INSN_SCHEDULING
+      flag_schedule_insns = 0;
+      flag_schedule_insns_after_reload = 0;
+#endif
+    }
+  if (level >= 3)
+    {
+      flag_inline_functions = 1;
+      flag_jump_back = 1;
+      flag_copy_prop = 1;
+      flag_compare_elim = 1;
+      flag_sftwr_pipe = 1;
+      flag_omit_frame_pointer = 1;
+      flag_reg_reg_copy_opt = 1;
+      flag_opt_reg_stack = 1;
+      flag_loop_after_global = 1;
+      flag_peep_spills = 1;
+      flag_replace_stack_mem = 1;
+      flag_opt_jumps_out = 1;
+      flag_replace_mem = 1;
+      flag_correct_cse_mistakes = 1;
+      flag_push_load_into_loop = 1;
+      flag_replace_reload_regs = 1;
+      flag_sign_extension_elim = 1;
+      flag_lift_stores = 1;
+      flag_runtime_lift_stores = 1;
+    }
+  if (level >= 4)
+    {
+#ifdef INSN_SCHEDULING
+      flag_schedule_insns_after_reload = 1;
+      flag_swap_for_agi = 1;
+      if (TARGET_PENTIUM)
+	{
+	  flag_risc = 1;
+	  flag_risc_const = 1;
+	  /*flag_recombine = 1;*/
+	  if (level == 4)
+	    {
+	      flag_schedule_stack_reg_insns = 1;
+	      flag_schedule_insns = 1;
+	    }
+	}
+#endif
+    }
+  if (level >= 5)
+    {
+#ifdef INSN_SCHEDULING
+      flag_schedule_insns = 1;
+#endif
+    }
+  if (flag_no_risc)
+    flag_risc = 0;
+  if (flag_no_risc_const)
+    flag_risc_const = 0;
+  if (flag_no_recombine)
+    flag_recombine = 0;
+  if (flag_no_risc_mem_dest)
+    flag_risc_mem_dest = 0;
+}
+
+/* intel1 */
+
+int
+is_fp_insn (insn)
+     rtx insn;
+{
+  if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
+      && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
+	  || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode))
+    {
+      return (1);
+    }
+  return (0);
+}
+
+
+/*
+  Return 1 if the mode of the SET_DEST of insn is floating point
+  and it is not an fld or a move from memory to memory.
+  Otherwise return 0
+*/
+int
+is_fp_dest (insn)
+     rtx insn;
+{
+  if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
+      && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
+	  || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode)
+      && GET_CODE (SET_DEST (PATTERN (insn))) == REG
+      && REGNO (SET_DEST (PATTERN (insn))) >= FIRST_FLOAT_REG
+      && GET_CODE (SET_SRC (insn)) != MEM
+     )
+    {
+      return (1);
+    }
+  return (0);
+}
+
+/*
+  Return 1 if the mode of the SET_DEST floating point and is memory
+  and the source is a register.  
+*/
+int
+is_fp_store (insn)
+     rtx insn;
+{
+  if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
+      && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
+	  || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode)
+      && GET_CODE (SET_DEST (PATTERN (insn))) == MEM
+      && GET_CODE (SET_SRC (PATTERN (insn))) == REG
+     )
+    {
+      return (1);
+    }
+  return (0);
+}
+
+
+/*
+  Return 1 if dep_insn sets a register which insn uses as a base
+  or index to reference memory.
+  otherwise return 0
+*/
+int
+agi_dependent (insn, dep_insn)
+     rtx insn, dep_insn;
+{
+  if (GET_CODE (dep_insn) == INSN && GET_CODE (PATTERN (dep_insn)) == SET
+      && GET_CODE (SET_DEST (PATTERN (dep_insn))) == REG)
+    {
+      return (reg_mentioned_in_mem (SET_DEST (PATTERN (dep_insn)), insn));
+    }
+  if (GET_CODE (dep_insn) == INSN && GET_CODE (PATTERN (dep_insn)) == SET
+      && GET_CODE (SET_DEST (PATTERN (dep_insn))) == MEM
+      && push_operand (SET_DEST (PATTERN (dep_insn)),
+                       GET_MODE (SET_DEST (PATTERN (dep_insn))))
+     )
+    {
+      return (reg_mentioned_in_mem (stack_pointer_rtx, insn));
+    }
+  
+  return (0);
+}
+
+/*
+  Return 1 if reg is used in rtl as a base or index for a memory ref
+  otherwise return 0.
+*/
+int
+reg_mentioned_in_mem (reg, rtl)
+     rtx reg, rtl;
+{
+  register char *fmt;
+  register int i;
+  register enum rtx_code code;
+
+  if (rtl == NULL)
+    return (0);
+
+  code = GET_CODE (rtl);
+
+  switch (code)
+    {
+    case HIGH:
+    case CONST_INT:
+    case CONST:
+    case CONST_DOUBLE:
+    case SYMBOL_REF:
+    case LABEL_REF:
+    case PC:
+    case CC0:
+    case SUBREG:
+      return (0);
+
+
+    }
+
+  if (code == MEM && reg_mentioned_p (reg, rtl))
+    {
+      return (1);
+    }
+
+  fmt = GET_RTX_FORMAT (code);
+
+  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+    {
+      if (fmt[i] == 'E')
+	{
+	  register int j;
+	  for (j = XVECLEN (rtl, i) - 1; j >= 0; j--)
+	    if (reg_mentioned_in_mem (reg, XVECEXP (rtl, i, j)))
+	      return 1;
+	}
+      else if (fmt[i] == 'e'
+	       && reg_mentioned_in_mem (reg, XEXP (rtl, i)))
+	return 1;
+    }
+  return (0);
+}
+
diff -r -u -H -N gcc-2.6.3/config/i386/i386.h gcc-i2.6.3/config/i386/i386.h
--- gcc-2.6.3/config/i386/i386.h	Wed Oct 19 16:52:09 1994
+++ gcc-i2.6.3/config/i386/i386.h	Wed Feb 15 23:07:40 1995
@@ -1,5 +1,8 @@
-/* Definitions of target machine for GNU compiler for Intel X86 (386, 486, pentium)
-   Copyright (C) 1988, 1992, 1994 Free Software Foundation, Inc.
+/* Definitions of target machine for GNU compiler for Intel X86.
+   Copyright (C) 1988, 1992 Free Software Foundation, Inc.
+
+   Pentium cpu support and other enhancements by Tevi Devor Intel Corp.
+   (tevi@iil.intel.com).
 
 This file is part of GNU CC.
 
@@ -54,6 +57,50 @@
 /* Run-time compilation parameters selecting different hardware subsets.  */
 
 extern int target_flags;
+/* Which processor to schedule for. intel1 */
+
+enum processor_type {
+  PROCESSOR_DEFAULT,
+  PROCESSOR_386,
+  PROCESSOR_486,
+  PROCESSOR_PENTIUM
+};
+extern enum processor_type x86_cpu;	/* which cpu are we scheduling for */
+
+/* intel1 */
+#define REDUCE_INDEX (TARGET_486 || TARGET_PENTIUM)
+#define SAVE_ON_REGS 1
+#define MAX_DEST_ADDR_GIVS 5
+#define PREFER_JUMP_NOT_TAKEN 1
+#define PREFER_CONST_IN_REG 1
+#define IGNORE_NON_DATA_DEP 1
+#define STORE_NOT_SET_CC0 1
+#define NO_CROSS_JUMP_ON_LOOP_ENTRY 1
+#define AGI 1
+/* #define SPILL1 */
+#define EXPENSIVE_OPS(x) \
+   ( GET_CODE(x)==MULT ? \
+       ((GET_CODE (XEXP (x, 1)) == CONST_INT && \
+	exact_log2 (INTVAL (XEXP (x, 1))) >= 0) ? 0 : 1) : \
+	(GET_CODE(x)==DIV || GET_CODE(x)==UDIV || \
+	 GET_CODE(x)==MOD || GET_CODE(x)==UMOD ))
+
+#define NO_STACK_REG_REORDER (!TARGET_PENTIUM)
+
+#define STACK_REG_REORDER \
+	((TARGET_PENTIUM) && reload_completed == 0 && flag_schedule_stack_reg_insns)
+
+#define STACK_NON_STACK_INTERLEAVE \
+	(reload_completed == 0 && flag_interleave_stack_non_stack)
+	
+#define IS_RISC_MODE(mode) (((mode) == QImode || (mode) == SImode))
+
+/* Number of extra pseudo registers we allocate for so that reg-stack
+   can replace fld's and fstps with movs
+*/
+#define SPARE_REGS 5
+#define OVERRIDE_OPTIONS override_options()
+
 
 /* Macros used in the machine description to test the flags.  */
 
@@ -62,142 +109,106 @@
 #define TARGET_CPU_DEFAULT 0
 #endif
 
-/* Masks for the -m switches */
-#define MASK_80387		000000000001	/* Hardware floating point */
-#define MASK_486		000000000002	/* 80486 specific */
-#define MASK_NOTUSED		000000000004	/* bit not currently used */
-#define MASK_RTD		000000000010	/* Use ret that pops args */
-#define MASK_REGPARM		000000000020	/* Pass args in eax, edx */
-#define MASK_SVR3_SHLIB		000000000040	/* Uninit locals into bss */
-#define MASK_IEEE_FP		000000000100	/* IEEE fp comparisons */
-#define MASK_FLOAT_RETURNS	000000000200	/* Return float in st(0) */
-#define MASK_NO_FANCY_MATH_387	000000000400	/* Disable sin, cos, sqrt */
-
-						/* Temporary codegen switches */
-#define MASK_DEBUG_ADDR		000001000000	/* Debug GO_IF_LEGITIMATE_ADDRESS */
-#define MASK_NO_WIDE_MULTIPLY	000002000000	/* Disable 32x32->64 multiplies */
-#define MASK_NO_MOVE		000004000000	/* Don't generate mem->mem */
-
-/* Use the floating point instructions */
-#define TARGET_80387 (target_flags & MASK_80387)
-
+/* Compile 80387 insns for floating point (not library calls).  */
+#define TARGET_80387 (target_flags & 1)
 /* Compile using ret insn that pops args.
    This will not work unless you use prototypes at least
    for all functions that can take varying numbers of args.  */  
-#define TARGET_RTD (target_flags & MASK_RTD)
-
+#define TARGET_RTD (target_flags & 8)
 /* Compile passing first two args in regs 0 and 1.
    This exists only to test compiler features that will
    be needed for RISC chips.  It is not usable
    and is not intended to be usable on this cpu.  */
-#define TARGET_REGPARM (target_flags & MASK_RTD)
+#define TARGET_REGPARM (target_flags & 020)
 
 /* Put uninitialized locals into bss, not data.
    Meaningful only on svr3.  */
-#define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
+#define TARGET_SVR3_SHLIB (target_flags & 040)
 
 /* Use IEEE floating point comparisons.  These handle correctly the cases
    where the result of a comparison is unordered.  Normally SIGFPE is
    generated in such cases, in which case this isn't needed.  */
-#define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
+#define TARGET_IEEE_FP (target_flags & 0100)
 
 /* Functions that return a floating point value may return that value
    in the 387 FPU or in 386 integer registers.  If set, this flag causes
    the 387 to be used, which is compatible with most calling conventions. */
-#define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
-
-/* Disable generation of FP sin, cos and sqrt operations for 387.
-   This is because FreeBSD lacks these in the math-emulator-code */
-#define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
-
-/* Temporary switches for tuning code generation */
-
-/* Disable 32x32->64 bit multiplies that are used for long long multiplies
-   and division by constants, but sometimes cause reload problems.  */
-#define TARGET_NO_WIDE_MULTIPLY (target_flags & MASK_NO_WIDE_MULTIPLY)
-#define TARGET_WIDE_MULTIPLY (!TARGET_NO_WIDE_MULTIPLY)
-
-/* Debug GO_IF_LEGITIMATE_ADDRESS */
-#define TARGET_DEBUG_ADDR (target_flags & MASK_DEBUG_ADDR)
-
-/* Hack macros for tuning code generation */
-#define TARGET_MOVE	((target_flags & MASK_NO_MOVE) == 0)	/* Don't generate memory->memory */
-
-/* Specific hardware switches */
-#define TARGET_486	(target_flags & MASK_486)	/* 80486DX, 80486SX, 80486DX[24] */
-#define TARGET_386	(!TARGET_486) 			/* 80386 */
-
-#define TARGET_SWITCHES							\
-{ { "80387",			 MASK_80387 },				\
-  { "no-80387",			-MASK_80387 },				\
-  { "hard-float",		 MASK_80387 },				\
-  { "soft-float",		-MASK_80387 },				\
-  { "no-soft-float",		 MASK_80387 },				\
-  { "386",			-MASK_486 },				\
-  { "no-386",			 MASK_486 },				\
-  { "486",			 MASK_486 },				\
-  { "no-486",			-MASK_486 },				\
-  { "rtd",			 MASK_RTD },				\
-  { "no-rtd",			-MASK_RTD },				\
-  { "regparm",			 MASK_REGPARM },			\
-  { "no-regparm",		-MASK_REGPARM },			\
-  { "svr3-shlib",		 MASK_SVR3_SHLIB },			\
-  { "no-svr3-shlib",		-MASK_SVR3_SHLIB },			\
-  { "ieee-fp",			 MASK_IEEE_FP },			\
-  { "no-ieee-fp",		-MASK_IEEE_FP },			\
-  { "fp-ret-in-387",		 MASK_FLOAT_RETURNS },			\
-  { "no-fp-ret-in-387",		-MASK_FLOAT_RETURNS },			\
-  { "no-fancy-math-387",	 MASK_NO_FANCY_MATH_387 },		\
-  { "fancy-math-387",		-MASK_NO_FANCY_MATH_387 },		\
-  { "no-wide-multiply",		 MASK_NO_WIDE_MULTIPLY },		\
-  { "wide-multiply",		-MASK_NO_WIDE_MULTIPLY },		\
-  { "debug-addr",		 MASK_DEBUG_ADDR },			\
-  { "no-debug-addr",		-MASK_DEBUG_ADDR },			\
-  { "move",			-MASK_NO_MOVE },			\
-  { "no-move",			 MASK_NO_MOVE },			\
-  SUBTARGET_SWITCHES							\
-  { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT}}
-
-/* This macro is similar to `TARGET_SWITCHES' but defines names of
-   command options that have values.  Its definition is an
-   initializer with a subgrouping for each command option.
-
-   Each subgrouping contains a string constant, that defines the
-   fixed part of the option name, and the address of a variable.  The
-   variable, type `char *', is set to the variable part of the given
-   option if the fixed part matches.  The actual option name is made
-   by appending `-m' to the specified name.  */
-#define TARGET_OPTIONS							\
-{ { "reg-alloc=", &i386_reg_alloc_order },				\
-  SUBTARGET_OPTIONS }
-
-/* Sometimes certain combinations of command options do not make
-   sense on a particular target machine.  You can define a macro
-   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
-   defined, is executed once just after all the command options have
-   been parsed.
+#define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & 0200)
 
-   Don't use this macro to turn on various extra optimizations for
-   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */
+/* Macro to define tables used to set the flags.
+   This is a list in braces of pairs in braces,
+   each pair being { "NAME", VALUE }
+   where VALUE is the bits to set or minus the bits to clear.
+   An empty string NAME is used to identify the default VALUE.  */
+
+/* intel1 */
+#define TARGET_486_SWITCH 2
+#define TARGET_486 (target_flags & TARGET_486_SWITCH)
+/* Compile code for a Pentium. intel1 */
+#define TARGET_PENTIUM_SWITCH 4
+#define TARGET_PENTIUM (target_flags & TARGET_PENTIUM_SWITCH)
+/* Compile code for an i386. intel1 */
+#define TARGET_386_SWITCH 0400
+#define TARGET_386 (target_flags & TARGET_386_SWITCH)
+/* Compile code for a Blend. intel1 */
+#define TARGET_BLEND_SWITCH 02000
+#define TARGET_BLEND (target_flags & TARGET_BLEND_SWITCH)
+
+#define TARGET_X ((TARGET_386) | (TARGET_486) | (TARGET_PENTIUM))
+#define USE_CPU ((TARGET_X) ? (TARGET_X) : TARGET_CPU_DEFAULT)
+
+#define TARGET_SWITCHES  \
+  { { "80387", 1},				\
+    { "no-80387", -1},				\
+    { "soft-float", -1},			\
+    { "no-soft-float", 1},			\
+    { "486", 2},				\
+    { "no-486", -2},				\
+    { "386", 0400},				\
+    { "pentium", 4},				\
+    { "blend", 02000},				\
+    { "rtd", 8},				\
+    { "no-rtd", -8},				\
+    { "regparm", 020},				\
+    { "no-regparm", -020},			\
+    { "svr3-shlib", 040},			\
+    { "no-svr3-shlib", -040},			\
+    { "ieee-fp", 0100},				\
+    { "no-ieee-fp", -0100},			\
+    { "fp-ret-in-387", 0200},			\
+    { "no-fp-ret-in-387", -0200},		\
+    SUBTARGET_SWITCHES                          \
+    { "", TARGET_DEFAULT }}
 
-#define OVERRIDE_OPTIONS override_options ()
-
-/* These are meant to be redefined in the host dependent files */
+/* This is meant to be redefined in the host dependent files */
 #define SUBTARGET_SWITCHES
-#define SUBTARGET_OPTIONS
 
 
+/* intel1 */
+
+#define SUB_TARGET_STRING \
+(TARGET_PENTIUM ? "Pentium"  : (TARGET_386 ? "Intel386" : "Intel486"))
+
+#define SUB_TARGET_VERSION fprintf (stderr, " [%s cpu] ", SUB_TARGET_STRING)
+
+
+/* Define this to change the optimizations performed by default.  */
+
+#define OPTIMIZATION_OPTIONS(LEVEL)	\
+optimization_options(LEVEL)
+
 /* target machine storage layout */
 
 /* Define for XFmode extended real floating point support.
    This will automatically cause REAL_ARITHMETIC to be defined.  */
 #define LONG_DOUBLE_TYPE_SIZE 96
-
+ 
 /* Define if you don't want extended real, but do want to use the
    software floating point emulator for REAL_ARITHMETIC and
    decimal <-> binary conversion. */
 /* #define REAL_ARITHMETIC */
 
+
 /* Define this if most significant byte of a word is the lowest numbered.  */
 /* That is true on the 80386.  */
 
@@ -250,6 +261,9 @@
    quantities, but these can be aligned on any 32-bit boundary.  */
 #define BIGGEST_ALIGNMENT 32
 
+/* intel1 - align DFmode constants and nonaggregates */
+#define ALIGN_DFmode (!TARGET_386)
+
 /* Set this non-zero if move instructions will actually fail to work
    when given unaligned data.  */
 #define STRICT_ALIGNMENT 0
@@ -275,6 +289,8 @@
    for details. */
 
 #define STACK_REGS
+/* intel1 */
+#define IS_STACK_MODE(mode) (mode==DFmode || mode==SFmode)
 
 /* Number of actual hardware registers.
    The hardware registers are assigned numbers for the compiler
@@ -312,44 +328,6 @@
 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \
 {  1, 1, 1, 0, 0, 0, 0, 1, 1,  1,  1,  1,  1,  1,  1,  1,  1 }
 
-/* Order in which to allocate registers.  Each register must be
-   listed once, even those in FIXED_REGISTERS.  List frame pointer
-   late and fixed registers last.  Note that, in general, we prefer
-   registers listed in CALL_USED_REGISTERS, keeping the others
-   available for storage of persistent values.
-
-   Three different versions of REG_ALLOC_ORDER have been tried:
-
-   If the order is edx, ecx, eax, ... it produces a slightly faster compiler,
-   but slower code on simple functions returning values in eax.
-
-   If the order is eax, ecx, edx, ... it causes reload to abort when compiling
-   perl 4.036 due to not being able to create a DImode register (to hold a 2
-   word union).
-
-   If the order is eax, edx, ecx, ... it produces better code for simple
-   functions, and a slightly slower compiler.  Users complained about the code
-   generated by allocating edx first, so restore the 'natural' order of things. */
-
-#define REG_ALLOC_ORDER \
-/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \
-{  0, 1, 2, 3, 4, 5, 6, 7, 8,  9, 10, 11, 12, 13, 14, 15, 16 }
-
-/* A C statement (sans semicolon) to choose the order in which to
-   allocate hard registers for pseudo-registers local to a basic
-   block.
-
-   Store the desired register order in the array `reg_alloc_order'.
-   Element 0 should be the register to allocate first; element 1, the
-   next register; and so on.
-
-   The macro body should not assume anything about the contents of
-   `reg_alloc_order' before execution of the macro.
-
-   On most machines, it is not necessary to define this macro.  */
-
-#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
-
 /* Macro to conditionally modify fixed_regs/call_used_regs.  */
 #define CONDITIONAL_REGISTER_USAGE			\
   {							\
@@ -391,6 +369,9 @@
 /* The casts to int placate a compiler on a microvax,
    for cross-compiler testing.  */
 
+/* intel1 - added case of (REGNO)==16 (gbug12)*/
+/*   : (REGNO) == 16 ? 1                             \ */
+
 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
   ((REGNO) < 2 ? 1						\
    : (REGNO) < 4 ? 1						\
@@ -462,27 +443,6 @@
 /* Place in which caller passes the structure value address.
    0 means push the value on the stack like an argument.  */
 #define STRUCT_VALUE 0
-
-/* A C expression which can inhibit the returning of certain function
-   values in registers, based on the type of value.  A nonzero value
-   says to return the function value in memory, just as large
-   structures are always returned.  Here TYPE will be a C expression
-   of type `tree', representing the data type of the value.
-
-   Note that values of mode `BLKmode' must be explicitly handled by
-   this macro.  Also, the option `-fpcc-struct-return' takes effect
-   regardless of this macro.  On most systems, it is possible to
-   leave the macro undefined; this causes a default definition to be
-   used, whose value is the constant 1 for `BLKmode' values, and 0
-   otherwise.
-
-   Do not use this macro to indicate that structures and unions
-   should always be returned in memory.  You should instead use
-   `DEFAULT_PCC_STRUCT_RETURN' to indicate this.  */
-
-#define RETURN_IN_MEMORY(TYPE) \
-  ((TYPE_MODE (TYPE) == BLKmode) || int_size_in_bytes (TYPE) > 12)
-
 
 /* Define the classes of registers for register constraints in the
    machine description.  Also define ranges of constants.
@@ -512,7 +472,6 @@
 {
   NO_REGS,
   AREG, DREG, CREG, BREG,
-  AD_REGS,			/* %eax/%edx for DImode */
   Q_REGS,			/* %eax %ebx %ecx %edx */
   SIREG, DIREG,
   INDEX_REGS,			/* %eax %ebx %ecx %edx %esi %edi %ebp */
@@ -531,7 +490,6 @@
 #define REG_CLASS_NAMES \
 {  "NO_REGS",				\
    "AREG", "DREG", "CREG", "BREG",	\
-   "AD_REGS",				\
    "Q_REGS",				\
    "SIREG", "DIREG",			\
    "INDEX_REGS",			\
@@ -547,10 +505,9 @@
 #define REG_CLASS_CONTENTS \
 {      0,							\
      0x1,    0x2,  0x4,	 0x8,	/* AREG, DREG, CREG, BREG */	\
-     0x3,			/* AD_REGS */			\
      0xf,			/* Q_REGS */			\
     0x10,   0x20,		/* SIREG, DIREG */		\
- 0x07f,				/* INDEX_REGS */		\
+ 0x1007f,			/* INDEX_REGS */		\
  0x100ff,			/* GENERAL_REGS */		\
   0x0100, 0x0200,		/* FP_TOP_REG, FP_SECOND_REG */	\
   0xff00,			/* FLOAT_REGS */		\
@@ -561,6 +518,7 @@
    reg number REGNO.  This could be a conditional expression
    or could index an array.  */
 
+extern enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
 
 /* When defined, the compiler allows registers explicitly used in the
@@ -618,9 +576,8 @@
    (C) == 'b' ? BREG :						\
    (C) == 'c' ? CREG :						\
    (C) == 'd' ? DREG :						\
-   (C) == 'A' ? AD_REGS :					\
    (C) == 'D' ? DIREG :						\
-   (C) == 'S' ? SIREG : NO_REGS)
+   (C) == 'S' ? SIREG : NO_REGS) /* intel1 changed to e from S */
 
 /* The letters I, J, K, L and M in a register constraint string
    can be used to stand for particular ranges of immediate operands.
@@ -632,6 +589,7 @@
    J is for DImode shifts.
    K and L are for an `andsi' optimization.
    M is for shifts that can be executed by the "lea" opcode.
+   O is for block moves intel1
    */
 
 #define CONST_OK_FOR_LETTER_P(VALUE, C)  \
@@ -640,6 +598,7 @@
    (C) == 'K' ? (VALUE) == 0xff :		\
    (C) == 'L' ? (VALUE) == 0xffff :		\
    (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 :	\
+   (C) == 'O' ? (VALUE) >= 0 && (VALUE) <= 32 :	\
    0)
 
 /* Similar, but for floating constants, and defining letters G and H.
@@ -692,33 +651,91 @@
 #define CLASS_MAX_NREGS(CLASS, MODE)	\
  (FLOAT_CLASS_P (CLASS) ? 1 :		\
   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
+
+
+/* A C statement (sans semicolon) to update the integer variable COST
+   based on the relationship between INSN that is dependent on
+   DEP_INSN through the dependence LINK.  The default is to make no
+   adjustment to COST.  */
+#define ADJUST_COST(insn,link,dep_insn,cost)				\
+  {									\
+    rtx next_inst;							\
+    if (GET_CODE (dep_insn) == CALL_INSN)				\
+      (cost) = 0;							\
+        if (GET_CODE (dep_insn) == INSN					\
+            && GET_CODE (PATTERN (dep_insn)) == SET			\
+            && GET_CODE (SET_DEST (PATTERN (dep_insn))) == REG		\
+            && GET_CODE (insn) == INSN					\
+            && GET_CODE (PATTERN (insn)) == SET				\
+            && !reg_overlap_mentioned_p (SET_DEST (PATTERN (dep_insn)),	\
+            	                         SET_SRC (PATTERN (insn))))	\
+          {								\
+            (cost) = 0;							\
+          }								\
+    if (GET_CODE (insn) == JUMP_INSN)					\
+      {									\
+        (cost) = 0;							\
+      }									\
+    if (TARGET_PENTIUM)							\
+      {									\
+        if (cost !=0 && is_fp_insn (insn) && is_fp_insn (dep_insn) 	\
+            && !is_fp_dest (dep_insn))					\
+          {								\
+            (cost) = 0;							\
+          }								\
+        if (agi_dependent (insn, dep_insn))				\
+          {								\
+            (cost) = 3;							\
+          }								\
+        else if (GET_CODE (insn) == INSN 				\
+                 && GET_CODE (PATTERN (insn)) == SET			\
+                 && SET_DEST (PATTERN (insn)) == cc0_rtx		\
+                 && (next_inst = next_nonnote_insn (insn))		\
+                 && GET_CODE (next_inst) == JUMP_INSN)			\
+          { /* compare probably paired with jump */			\
+            (cost) = 0;							\
+          }								\
+      }									\
+    else								\
+    if(!is_fp_dest (dep_insn))						\
+      {									\
+        if(!agi_dependent (insn, dep_insn))				\
+          (cost) = 0;							\
+         else if (TARGET_486)						\
+           (cost) = 2;							\
+      }									\
+    else								\
+    if(is_fp_store (insn) && is_fp_insn (dep_insn)			\
+       && NEXT_INSN (insn) && NEXT_INSN (NEXT_INSN (insn))		\
+       && NEXT_INSN (NEXT_INSN (NEXT_INSN (insn)))			\
+       && (GET_CODE (NEXT_INSN (insn)) == INSN)				\
+       && (GET_CODE (NEXT_INSN (NEXT_INSN (insn))) == JUMP_INSN)	\
+       && (GET_CODE (NEXT_INSN (NEXT_INSN (NEXT_INSN (insn)))) 		\
+            == NOTE)							\
+       && NOTE_LINE_NUMBER (NEXT_INSN (NEXT_INSN (NEXT_INSN (insn)))) 	\
+           == NOTE_INSN_LOOP_END)					\
+      {									\
+           (cost) = 3;							\
+      }									\
+  }									
 
-/* A C expression whose value is nonzero if pseudos that have been
-   assigned to registers of class CLASS would likely be spilled
-   because registers of CLASS are needed for spill registers.
-
-   The default value of this macro returns 1 if CLASS has exactly one
-   register and zero otherwise.  On most machines, this default
-   should be used.  Only define this macro to some other expression
-   if pseudo allocated by `local-alloc.c' end up in memory because
-   their hard registers were needed for spill regisers.  If this
-   macro returns nonzero for those classes, those pseudos will only
-   be allocated by `global.c', which knows how to reallocate the
-   pseudo to another register.  If there would not be another
-   register available for reallocation, you should not change the
-   definition of this macro since the only effect of such a
-   definition would be to slow down register allocation.  */
-
-#define CLASS_LIKELY_SPILLED_P(CLASS)					\
-  (((CLASS) == AREG)							\
-   || ((CLASS) == DREG)							\
-   || ((CLASS) == CREG)							\
-   || ((CLASS) == BREG)							\
-   || ((CLASS) == AD_REGS)						\
-   || ((CLASS) == SIREG)						\
-   || ((CLASS) == DIREG))
 
-
+#define ADJUST_BLOCKAGE(last_insn,insn,blockage)			\
+  {									\
+    if(is_fp_store (last_insn) && is_fp_insn (insn)			\
+       && NEXT_INSN (last_insn) && NEXT_INSN (NEXT_INSN (last_insn))	\
+       && NEXT_INSN (NEXT_INSN (NEXT_INSN (last_insn)))			\
+       && (GET_CODE (NEXT_INSN (last_insn)) == INSN)			\
+       && (GET_CODE (NEXT_INSN (NEXT_INSN (last_insn))) == JUMP_INSN)	\
+       && (GET_CODE (NEXT_INSN (NEXT_INSN (NEXT_INSN (last_insn)))) 	\
+            == NOTE)							\
+       && NOTE_LINE_NUMBER (NEXT_INSN (NEXT_INSN (NEXT_INSN (last_insn)))) 	\
+           == NOTE_INSN_LOOP_END)					\
+      {									\
+           (blockage) = 3;						\
+      }									\
+  }									
+
 /* Stack layout; function entry, exit and calling.  */
 
 /* Define this if pushing a word on the stack
@@ -889,102 +906,6 @@
     }									\
 }
 
-/* A C statement or compound statement to output to FILE some
-   assembler code to initialize basic-block profiling for the current
-   object module.  This code should call the subroutine
-   `__bb_init_func' once per object module, passing it as its sole
-   argument the address of a block allocated in the object module.
-
-   The name of the block is a local symbol made with this statement:
-
-	ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
-
-   Of course, since you are writing the definition of
-   `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
-   can take a short cut in the definition of this macro and use the
-   name that you know will result.
-
-   The first word of this block is a flag which will be nonzero if the
-   object module has already been initialized.  So test this word
-   first, and do not call `__bb_init_func' if the flag is nonzero.  */
-
-#undef	FUNCTION_BLOCK_PROFILER
-#define FUNCTION_BLOCK_PROFILER(STREAM, LABELNO)			\
-do									\
-  {									\
-    static int num_func = 0;						\
-    rtx xops[8];							\
-    char block_table[80], false_label[80];				\
-									\
-    ASM_GENERATE_INTERNAL_LABEL (block_table, "LPBX", 0);		\
-    ASM_GENERATE_INTERNAL_LABEL (false_label, "LPBZ", num_func);	\
-									\
-    xops[0] = const0_rtx;						\
-    xops[1] = gen_rtx (SYMBOL_REF, VOIDmode, block_table);		\
-    xops[2] = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, VOIDmode, false_label)); \
-    xops[3] = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, VOIDmode, "__bb_init_func")); \
-    xops[4] = gen_rtx (MEM, Pmode, xops[1]);				\
-    xops[5] = stack_pointer_rtx;					\
-    xops[6] = GEN_INT (4);						\
-    xops[7] = gen_rtx (REG, Pmode, 0);	/* eax */			\
-									\
-    CONSTANT_POOL_ADDRESS_P (xops[1]) = TRUE;				\
-    CONSTANT_POOL_ADDRESS_P (xops[2]) = TRUE;				\
-									\
-    output_asm_insn (AS2(cmp%L4,%0,%4), xops);				\
-    output_asm_insn (AS1(jne,%2), xops);				\
-									\
-    if (!flag_pic)							\
-      output_asm_insn (AS1(push%L1,%1), xops);				\
-    else								\
-      {									\
-	output_asm_insn (AS2 (lea%L7,%a1,%7), xops);			\
-	output_asm_insn (AS1 (push%L7,%7), xops);			\
-      }									\
-									\
-    output_asm_insn (AS1(call,%P3), xops);				\
-    output_asm_insn (AS2(add%L0,%6,%5), xops);				\
-    ASM_OUTPUT_INTERNAL_LABEL (STREAM, "LPBZ", num_func);		\
-    num_func++;								\
-  }									\
-while (0)
-
-
-/* A C statement or compound statement to increment the count
-   associated with the basic block number BLOCKNO.  Basic blocks are
-   numbered separately from zero within each compilation.  The count
-   associated with block number BLOCKNO is at index BLOCKNO in a
-   vector of words; the name of this array is a local symbol made
-   with this statement:
-
-	ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2);
-
-   Of course, since you are writing the definition of
-   `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
-   can take a short cut in the definition of this macro and use the
-   name that you know will result.  */
-
-#define BLOCK_PROFILER(STREAM, BLOCKNO)					\
-do									\
-  {									\
-    rtx xops[1], cnt_rtx;						\
-    char counts[80];							\
-									\
-    ASM_GENERATE_INTERNAL_LABEL (counts, "LPBX", 2);			\
-    cnt_rtx = gen_rtx (SYMBOL_REF, VOIDmode, counts);			\
-    SYMBOL_REF_FLAG (cnt_rtx) = TRUE;					\
-									\
-    if (BLOCKNO)							\
-      cnt_rtx = plus_constant (cnt_rtx, (BLOCKNO)*4);			\
-									\
-    if (flag_pic)							\
-      cnt_rtx = gen_rtx (PLUS, Pmode, pic_offset_table_rtx, cnt_rtx);	\
-									\
-    xops[0] = gen_rtx (MEM, SImode, cnt_rtx);				\
-    output_asm_insn (AS1(inc%L0,%0), xops);				\
-  }									\
-while (0)
-
 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
    the stack pointer does not matter.  The value is tested only in
    functions that have frame pointers.
@@ -1148,35 +1069,36 @@
    After reload, it makes no difference, since pseudo regs have
    been eliminated by then.  */
 
+#ifndef REG_OK_STRICT
+
+/* Nonzero if X is a hard reg that can be used as an index or if
+   it is a pseudo reg.  */
 
-/* Non strict versions, pseudos are ok */
-#define REG_OK_FOR_INDEX_NONSTRICT_P(X)					\
-  (REGNO (X) < STACK_POINTER_REGNUM					\
+#define REG_OK_FOR_INDEX_P(X) \
+  (REGNO (X) < STACK_POINTER_REGNUM \
    || REGNO (X) >= FIRST_PSEUDO_REGISTER)
 
-#define REG_OK_FOR_BASE_NONSTRICT_P(X)					\
-  (REGNO (X) <= STACK_POINTER_REGNUM					\
-   || REGNO (X) == ARG_POINTER_REGNUM					\
-   || REGNO (X) >= FIRST_PSEUDO_REGISTER)
+/* Nonzero if X is a hard reg that can be used as a base reg
+   of if it is a pseudo reg.  */
+  /* ?wfs */
+
+#define REG_OK_FOR_BASE_P(X) \
+  (REGNO (X) <= STACK_POINTER_REGNUM \
+   || REGNO (X) == ARG_POINTER_REGNUM \
+   || REGNO(X) >= FIRST_PSEUDO_REGISTER)
 
-#define REG_OK_FOR_STRREG_NONSTRICT_P(X)				\
+#define REG_OK_FOR_STRREG_P(X) \
   (REGNO (X) == 4 || REGNO (X) == 5 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
 
-/* Strict versions, hard registers only */
-#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-#define REG_OK_FOR_BASE_STRICT_P(X)  REGNO_OK_FOR_BASE_P (REGNO (X))
-#define REG_OK_FOR_STRREG_STRICT_P(X)					\
-  (REGNO_OK_FOR_DIREG_P (REGNO (X)) || REGNO_OK_FOR_SIREG_P (REGNO (X)))
+#else
 
-#ifndef REG_OK_STRICT
-#define REG_OK_FOR_INDEX_P(X)  REG_OK_FOR_INDEX_NONSTRICT_P(X)
-#define REG_OK_FOR_BASE_P(X)   REG_OK_FOR_BASE_NONSTRICT_P(X)
-#define REG_OK_FOR_STRREG_P(X) REG_OK_FOR_STRREG_NONSTRICT_P(X)
+/* Nonzero if X is a hard reg that can be used as an index.  */
+#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
+/* Nonzero if X is a hard reg that can be used as a base reg.  */
+#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
+#define REG_OK_FOR_STRREG_P(X) \
+  (REGNO_OK_FOR_DIREG_P (REGNO (X)) || REGNO_OK_FOR_SIREG_P (REGNO (X)))
 
-#else
-#define REG_OK_FOR_INDEX_P(X)  REG_OK_FOR_INDEX_STRICT_P(X)
-#define REG_OK_FOR_BASE_P(X)   REG_OK_FOR_BASE_STRICT_P(X)
-#define REG_OK_FOR_STRREG_P(X) REG_OK_FOR_STRREG_STRICT_P(X)
 #endif
 
 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
@@ -1202,22 +1124,62 @@
 
 #define LEGITIMATE_CONSTANT_P(X) 1
 
-#ifdef REG_OK_STRICT
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)				\
-{									\
-  if (legitimate_address_p (MODE, X, 1))				\
-    goto ADDR;								\
-}
+#define GO_IF_INDEXABLE_BASE(X, ADDR)	\
+ if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) goto ADDR
 
-#else
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)				\
+#define LEGITIMATE_INDEX_REG_P(X)   \
+  (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
+
+/* Return 1 if X is an index or an index times a scale.  */
+
+#define LEGITIMATE_INDEX_P(X)   \
+   (LEGITIMATE_INDEX_REG_P (X)				\
+    || (GET_CODE (X) == MULT				\
+	&& LEGITIMATE_INDEX_REG_P (XEXP (X, 0))		\
+	&& GET_CODE (XEXP (X, 1)) == CONST_INT		\
+	&& (INTVAL (XEXP (X, 1)) == 2			\
+	    || INTVAL (XEXP (X, 1)) == 4		\
+	    || INTVAL (XEXP (X, 1)) == 8)))
+
+/* Go to ADDR if X is an index term, a base reg, or a sum of those.  */
+
+#define GO_IF_INDEXING(X, ADDR)	\
+{ if (LEGITIMATE_INDEX_P (X)) goto ADDR;				\
+  GO_IF_INDEXABLE_BASE (X, ADDR);					\
+  if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0)))		\
+    { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); }			\
+  if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1)))		\
+    { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
+
+/* We used to allow this, but it isn't ever used.
+   || ((GET_CODE (X) == POST_DEC || GET_CODE (X) == POST_INC)		\
+       && REG_P (XEXP (X, 0))						\
+       && REG_OK_FOR_STRREG_P (XEXP (X, 0)))				\
+*/
+
+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)	\
 {									\
-  if (legitimate_address_p (MODE, X, 0))				\
+  if (CONSTANT_ADDRESS_P (X)						\
+      && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (X)))			\
     goto ADDR;								\
+  GO_IF_INDEXING (X, ADDR);						\
+  if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1)))		\
+    {									\
+      rtx x0 = XEXP (X, 0);						\
+      if (! flag_pic || ! SYMBOLIC_CONST (XEXP (X, 1)))			\
+	{ GO_IF_INDEXING (x0, ADDR); }					\
+      else if (x0 == pic_offset_table_rtx)				\
+	goto ADDR;							\
+      else if (GET_CODE (x0) == PLUS)					\
+	{								\
+	  if (XEXP (x0, 0) == pic_offset_table_rtx)			\
+	    { GO_IF_INDEXABLE_BASE (XEXP (x0, 1), ADDR); }		\
+	  if (XEXP (x0, 1) == pic_offset_table_rtx)			\
+	    { GO_IF_INDEXABLE_BASE (XEXP (x0, 0), ADDR); }		\
+	}								\
+    }									\
 }
 
-#endif
-
 /* Try machine-dependent ways of modifying an illegitimate address
    to be legitimate.  If we find one, return the new, valid address.
    This macro is used in only one place: `memory_address' in explow.c.
@@ -1239,13 +1201,41 @@
    When -fpic is used, special handling is needed for symbolic references.
    See comments by legitimize_pic_address in i386.c for details.  */
 
-#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)				\
-{									\
-  rtx orig_x = (X);							\
-  (X) = legitimize_address (X, OLDX, MODE);				\
-  if (memory_address_p (MODE, X))					\
-    goto WIN;								\
-}
+#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)   \
+{ extern rtx legitimize_pic_address ();					\
+  int ch = (X) != (OLDX);						\
+  if (flag_pic && SYMBOLIC_CONST (X))					\
+    {									\
+      (X) = legitimize_pic_address (X, 0);				\
+      if (memory_address_p (MODE, X))					\
+	goto WIN;							\
+    }									\
+  if (GET_CODE (X) == PLUS)						\
+    { if (GET_CODE (XEXP (X, 0)) == MULT)				\
+	ch = 1, XEXP (X, 0) = force_operand (XEXP (X, 0), 0);		\
+      if (GET_CODE (XEXP (X, 1)) == MULT)				\
+	ch = 1, XEXP (X, 1) = force_operand (XEXP (X, 1), 0);		\
+      if (ch && GET_CODE (XEXP (X, 1)) == REG				\
+	  && GET_CODE (XEXP (X, 0)) == REG)				\
+	goto WIN;							\
+      if (flag_pic && SYMBOLIC_CONST (XEXP (X, 1)))			\
+        ch = 1, (X) = legitimize_pic_address (X, 0);			\
+      if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); }		\
+      if (GET_CODE (XEXP (X, 0)) == REG)                                \
+	{ register rtx temp = gen_reg_rtx (Pmode);			\
+	  register rtx val = force_operand (XEXP (X, 1), temp);		\
+	  if (val != temp) emit_move_insn (temp, val);			\
+	  XEXP (X, 1) = temp;						\
+	  goto WIN; }							\
+      else if (GET_CODE (XEXP (X, 1)) == REG)				\
+	{ register rtx temp = gen_reg_rtx (Pmode);			\
+	  register rtx val = force_operand (XEXP (X, 0), temp);		\
+	  if (val != temp) emit_move_insn (temp, val);			\
+	  XEXP (X, 0) = temp;						\
+	  goto WIN; }}}
+
+/* intel1 */
+#define REWRITE_ADDRESS(x) rewrite_address(x)
 
 /* Nonzero if the constant value X is a legitimate general operand
    when generating PIC code.  It is given that flag_pic is on and 
@@ -1348,6 +1338,10 @@
 /* Nonzero if access to memory by bytes is slow and undesirable.  */
 #define SLOW_BYTE_ACCESS 0
 
+/* intel1 */
+/* Nonzero if access to memory by shorts is slow and undesirable.  */
+#define SLOW_SHORT_ACCESS 1
+
 /* Define if shifts truncate the shift count
    which implies one can omit a sign-extension or zero-extension
    of a shift count.  */
@@ -1469,6 +1463,7 @@
    stored from the compare operation.  Note that we can't use "rtx" here
    since it hasn't been defined!  */
 
+extern struct rtx_def *i386_compare_op0, *i386_compare_op1;
 extern struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)();
 
 /* Tell final.c how to eliminate redundant test instructions.  */
@@ -1476,6 +1471,10 @@
 /* Here we define machine-dependent flags and fields in cc_status
    (see `conditions.h').  */
 
+/* intel1 Set if the cc value is was actually from the 80387 and
+   we are testing eax directly (i.e. no sahf) */
+#define CC_TEST_AX 020000
+
 /* Set if the cc value is actually in the 80387, so a floating point
    conditional branch must be output.  */
 #define CC_IN_80387 04000
@@ -1773,12 +1772,12 @@
 	 { fputs ("argp", FILE); break; }		\
        if (STACK_TOP_P (X))				\
 	 { fputs ("st(0)", FILE); break; }		\
-       if (FP_REG_P (X))				\
-	 { fputs (hi_name[REGNO(X)], FILE); break; }	\
        switch (GET_MODE_SIZE (GET_MODE (X)))		\
 	 {						\
-	 default:					\
-	   fputs ("e", FILE);				\
+	 case 12:					\
+	 case 8:					\
+	 case 4:					\
+	   if (! FP_REG_P (X)) fputs ("e", FILE);	\
 	 case 2:					\
 	   fputs (hi_name[REGNO (X)], FILE);		\
 	   break;					\
@@ -1813,60 +1812,6 @@
 
 #define RET return ""
 #define AT_SP(mode) (gen_rtx (MEM, (mode), stack_pointer_rtx))
-
-/* Functions in i386.c */
-extern void override_options ();
-extern void order_regs_for_local_alloc ();
-extern void output_op_from_reg ();
-extern void output_to_reg ();
-extern char *singlemove_string ();
-extern char *output_move_double ();
-extern char *output_move_memory ();
-extern char *output_move_pushmem ();
-extern int standard_80387_constant_p ();
-extern char *output_move_const_single ();
-extern int symbolic_operand ();
-extern int call_insn_operand ();
-extern int expander_call_insn_operand ();
-extern int symbolic_reference_mentioned_p ();
-extern void emit_pic_move ();
-extern void function_prologue ();
-extern int simple_386_epilogue ();
-extern void function_epilogue ();
-extern int legitimate_address_p ();
-extern struct rtx_def *legitimize_pic_address ();
-extern struct rtx_def *legitimize_address ();
-extern void print_operand ();
-extern void print_operand_address ();
-extern void notice_update_cc ();
-extern void split_di ();
-extern int binary_387_op ();
-extern int shift_op ();
-extern int VOIDmode_compare_op ();
-extern char *output_387_binary_op ();
-extern char *output_fix_trunc ();
-extern char *output_float_compare ();
-extern char *output_fp_cc0_set ();
-extern void save_386_machine_status ();
-extern void restore_386_machine_status ();
-extern void clear_386_stack_locals ();
-extern struct rtx_def *assign_386_stack_local ();
-
-/* Variables in i386.c */
-extern char *i386_reg_alloc_order;		/* register allocation order */
-extern char *hi_reg_name[];			/* names for 16 bit regs */
-extern char *qi_reg_name[];			/* names for 8 bit regs (low) */
-extern char *qi_high_reg_name[];		/* names for 8 bit regs (high) */
-extern enum reg_class regclass_map[];		/* smalled class containing REGNO */
-extern struct rtx_def *i386_compare_op0;	/* operand 0 for comparisons */
-extern struct rtx_def *i386_compare_op1;	/* operand 1 for comparisons */
-
-/* External variables used */
-extern int optimize;			/* optimization level */
-extern int obey_regdecls;		/* TRUE if stupid register allocation */
-
-/* External functions used */
-extern struct rtx_def *force_operand ();
 
 /*
 Local variables:
diff -r -u -H -N gcc-2.6.3/config/i386/i386.md gcc-i2.6.3/config/i386/i386.md
--- gcc-2.6.3/config/i386/i386.md	Mon Oct 31 16:16:33 1994
+++ gcc-i2.6.3/config/i386/i386.md	Wed Feb 15 23:08:02 1995
@@ -1,7 +1,10 @@
 ;; GCC machine description for Intel X86.
-;; Copyright (C) 1988, 1994 Free Software Foundation, Inc.
+;; Copyright (C) 1988 Free Software Foundation, Inc.
 ;; Mostly by William Schelter.
 
+;; Pentium cpu support and other enhancements by Tevi Devor Intel Corp.
+;; (tevi@iil.intel.com).
+
 ;; This file is part of GNU CC.
 
 ;; GNU CC is free software; you can redistribute it and/or modify
@@ -70,6 +73,36 @@
 ;; actually generating RTL.  The bCOND or sCOND (emitted immediately
 ;; after the tstM or cmp) will actually emit the tstM or cmpM.
 
+;intel1
+(define_attr "type" "fld,integer,fpop,fpdiv"
+  (const_string "integer"))
+
+;; Functional units intel1
+(define_function_unit "fp" 1 0
+ (and (eq_attr "type" "fpop") 
+      (ne (symbol_ref "x86_cpu") (symbol_ref "PROCESSOR_PENTIUM")))
+ 5 5)
+
+(define_function_unit "fp" 1 0
+ (and (eq_attr "type" "fpop") 
+      (eq (symbol_ref "x86_cpu") (symbol_ref "PROCESSOR_PENTIUM")))
+ 3 0)
+
+(define_function_unit "fp" 1 0
+ (eq_attr "type" "fpdiv") 
+ 10 10)
+
+(define_function_unit "fp" 1 0
+ (eq_attr "type" "fld") 
+ 1 0)
+
+(define_function_unit "integer" 1 0
+ (and (eq_attr "type" "integer") 
+      (ne (symbol_ref "x86_cpu") (symbol_ref "PROCESSOR_386")))
+ 2 0)
+
+
+
 (define_insn "tstsi_1"
   [(set (cc0)
 	(match_operand:SI 0 "nonimmediate_operand" "rm"))]
@@ -142,104 +175,105 @@
   DONE;
 }")
 
-(define_insn "tstsf_cc"
-  [(set (cc0)
-	(match_operand:SF 0 "register_operand" "f"))
-   (clobber (match_scratch:HI 1 "=a"))]
-  "TARGET_80387 && ! TARGET_IEEE_FP"
-  "*
-{
-  if (! STACK_TOP_P (operands[0]))
-    abort ();
-
-  output_asm_insn (\"ftst\", operands);
-
-  if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
-    output_asm_insn (AS1 (fstp,%y0), operands);
-
-  return output_fp_cc0_set (insn);
-}")
-
-;; Don't generate tstsf if generating IEEE code, since the `ftst' opcode
-;; isn't IEEE compliant.
-
-(define_expand "tstsf"
-  [(parallel [(set (cc0)
-		   (match_operand:SF 0 "register_operand" ""))
-	      (clobber (match_scratch:HI 1 ""))])]
-  "TARGET_80387 && ! TARGET_IEEE_FP"
-  "
-{
-  i386_compare_gen = gen_tstsf_cc;
-  i386_compare_op0 = operands[0];
-  DONE;
-}")
-
-(define_insn "tstdf_cc"
-  [(set (cc0)
-	(match_operand:DF 0 "register_operand" "f"))
-   (clobber (match_scratch:HI 1 "=a"))]
-  "TARGET_80387 && ! TARGET_IEEE_FP"
-  "*
-{
-  if (! STACK_TOP_P (operands[0]))
-    abort ();
-
-  output_asm_insn (\"ftst\", operands);
-
-  if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
-    output_asm_insn (AS1 (fstp,%y0), operands);
-
-  return output_fp_cc0_set (insn);
-}")
-
-;; Don't generate tstdf if generating IEEE code, since the `ftst' opcode
-;; isn't IEEE compliant.
-
-(define_expand "tstdf"
-  [(parallel [(set (cc0)
-		   (match_operand:DF 0 "register_operand" ""))
-	      (clobber (match_scratch:HI 1 ""))])]
-  "TARGET_80387 && ! TARGET_IEEE_FP"
-  "
-{
-  i386_compare_gen = gen_tstdf_cc;
-  i386_compare_op0 = operands[0];
-  DONE;
-}")
-
-(define_insn "tstxf_cc"
-  [(set (cc0)
-	(match_operand:XF 0 "register_operand" "f"))
-   (clobber (match_scratch:HI 1 "=a"))]
-  "TARGET_80387 && ! TARGET_IEEE_FP"
-  "*
-{
-  if (! STACK_TOP_P (operands[0]))
-    abort ();
-
-  output_asm_insn (\"ftst\", operands);
-
-  if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
-    output_asm_insn (AS1 (fstp,%y0), operands);
-
-  return output_fp_cc0_set (insn);
-}")
-
-;; Don't generate tstdf if generating IEEE code, since the `ftst' opcode
-;; isn't IEEE compliant.
-
-(define_expand "tstxf"
-  [(parallel [(set (cc0)
-		   (match_operand:XF 0 "register_operand" ""))
-	      (clobber (match_scratch:HI 1 ""))])]
-  "TARGET_80387 && ! TARGET_IEEE_FP"
-  "
-{
-  i386_compare_gen = gen_tstxf_cc;
-  i386_compare_op0 = operands[0];
-  DONE;
-}")
+;; intel1
+;;(define_insn "tstsf_cc"
+;;  [(set (cc0)
+;;	(match_operand:SF 0 "register_operand" "f"))
+;;   (clobber (match_scratch:HI 1 "=a"))]
+;;  "TARGET_80387 && ! TARGET_IEEE_FP"
+;;  "*
+;;{
+;;  if (! STACK_TOP_P (operands[0]))
+;;    abort ();
+;;
+;;  output_asm_insn (\"ftst\", operands);
+;;
+;;  if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
+;;    output_asm_insn (AS1 (fstp,%y0), operands);
+;;
+;;  return (char *) output_fp_cc0_set (insn);
+;;}")
+;;
+;;;; Don't generate tstsf if generating IEEE code, since the `ftst' opcode
+;;;; isn't IEEE compliant.
+;;
+;;(define_expand "tstsf"
+;;  [(parallel [(set (cc0)
+;;		   (match_operand:SF 0 "register_operand" ""))
+;;	      (clobber (match_scratch:HI 1 ""))])]
+;;  "TARGET_80387 && ! TARGET_IEEE_FP"
+;;  "
+;;{
+;;  i386_compare_gen = gen_tstsf_cc;
+;;  i386_compare_op0 = operands[0];
+;;  DONE;
+;;}")
+;;
+;;(define_insn "tstdf_cc"
+;;  [(set (cc0)
+;;	(match_operand:DF 0 "register_operand" "f"))
+;;   (clobber (match_scratch:HI 1 "=a"))]
+;;  "TARGET_80387 && ! TARGET_IEEE_FP"
+;;  "*
+;;{
+;;  if (! STACK_TOP_P (operands[0]))
+;;    abort ();
+;;
+;;  output_asm_insn (\"ftst\", operands);
+;;
+;;  if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
+;;    output_asm_insn (AS1 (fstp,%y0), operands);
+;;
+;;  return (char *) output_fp_cc0_set (insn);
+;;}")
+;;
+;;;; Don't generate tstdf if generating IEEE code, since the `ftst' opcode
+;;;; isn't IEEE compliant.
+;;
+;;(define_expand "tstdf"
+;;  [(parallel [(set (cc0)
+;;		   (match_operand:DF 0 "register_operand" ""))
+;;	      (clobber (match_scratch:HI 1 ""))])]
+;;  "TARGET_80387 && ! TARGET_IEEE_FP"
+;;  "
+;;{
+;;  i386_compare_gen = gen_tstdf_cc;
+;;  i386_compare_op0 = operands[0];
+;;  DONE;
+;;}")
+
+;;(define_insn "tstxf_cc"
+;;  [(set (cc0)
+;;      (match_operand:XF 0 "register_operand" "f"))
+;;   (clobber (match_scratch:HI 1 "=a"))]
+;;  "TARGET_80387 && ! TARGET_IEEE_FP"
+;;  "*
+;;{
+;;  if (! STACK_TOP_P (operands[0]))
+;;    abort ();
+;;
+;;  output_asm_insn (\"ftst\", operands);
+;;
+;;  if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
+;;    output_asm_insn (AS1 (fstp,%y0), operands);
+;;
+;;  return (char *) output_fp_cc0_set (insn);
+;;}")
+;;
+;;;; Don't generate tstdf if generating IEEE code, since the `ftst' opcode
+;;;; isn't IEEE compliant.
+;;
+;;(define_expand "tstxf"
+;;  [(parallel [(set (cc0)
+;;                 (match_operand:XF 0 "register_operand" ""))
+;;            (clobber (match_scratch:HI 1 ""))])]
+;;  "TARGET_80387 && ! TARGET_IEEE_FP"
+;;  "
+;;{
+;;  i386_compare_gen = gen_tstxf_cc;
+;;  i386_compare_op0 = operands[0];
+;;  DONE;
+;;}")
 
 ;;- compare instructions.  See comments above tstM patterns about
 ;;  expansion of these insns.
@@ -341,55 +375,56 @@
 ;; SFmode, there is the normal insn, and an insn where the second operand
 ;; is converted to the desired mode.
 
+;;intel1 operand 1 and 2 changed from nonimmediate_operand to general_operand
 (define_insn ""
   [(set (cc0)
 	(match_operator 2 "VOIDmode_compare_op"
-			[(match_operand:XF 0 "nonimmediate_operand" "f")
-			 (match_operand:XF 1 "nonimmediate_operand" "f")]))
+			[(match_operand:XF 0 "general_operand" "f")
+			 (match_operand:XF 1 "general_operand" "f")]))
    (clobber (match_scratch:HI 3 "=a"))]
   "TARGET_80387
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
-  "* return output_float_compare (insn, operands);")
+  "* return (char *) output_float_compare (insn, operands);")
 
 (define_insn ""
   [(set (cc0)
 	(match_operator 2 "VOIDmode_compare_op"
 			[(match_operand:XF 0 "register_operand" "f")
 			 (float:XF
-			  (match_operand:SI 1 "nonimmediate_operand" "rm"))]))
+			  (match_operand:SI 1 "general_operand" "rm"))]))
    (clobber (match_scratch:HI 3 "=a"))]
   "TARGET_80387"
-  "* return output_float_compare (insn, operands);")
+  "* return (char *) output_float_compare (insn, operands);")
 
 (define_insn ""
   [(set (cc0)
 	(match_operator 2 "VOIDmode_compare_op"
 			[(float:XF
-			  (match_operand:SI 0 "nonimmediate_operand" "rm"))
+			  (match_operand:SI 0 "general_operand" "rm"))
 			 (match_operand:XF 1 "register_operand" "f")]))
    (clobber (match_scratch:HI 3 "=a"))]
   "TARGET_80387"
-  "* return output_float_compare (insn, operands);")
+  "* return (char *) output_float_compare (insn, operands);")
 
 (define_insn ""
   [(set (cc0)
 	(match_operator 2 "VOIDmode_compare_op"
 			[(match_operand:XF 0 "register_operand" "f")
 			 (float_extend:XF
-			  (match_operand:DF 1 "nonimmediate_operand" "fm"))]))
+			  (match_operand:DF 1 "general_operand" "fm"))]))
    (clobber (match_scratch:HI 3 "=a"))]
   "TARGET_80387"
-  "* return output_float_compare (insn, operands);")
+  "* return (char *) output_float_compare (insn, operands);")
 
 (define_insn ""
   [(set (cc0)
 	(match_operator 2 "VOIDmode_compare_op"
 			[(match_operand:XF 0 "register_operand" "f")
 			 (float_extend:XF
-			  (match_operand:SF 1 "nonimmediate_operand" "fm"))]))
+			  (match_operand:SF 1 "general_operand" "fm"))]))
    (clobber (match_scratch:HI 3 "=a"))]
   "TARGET_80387"
-  "* return output_float_compare (insn, operands);")
+  "* return (char *) output_float_compare (insn, operands);")
 
 (define_insn ""
   [(set (cc0)
@@ -397,17 +432,17 @@
 			(match_operand:XF 1 "register_operand" "f")))
    (clobber (match_scratch:HI 2 "=a"))]
   "TARGET_80387"
-  "* return output_float_compare (insn, operands);")
+  "* return (char *) output_float_compare (insn, operands);")
 
 (define_insn ""
   [(set (cc0)
 	(match_operator 2 "VOIDmode_compare_op"
-			[(match_operand:DF 0 "nonimmediate_operand" "f,fm")
-			 (match_operand:DF 1 "nonimmediate_operand" "fm,f")]))
+			[(match_operand:DF 0 "general_operand" "f,fm")
+			 (match_operand:DF 1 "general_operand" "fm,f")]))
    (clobber (match_scratch:HI 3 "=a,a"))]
   "TARGET_80387
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
-  "* return output_float_compare (insn, operands);")
+  "* return (char *) output_float_compare (insn, operands);")
 
 (define_insn ""
   [(set (cc0)
@@ -417,7 +452,7 @@
 			  (match_operand:SI 1 "nonimmediate_operand" "rm"))]))
    (clobber (match_scratch:HI 3 "=a"))]
   "TARGET_80387"
-  "* return output_float_compare (insn, operands);")
+  "* return (char *) output_float_compare (insn, operands);")
 
 (define_insn ""
   [(set (cc0)
@@ -427,7 +462,7 @@
 			 (match_operand:DF 1 "register_operand" "f")]))
    (clobber (match_scratch:HI 3 "=a"))]
   "TARGET_80387"
-  "* return output_float_compare (insn, operands);")
+  "* return (char *) output_float_compare (insn, operands);")
 
 (define_insn ""
   [(set (cc0)
@@ -437,7 +472,7 @@
 			  (match_operand:SF 1 "nonimmediate_operand" "fm"))]))
    (clobber (match_scratch:HI 3 "=a"))]
   "TARGET_80387"
-  "* return output_float_compare (insn, operands);")
+  "* return (char *) output_float_compare (insn, operands);")
 
 (define_insn ""
   [(set (cc0)
@@ -447,7 +482,18 @@
 			 (match_operand:DF 1 "register_operand" "f")]))
    (clobber (match_scratch:HI 3 "=a"))]
   "TARGET_80387"
-  "* return output_float_compare (insn, operands);")
+  "* return (char *) output_float_compare (insn, operands);")
+
+;;intel1 
+(define_insn ""
+  [(set (cc0)
+	(match_operator 2 "VOIDmode_compare_op"
+			[(float_extend:DF
+			  (match_operand:SF 0 "register_operand" "f"))
+			 (match_operand:DF 1 "general_operand" "fm")]))
+   (clobber (match_scratch:HI 3 "=a"))]
+  "TARGET_80387"
+  "* return (char *) output_float_compare (insn, operands);")
 
 (define_insn ""
   [(set (cc0)
@@ -455,7 +501,7 @@
 			(match_operand:DF 1 "register_operand" "f")))
    (clobber (match_scratch:HI 2 "=a"))]
   "TARGET_80387"
-  "* return output_float_compare (insn, operands);")
+  "* return (char *) output_float_compare (insn, operands);")
 
 ;; These two insns will never be generated by combine due to the mode of
 ;; the COMPARE.
@@ -466,7 +512,7 @@
 ;			 (match_operand:SF 1 "register_operand" "f"))))
 ;   (clobber (match_scratch:HI 2 "=a"))]
 ;  "TARGET_80387"
-;  "* return output_float_compare (insn, operands);")
+;  "* return (char *) output_float_compare (insn, operands);")
 ;
 ;(define_insn ""
 ;  [(set (cc0)
@@ -475,17 +521,18 @@
 ;			(match_operand:DF 1 "register_operand" "f")))
 ;   (clobber (match_scratch:HI 2 "=a"))]
 ;  "TARGET_80387"
-;  "* return output_float_compare (insn, operands);")
+;  "* return (char *) output_float_compare (insn, operands);")
 
+;;intel1 operand 1 changed from nonimmediate_operand to general_operand
 (define_insn "cmpsf_cc_1"
   [(set (cc0)
 	(match_operator 2 "VOIDmode_compare_op"
 			[(match_operand:SF 0 "nonimmediate_operand" "f,fm")
-			 (match_operand:SF 1 "nonimmediate_operand" "fm,f")]))
+			 (match_operand:SF 1 "general_operand" "fm,f")]))
    (clobber (match_scratch:HI 3 "=a,a"))]
   "TARGET_80387
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
-  "* return output_float_compare (insn, operands);")
+  "* return (char *) output_float_compare (insn, operands);")
 
 (define_insn ""
   [(set (cc0)
@@ -495,7 +542,7 @@
 			  (match_operand:SI 1 "nonimmediate_operand" "rm"))]))
    (clobber (match_scratch:HI 3 "=a"))]
   "TARGET_80387"
-  "* return output_float_compare (insn, operands);")
+  "* return (char *) output_float_compare (insn, operands);")
 
 (define_insn ""
   [(set (cc0)
@@ -505,7 +552,7 @@
 			 (match_operand:SF 1 "register_operand" "f")]))
    (clobber (match_scratch:HI 3 "=a"))]
   "TARGET_80387"
-  "* return output_float_compare (insn, operands);")
+  "* return (char *) output_float_compare (insn, operands);")
 
 (define_insn ""
   [(set (cc0)
@@ -513,12 +560,12 @@
 			(match_operand:SF 1 "register_operand" "f")))
    (clobber (match_scratch:HI 2 "=a"))]
   "TARGET_80387"
-  "* return output_float_compare (insn, operands);")
+  "* return (char *) output_float_compare (insn, operands);")
 
 (define_expand "cmpxf"
   [(set (cc0)
-	(compare (match_operand:XF 0 "register_operand" "")
-		 (match_operand:XF 1 "nonimmediate_operand" "")))]
+      (compare (match_operand:XF 0 "register_operand" "")
+               (match_operand:XF 1 "nonimmediate_operand" "")))]
   "TARGET_80387"
   "
 {
@@ -529,10 +576,11 @@
   DONE;
 }")
 
+;;intel1 operand 1 changed from nonimmediate_operand to general_operand
 (define_expand "cmpdf"
   [(set (cc0)
 	(compare (match_operand:DF 0 "register_operand" "")
-		 (match_operand:DF 1 "nonimmediate_operand" "")))]
+		 (match_operand:DF 1 "general_operand" "")))]
   "TARGET_80387"
   "
 {
@@ -543,10 +591,11 @@
   DONE;
 }")
 
+;;intel1 operand 1 changed from nonimmediate_operand to general_operand
 (define_expand "cmpsf"
   [(set (cc0)
 	(compare (match_operand:SF 0 "register_operand" "")
-		 (match_operand:SF 1 "nonimmediate_operand" "")))]
+		 (match_operand:SF 1 "general_operand" "")))]
   "TARGET_80387"
   "
 {
@@ -559,17 +608,17 @@
 
 (define_expand "cmpxf_cc"
   [(parallel [(set (cc0)
-		   (compare (match_operand:XF 0 "register_operand" "")
-			    (match_operand:XF 1 "register_operand" "")))
-	      (clobber (match_scratch:HI 2 ""))])]
+                 (compare (match_operand:XF 0 "register_operand" "")
+                          (match_operand:XF 1 "register_operand" "")))
+            (clobber (match_scratch:HI 2 ""))])]
   "TARGET_80387"
   "")
 
 (define_expand "cmpxf_ccfpeq"
   [(parallel [(set (cc0)
-		   (compare:CCFPEQ (match_operand:XF 0 "register_operand" "")
-				   (match_operand:XF 1 "register_operand" "")))
-	      (clobber (match_scratch:HI 2 ""))])]
+                 (compare:CCFPEQ (match_operand:XF 0 "register_operand" "")
+                                 (match_operand:XF 1 "register_operand" "")))
+            (clobber (match_scratch:HI 2 ""))])]
   "TARGET_80387"
   "
 {
@@ -740,7 +789,7 @@
 (define_insn ""
   [(set (match_operand:SI 0 "push_operand" "=<")
 	(match_operand:SI 1 "general_operand" "g"))]
-  "TARGET_386"
+  "! TARGET_486"
   "push%L0 %1")
 
 ;; On a 486, it is faster to move MEM to a REG and then push, rather than
@@ -748,14 +797,8 @@
 
 (define_insn ""
   [(set (match_operand:SI 0 "push_operand" "=<")
-	(match_operand:SI 1 "nonmemory_operand" "ri"))]
-  "!TARGET_386 && TARGET_MOVE"
-  "push%L0 %1")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "push_operand" "=<")
 	(match_operand:SI 1 "general_operand" "ri"))]
-  "!TARGET_386 && !TARGET_MOVE"
+  "TARGET_486"
   "push%L0 %1")
 
 ;; General case of fullword move.
@@ -773,15 +816,6 @@
 
   if (flag_pic && SYMBOLIC_CONST (operands[1]))
     emit_pic_move (operands, SImode);
-
-  /* Don't generate memory->memory moves, go through a register */
-  else if (TARGET_MOVE
-	   && (reload_in_progress | reload_completed) == 0
-	   && GET_CODE (operands[0]) == MEM
-	   && GET_CODE (operands[1]) == MEM)
-    {
-      operands[1] = force_reg (SImode, operands[1]);
-    }
 }")
 
 ;; On i486, incl reg is faster than movl $1,reg.
@@ -789,7 +823,7 @@
 (define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=g,r")
 	(match_operand:SI 1 "general_operand" "ri,m"))]
-  "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
+  ""
   "*
 {
   rtx link;
@@ -808,52 +842,21 @@
     /* Fastest way to change a 0 to a 1.  */
     return AS1 (inc%L0,%0);
 
-  if (flag_pic && SYMBOLIC_CONST (operands[1]))
-    return AS2 (lea%L0,%a1,%0);
-
   return AS2 (mov%L0,%1,%0);
 }")
 
 (define_insn ""
   [(set (match_operand:HI 0 "push_operand" "=<")
 	(match_operand:HI 1 "general_operand" "g"))]
-  "TARGET_386"
-  "push%W0 %1")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "push_operand" "=<")
-	(match_operand:HI 1 "nonmemory_operand" "ri"))]
-  "!TARGET_386 && TARGET_MOVE"
-  "push%W0 %1")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "push_operand" "=<")
-	(match_operand:HI 1 "general_operand" "ri"))]
-  "!TARGET_386 && !TARGET_MOVE"
+  ""
   "push%W0 %1")
 
 ;; On i486, an incl and movl are both faster than incw and movw.
 
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Don't generate memory->memory moves, go through a register */
-  if (TARGET_MOVE
-      && (reload_in_progress | reload_completed) == 0
-      && GET_CODE (operands[0]) == MEM
-      && GET_CODE (operands[1]) == MEM)
-    {
-      operands[1] = force_reg (HImode, operands[1]);
-    }
-}")
-
-(define_insn ""
+(define_insn "movhi"
   [(set (match_operand:HI 0 "general_operand" "=g,r")
 	(match_operand:HI 1 "general_operand" "ri,m"))]
-  "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
+  ""
   "*
 {
   rtx link;
@@ -883,26 +886,10 @@
   return AS2 (mov%W0,%1,%0);
 }")
 
-(define_expand "movstricthi"
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" ""))
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Don't generate memory->memory moves, go through a register */
-  if (TARGET_MOVE
-      && (reload_in_progress | reload_completed) == 0
-      && GET_CODE (operands[0]) == MEM
-      && GET_CODE (operands[1]) == MEM)
-    {
-      operands[1] = force_reg (HImode, operands[1]);
-    }
-}")
-
-(define_insn ""
+(define_insn "movstricthi"
   [(set (strict_low_part (match_operand:HI 0 "general_operand" "+g,r"))
 	(match_operand:HI 1 "general_operand" "ri,m"))]
-  "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
+  ""
   "*
 {
   rtx link;
@@ -930,24 +917,8 @@
 ;; the amount pushed up to a halfword.
 (define_insn ""
   [(set (match_operand:QI 0 "push_operand" "=<")
-	(match_operand:QI 1 "immediate_operand" "n"))]
+	(match_operand:QI 1 "general_operand" "q"))]
   ""
-  "* return AS1 (push%W0,%1);")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "push_operand" "=<")
-	(match_operand:QI 1 "nonimmediate_operand" "q"))]
-  "!TARGET_MOVE"
-  "*
-{
-  operands[1] = gen_rtx (REG, HImode, REGNO (operands[1]));
-  return AS1 (push%W0,%1);
-}")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "push_operand" "=<")
-	(match_operand:QI 1 "register_operand" "q"))]
-  "TARGET_MOVE"
   "*
 {
   operands[1] = gen_rtx (REG, HImode, REGNO (operands[1]));
@@ -959,26 +930,10 @@
 ;; ??? Do a recognizer for zero_extract that looks just like this, but reads
 ;; or writes %ah, %bh, %ch, %dh.
 
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Don't generate memory->memory moves, go through a register */
-  if (TARGET_MOVE
-      && (reload_in_progress | reload_completed) == 0
-      && GET_CODE (operands[0]) == MEM
-      && GET_CODE (operands[1]) == MEM)
-    {
-      operands[1] = force_reg (QImode, operands[1]);
-    }
-}")
-
-(define_insn ""
+(define_insn "movqi"
   [(set (match_operand:QI 0 "general_operand" "=q,*r,qm")
 	(match_operand:QI 1 "general_operand" "*g,q,qn"))]
-  "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
+  ""
   "*
 {
   rtx link;
@@ -1013,26 +968,10 @@
 ;; If operands[1] is a constant, then an andl/orl sequence would be
 ;; faster.
 
-(define_expand "movstrictqi"
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" ""))
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Don't generate memory->memory moves, go through a register */
-  if (TARGET_MOVE
-      && (reload_in_progress | reload_completed) == 0
-      && GET_CODE (operands[0]) == MEM
-      && GET_CODE (operands[1]) == MEM)
-    {
-      operands[1] = force_reg (QImode, operands[1]);
-    }
-}")
-
-(define_insn ""
+(define_insn "movstrictqi"
   [(set (strict_low_part (match_operand:QI 0 "general_operand" "+qm,q"))
 	(match_operand:QI 1 "general_operand" "*qn,m"))]
-  "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
+  ""
   "*
 {
   rtx link;
@@ -1061,43 +1000,10 @@
   return AS2 (mov%B0,%1,%0);
 }")
 
-(define_expand "movsf"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(match_operand:SF 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Special case memory->memory moves and pushes */
-  if (TARGET_MOVE
-      && (reload_in_progress | reload_completed) == 0
-      && GET_CODE (operands[0]) == MEM
-      && (GET_CODE (operands[1]) == MEM || push_operand (operands[0], SFmode)))
-    {
-      rtx (*genfunc) PROTO((rtx, rtx)) = (push_operand (operands[0], SFmode))
-						? gen_movsf_push
-						: gen_movsf_mem;
-
-      emit_insn ((*genfunc) (operands[0], operands[1]));
-      DONE;
-    }
-
-  /* If we are loading a floating point constant that isn't 0 or 1 into a register,
-     indicate we need the pic register loaded.  This could be optimized into stores
-     of constants if the target eventually moves to memory, but better safe than
-     sorry.  */
-  if (flag_pic
-      && GET_CODE (operands[0]) != MEM
-      && GET_CODE (operands[1]) == CONST_DOUBLE
-      && !standard_80387_constant_p (operands[1]))
-    {
-      current_function_uses_pic_offset_table = 1;
-    }
-}")
-
-(define_insn "movsf_push_nomove"
+(define_insn ""
   [(set (match_operand:SF 0 "push_operand" "=<,<")
 	(match_operand:SF 1 "general_operand" "gF,f"))]
-  "!TARGET_MOVE"
+  ""
   "*
 {
   if (STACK_REG_P (operands[1]))
@@ -1122,61 +1028,24 @@
   return AS1 (push%L1,%1);
 }")
 
-(define_insn "movsf_push"
-  [(set (match_operand:SF 0 "push_operand" "=<,<,<,<")
-	(match_operand:SF 1 "general_operand" "rF,f,m,m"))
-   (clobber (match_scratch:SI 2 "=X,X,r,X"))]
-  ""
-  "*
-{
-  if (STACK_REG_P (operands[1]))
-    {
-      rtx xops[3];
-
-      if (! STACK_TOP_P (operands[1]))
-        abort ();
-
-      xops[0] = AT_SP (SFmode);
-      xops[1] = GEN_INT (4);
-      xops[2] = stack_pointer_rtx;
-
-      output_asm_insn (AS2 (sub%L2,%1,%2), xops);
-
-      if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
-        output_asm_insn (AS1 (fstp%S0,%0), xops);
-      else
-        output_asm_insn (AS1 (fst%S0,%0), xops);
-      RET;
-    }
-
-  else if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != REG)
-    return AS1 (push%L1,%1);
-
-  else
-    {
-      output_asm_insn (AS2 (mov%L2,%1,%2), operands);
-      return AS1 (push%L2,%2);
-    }
-}")
+;; Allow MEM-MEM moves before reload.  The reload class for such a
+;; move will be ALL_REGS.  PREFERRED_RELOAD_CLASS will narrow this to
+;; GENERAL_REGS.  For the purposes of regclass, prefer FLOAT_REGS.
 
-;; Special memory<->memory pattern that combine will recreate from the
-;; moves to pseudos.
-(define_insn "movsf_mem"
-  [(set (match_operand:SF 0 "memory_operand" "=m")
-	(match_operand:SF 1 "memory_operand" "m"))
-   (clobber (match_scratch:SI 2 "=&r"))]
+;;intel1
+(define_insn "memmovsf"
+  [(set (match_operand:SF 0 "memory_operand" "=r,m")
+	(match_operand:SF 1 "memory_operand" "m,r"))]
   ""
   "*
 {
-  output_asm_insn (AS2 (mov%L2,%1,%2), operands);
-  return AS2 (mov%L0,%2,%0);
+  return (char *) singlemove_string (operands);
 }")
 
-;; For the purposes of regclass, prefer FLOAT_REGS.
-(define_insn "movsf_normal"
+(define_insn "movsf"
   [(set (match_operand:SF 0 "general_operand" "=*rfm,*rf,f,!*rm")
 	(match_operand:SF 1 "general_operand" "*rf,*rfm,fG,fF"))]
-  "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
+  ""
   "*
 {
   int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
@@ -1218,67 +1087,21 @@
   /* Handle other kinds of reads to the 387 */
 
   if (STACK_TOP_P (operands[0]) && GET_CODE (operands[1]) == CONST_DOUBLE)
-    return output_move_const_single (operands);
+    return (char *) output_move_const_single (operands);
 
   if (STACK_TOP_P (operands[0]))
     return AS1 (fld%z1,%y1);
 
   /* Handle all SFmode moves not involving the 387 */
 
-  return singlemove_string (operands);
-}")
-
-(define_insn "swapsf"
-  [(set (match_operand:SF 0 "register_operand" "f")
-	(match_operand:SF 1 "register_operand" "f"))
-   (set (match_dup 1)
-	(match_dup 0))]
-  ""
-  "*
-{
-  if (STACK_TOP_P (operands[0]))
-    return AS1 (fxch,%1);
-  else
-    return AS1 (fxch,%0);
-}")
-
-(define_expand "movdf"
-  [(set (match_operand:DF 0 "general_operand" "")
-	(match_operand:DF 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Special case memory->memory moves and pushes */
-  if (TARGET_MOVE
-      && (reload_in_progress | reload_completed) == 0
-      && GET_CODE (operands[0]) == MEM
-      && (GET_CODE (operands[1]) == MEM || push_operand (operands[0], DFmode)))
-    {
-      rtx (*genfunc) PROTO((rtx, rtx)) = (push_operand (operands[0], DFmode))
-						? gen_movdf_push
-						: gen_movdf_mem;
-
-      emit_insn ((*genfunc) (operands[0], operands[1]));
-      DONE;
-    }
-
-  /* If we are loading a floating point constant that isn't 0 or 1 into a register,
-     indicate we need the pic register loaded.  This could be optimized into stores
-     of constants if the target eventually moves to memory, but better safe than
-     sorry.  */
-  if (flag_pic
-      && GET_CODE (operands[0]) != MEM
-      && GET_CODE (operands[1]) == CONST_DOUBLE
-      && !standard_80387_constant_p (operands[1]))
-    {
-      current_function_uses_pic_offset_table = 1;
-    }
-}")
+  return (char *) singlemove_string (operands);
+}"[(set_attr "type" "fld")])
 
-(define_insn "movdf_push_nomove"
+;;should change to handle the memory operands[1] without doing df push..
+(define_insn ""
   [(set (match_operand:DF 0 "push_operand" "=<,<")
 	(match_operand:DF 1 "general_operand" "gF,f"))]
-  "!TARGET_MOVE"
+  ""
   "*
 {
   if (STACK_REG_P (operands[1]))
@@ -1299,55 +1122,41 @@
       RET;
     }
   else
-    return output_move_double (operands);
+    return (char *) output_move_double (operands);
 }")
 
-(define_insn "movdf_push"
-  [(set (match_operand:DF 0 "push_operand" "=<,<,<,<,<")
-	(match_operand:DF 1 "general_operand" "rF,f,o,o,o"))
-   (clobber (match_scratch:SI 2 "=X,X,&r,&r,X"))
-   (clobber (match_scratch:SI 3 "=X,X,&r,X,X"))]
+(define_insn "swapdf"
+  [(set (match_operand:DF 0 "register_operand" "f")
+	(match_operand:DF 1 "register_operand" "f"))
+   (set (match_dup 1)
+	(match_dup 0))]
   ""
   "*
 {
-  if (STACK_REG_P (operands[1]))
-    {
-      rtx xops[3];
-
-      xops[0] = AT_SP (SFmode);
-      xops[1] = GEN_INT (8);
-      xops[2] = stack_pointer_rtx;
-
-      output_asm_insn (AS2 (sub%L2,%1,%2), xops);
-
-      if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
-        output_asm_insn (AS1 (fstp%Q0,%0), xops);
-      else
-        output_asm_insn (AS1 (fst%Q0,%0), xops);
-
-      RET;
-    }
-
-  else if (GET_CODE (operands[1]) != MEM)
-    return output_move_double (operands);
-
+  if (STACK_TOP_P (operands[0]))
+    return AS1 (fxch,%1);
   else
-    return output_move_pushmem (operands, insn, GET_MODE_SIZE (DFmode), 2, 4);
+    return AS1 (fxch,%0);
 }")
 
-(define_insn "movdf_mem"
-  [(set (match_operand:DF 0 "memory_operand" "=o,o")
-	(match_operand:DF 1 "memory_operand" "o,o"))
-   (clobber (match_scratch:SI 2 "=&r,&r"))
-   (clobber (match_scratch:SI 3 "=&r,X"))]
+;; Allow MEM-MEM moves before reload.  The reload class for such a
+;; move will be ALL_REGS.  PREFERRED_RELOAD_CLASS will narrow this to
+;; GENERAL_REGS.  For the purposes of regclass, prefer FLOAT_REGS.
+
+;;intel1
+(define_insn "memmovdf"
+  [(set (match_operand:DF 0 "memory_operand" "=r,m")
+	(match_operand:DF 1 "memory_operand" "m,r"))]
   ""
-  "* return output_move_memory (operands, insn, GET_MODE_SIZE (DFmode), 2, 4);")
+  "*
+{
+  return (char *) output_move_double (operands);
+}")
 
-;; For the purposes of regclass, prefer FLOAT_REGS.
-(define_insn "movdf_normal"
-  [(set (match_operand:DF 0 "general_operand" "=f,fm,!*rf,!*rm")
-	(match_operand:DF 1 "general_operand" "fmG,f,*rfm,*rfF"))]
-  "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
+(define_insn "movdf"
+  [(set (match_operand:DF 0 "general_operand" "=*rfm,*rf,f,!*rm")
+	(match_operand:DF 1 "general_operand" "*rf,*rfm,fG,fF"))]
+  ""
   "*
 {
   int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
@@ -1389,68 +1198,20 @@
   /* Handle other kinds of reads to the 387 */
 
   if (STACK_TOP_P (operands[0]) && GET_CODE (operands[1]) == CONST_DOUBLE)
-    return output_move_const_single (operands);
+    return (char *) output_move_const_single (operands);
 
   if (STACK_TOP_P (operands[0]))
     return AS1 (fld%z1,%y1);
 
   /* Handle all DFmode moves not involving the 387 */
 
-  return output_move_double (operands);
-}")
+  return (char *) output_move_double (operands);
+}"[(set_attr "type" "fld")])
 
-(define_insn "swapdf"
-  [(set (match_operand:DF 0 "register_operand" "f")
-	(match_operand:DF 1 "register_operand" "f"))
-   (set (match_dup 1)
-	(match_dup 0))]
-  ""
-  "*
-{
-  if (STACK_TOP_P (operands[0]))
-    return AS1 (fxch,%1);
-  else
-    return AS1 (fxch,%0);
-}")
-
-(define_expand "movxf"
-  [(set (match_operand:XF 0 "general_operand" "")
-	(match_operand:XF 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Special case memory->memory moves and pushes */
-  if (TARGET_MOVE
-      && (reload_in_progress | reload_completed) == 0
-      && GET_CODE (operands[0]) == MEM
-      && (GET_CODE (operands[1]) == MEM || push_operand (operands[0], XFmode)))
-    {
-      rtx (*genfunc) PROTO((rtx, rtx)) = (push_operand (operands[0], XFmode))
-						? gen_movxf_push
-						: gen_movxf_mem;
-
-      emit_insn ((*genfunc) (operands[0], operands[1]));
-      DONE;
-    }
-
-  /* If we are loading a floating point constant that isn't 0 or 1 into a register,
-     indicate we need the pic register loaded.  This could be optimized into stores
-     of constants if the target eventually moves to memory, but better safe than
-     sorry.  */
-  if (flag_pic
-      && GET_CODE (operands[0]) != MEM
-      && GET_CODE (operands[1]) == CONST_DOUBLE
-      && !standard_80387_constant_p (operands[1]))
-    {
-      current_function_uses_pic_offset_table = 1;
-    }
-}")
-
-
-(define_insn "movxf_push_nomove"
+(define_insn ""
   [(set (match_operand:XF 0 "push_operand" "=<,<")
  	(match_operand:XF 1 "general_operand" "gF,f"))]
-  "!TARGET_MOVE"
+  ""
   "*
 {
   if (STACK_REG_P (operands[1]))
@@ -1469,53 +1230,29 @@
       RET;
     }
   else
-    return output_move_double (operands);
+    return (char *) output_move_double (operands);
  }")
 
-(define_insn "movxf_push"
-  [(set (match_operand:XF 0 "push_operand" "=<,<,<,<,<")
- 	(match_operand:XF 1 "general_operand" "rF,f,o,o,o"))
-   (clobber (match_scratch:SI 2 "=X,X,&r,&r,X"))
-   (clobber (match_scratch:SI 3 "=X,X,&r,X,X"))]
+(define_insn "swapxf"
+  [(set (match_operand:XF 0 "register_operand" "f")
+	(match_operand:XF 1 "register_operand" "f"))
+   (set (match_dup 1)
+	(match_dup 0))]
   ""
   "*
 {
-  if (STACK_REG_P (operands[1]))
-    {
-      rtx xops[3];
-
-      xops[0] = AT_SP (SFmode);
-      xops[1] = GEN_INT (12);
-      xops[2] = stack_pointer_rtx;
-
-      output_asm_insn (AS2 (sub%L2,%1,%2), xops);
-      output_asm_insn (AS1 (fstp%T0,%0), xops);
-      if (! find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
-	output_asm_insn (AS1 (fld%T0,%0), xops);
-
-      RET;
-    }
-
-  else if (GET_CODE (operands[1]) != MEM
-	   || GET_CODE (operands[2]) != REG)
-    return output_move_double (operands);
-
+  if (STACK_TOP_P (operands[0]))
+    return AS1 (fxch,%1);
   else
-    return output_move_pushmem (operands, insn, GET_MODE_SIZE (XFmode), 2, 4);
+    return AS1 (fxch,%0);
 }")
 
-(define_insn "movxf_mem"
-  [(set (match_operand:XF 0 "memory_operand" "=o,o")
-	(match_operand:XF 1 "memory_operand" "o,o"))
-   (clobber (match_scratch:SI 2 "=&r,&r"))
-   (clobber (match_scratch:SI 3 "=&r,X"))]
-  ""
-  "* return output_move_memory (operands, insn, GET_MODE_SIZE (XFmode), 2, 4);")
-
-(define_insn "movxf_normal"
+(define_insn "movxf"
   [(set (match_operand:XF 0 "general_operand" "=f,fm,!*rf,!*rm")
 	(match_operand:XF 1 "general_operand" "fmG,f,*rfm,*rfF"))]
-  "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
+;;  [(set (match_operand:XF 0 "general_operand" "=*rf,*rfm,f,!*rm")
+;;	(match_operand:XF 1 "general_operand" "*rfm,*rf,fG,fF"))]
+  ""
   "*
 {
   int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
@@ -1558,61 +1295,33 @@
   /* Handle other kinds of reads to the 387 */
 
   if (STACK_TOP_P (operands[0]) && GET_CODE (operands[1]) == CONST_DOUBLE)
-    return output_move_const_single (operands);
+    return (char *) output_move_const_single (operands);
 
   if (STACK_TOP_P (operands[0]))
        return AS1 (fld%z1,%y1);
 
   /* Handle all XFmode moves not involving the 387 */
 
-  return output_move_double (operands);
-}")
-
-(define_insn "swapxf"
-  [(set (match_operand:XF 0 "register_operand" "f")
-	(match_operand:XF 1 "register_operand" "f"))
-   (set (match_dup 1)
-	(match_dup 0))]
-  ""
-  "*
-{
-  if (STACK_TOP_P (operands[0]))
-    return AS1 (fxch,%1);
-  else
-    return AS1 (fxch,%0);
+  return (char *) output_move_double (operands);
 }")
 
 (define_insn ""
-  [(set (match_operand:DI 0 "push_operand" "=<,<,<,<")
-	(match_operand:DI 1 "general_operand" "riF,o,o,o"))
-   (clobber (match_scratch:SI 2 "=X,&r,&r,X"))
-   (clobber (match_scratch:SI 3 "=X,&r,X,X"))]
+  [(set (match_operand:DI 0 "push_operand" "=<")
+	(match_operand:DI 1 "general_operand" "roiF"))]
   ""
   "*
 {
-  if (GET_CODE (operands[1]) != MEM)
-    return output_move_double (operands);
-
-  else
-    return output_move_pushmem (operands, insn, GET_MODE_SIZE (DImode), 2, 4);
+  return (char *) output_move_double (operands);
 }")
 
 (define_insn "movdi"
-  [(set (match_operand:DI 0 "general_operand" "=o,o,r,rm")
-	(match_operand:DI 1 "general_operand" "o,o,m,riF"))
-   (clobber (match_scratch:SI 2 "=&r,&r,X,X"))
-   (clobber (match_scratch:SI 3 "=&r,X,X,X"))]
+  [(set (match_operand:DI 0 "general_operand" "=r,rm")
+	(match_operand:DI 1 "general_operand" "m,riF"))]
   ""
   "*
 {
-  rtx low[2], high[2], xop[6];
-
-  if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
-    return output_move_double (operands);
-  else
-    return output_move_memory (operands, insn, GET_MODE_SIZE (DImode), 2, 4);
+  return (char *) output_move_double (operands);
 }")
-
 
 ;;- conversion instructions
 ;;- NONE
@@ -1627,7 +1336,7 @@
   ""
   "*
 {
-  if ((!TARGET_386 || REGNO (operands[0]) == 0)
+  if (((TARGET_486 || TARGET_PENTIUM) || REGNO (operands[0]) == 0)
       && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1]))
     {
       rtx xops[2];
@@ -1637,6 +1346,25 @@
       RET;
     }
 
+  if ((((TARGET_486 || TARGET_PENTIUM))) 
+       && !reg_overlap_mentioned_p(operands[0],operands[1]))
+  {
+    rtx xops[2];
+      output_asm_insn (AS2 (xor%L0,%0,%0),operands);
+      output_asm_insn (AS2 (mov%W0,%1,%w0),operands);
+    RET;
+  }
+
+  if ((TARGET_486 || TARGET_PENTIUM))
+  {
+    rtx xops[2];
+      xops[0] = operands[0];
+      xops[1] = gen_rtx (CONST_INT, VOIDmode, 0xffff);
+      output_asm_insn (AS2 (mov%W0,%1,%w0),operands);
+      output_asm_insn (AS2 (and%L0,%1,%k0), xops);
+    RET;
+  }
+
 #ifdef INTEL_SYNTAX
   return AS2 (movzx,%1,%0);
 #else
@@ -1651,7 +1379,7 @@
   ""
   "*
 {
-  if ((!TARGET_386 || REGNO (operands[0]) == 0)
+  if (((TARGET_486 || TARGET_PENTIUM) || REGNO (operands[0]) == 0)
       && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1]))
     {
       rtx xops[2];
@@ -1661,6 +1389,26 @@
       RET;
     }
 
+    /* intel1 */
+  if ((((TARGET_486 || TARGET_PENTIUM))) &&
+       reg_fits_class_p (operands[0], Q_REGS, 0, SImode))
+  {
+    rtx xops[2];
+    if(!reg_overlap_mentioned_p(operands[0],operands[1]))
+    {
+      output_asm_insn (AS2 (xor%L0,%k0,%k0),operands);
+      output_asm_insn (AS2 (mov%B0,%1,%b0),operands);
+    }
+    else
+    {
+      xops[0] = operands[0];
+      xops[1] = gen_rtx (CONST_INT, VOIDmode, 0xff);
+      output_asm_insn (AS2 (mov%B0,%1,%b0),operands);
+      output_asm_insn (AS2 (and%L0,%1,%k0), xops);
+    }
+    RET;
+  }
+
 #ifdef INTEL_SYNTAX
   return AS2 (movzx,%1,%0);
 #else
@@ -1675,7 +1423,7 @@
   ""
   "*
 {
-  if ((!TARGET_386 || REGNO (operands[0]) == 0)
+  if (((TARGET_486 || TARGET_PENTIUM) || REGNO (operands[0]) == 0)
       && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1]))
     {
       rtx xops[2];
@@ -1685,6 +1433,37 @@
       RET;
     }
 
+    /* intel1 */
+  if ((((TARGET_486 || TARGET_PENTIUM))) &&
+       reg_fits_class_p (operands[0], Q_REGS, 0, SImode))
+  {
+    rtx xops[2];
+    if(!reg_overlap_mentioned_p(operands[0],operands[1]))
+    {
+      output_asm_insn (AS2 (xor%L0,%0,%0),operands);
+      output_asm_insn (AS2 (mov%B0,%1,%b0),operands);
+    }
+    else
+    {
+      xops[0] = operands[0];
+      xops[1] = gen_rtx (CONST_INT, VOIDmode, 0xff);
+      output_asm_insn (AS2 (mov%B0,%1,%b0),operands);
+      output_asm_insn (AS2 (and%L0,%1,%k0), xops);
+    }
+    RET;
+  }
+
+  if ((TARGET_486 || TARGET_PENTIUM) && GET_CODE (operands[1]) == REG)
+  {
+    rtx xops[2];
+      xops[0] = operands[0];
+      operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]));
+      xops[1] = gen_rtx (CONST_INT, VOIDmode, 0xff);
+      output_asm_insn (AS2 (mov%L0,%1,%0),operands);
+      output_asm_insn (AS2 (and%L0,%1,%k0), xops);
+    RET;
+  }
+
 #ifdef INTEL_SYNTAX
   return AS2 (movzx,%1,%0);
 #else
@@ -2011,15 +1790,15 @@
 
 (define_expand "fixuns_truncxfsi2"
   [(set (match_dup 4)
-	(match_operand:XF 1 "register_operand" ""))
+      (match_operand:XF 1 "register_operand" ""))
    (parallel [(set (match_dup 2)
-		   (fix:DI (fix:XF (match_dup 4))))
-	      (clobber (match_dup 4))
-	      (clobber (match_dup 5))
-	      (clobber (match_dup 6))
-	      (clobber (match_scratch:SI 7 ""))])
+                 (fix:DI (fix:XF (match_dup 4))))
+            (clobber (match_dup 4))
+            (clobber (match_dup 5))
+            (clobber (match_dup 6))
+            (clobber (match_scratch:SI 7 ""))])
    (set (match_operand:SI 0 "general_operand" "")
-	(match_dup 3))]
+      (match_dup 3))]
   "TARGET_80387"
   "
 {
@@ -2076,13 +1855,13 @@
 
 (define_expand "fix_truncxfdi2"
   [(set (match_dup 2)
-	(match_operand:XF 1 "register_operand" ""))
+      (match_operand:XF 1 "register_operand" ""))
    (parallel [(set (match_operand:DI 0 "general_operand" "")
-		   (fix:DI (fix:XF (match_dup 2))))
-	      (clobber (match_dup 2))
-	      (clobber (match_dup 3))
-	      (clobber (match_dup 4))
-	      (clobber (match_scratch:SI 5 ""))])]
+                 (fix:DI (fix:XF (match_dup 2))))
+            (clobber (match_dup 2))
+            (clobber (match_dup 3))
+            (clobber (match_dup 4))
+            (clobber (match_scratch:SI 5 ""))])]
   "TARGET_80387"
   "
 {
@@ -2132,23 +1911,23 @@
 
 (define_insn ""
   [(set (match_operand:DI 0 "general_operand" "=rm")
-	(fix:DI (fix:XF (match_operand:XF 1 "register_operand" "f"))))
+      (fix:DI (fix:XF (match_operand:XF 1 "register_operand" "f"))))
    (clobber (match_dup 1))
    (clobber (match_operand:SI 2 "memory_operand" "m"))
    (clobber (match_operand:SI 3 "memory_operand" "m"))
    (clobber (match_scratch:SI 4 "=&q"))]
   "TARGET_80387"
-  "* return output_fix_trunc (insn, operands);")
+  "* return (char *) output_fix_trunc (insn, operands);")
 
 (define_insn ""
-  [(set (match_operand:DI 0 "general_operand" "=rm")
-	(fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
+   [(set (match_operand:DI 0 "general_operand" "=rm")
+	   (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
    (clobber (match_dup 1))
    (clobber (match_operand:SI 2 "memory_operand" "m"))
    (clobber (match_operand:SI 3 "memory_operand" "m"))
    (clobber (match_scratch:SI 4 "=&q"))]
   "TARGET_80387"
-  "* return output_fix_trunc (insn, operands);")
+  "* return (char *) output_fix_trunc (insn, operands);")
 
 (define_insn ""
   [(set (match_operand:DI 0 "general_operand" "=rm")
@@ -2158,17 +1937,17 @@
    (clobber (match_operand:SI 3 "memory_operand" "m"))
    (clobber (match_scratch:SI 4 "=&q"))]
   "TARGET_80387"
-  "* return output_fix_trunc (insn, operands);")
+  "* return (char *) output_fix_trunc (insn, operands);")
 
 ;; Signed MODE_FLOAT conversion to SImode.
 
 (define_expand "fix_truncxfsi2"
   [(parallel [(set (match_operand:SI 0 "general_operand" "")
-		   (fix:SI
-		    (fix:XF (match_operand:XF 1 "register_operand" ""))))
-	      (clobber (match_dup 2))
-	      (clobber (match_dup 3))
-	      (clobber (match_scratch:SI 4 ""))])]
+                 (fix:SI
+                  (fix:XF (match_operand:XF 1 "register_operand" ""))))
+            (clobber (match_dup 2))
+            (clobber (match_dup 3))
+            (clobber (match_scratch:SI 4 ""))])]
   "TARGET_80387"
   "
 {
@@ -2206,21 +1985,21 @@
 
 (define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=rm")
-	(fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f"))))
+      (fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f"))))
    (clobber (match_operand:SI 2 "memory_operand" "m"))
    (clobber (match_operand:SI 3 "memory_operand" "m"))
    (clobber (match_scratch:SI 4 "=&q"))]
   "TARGET_80387"
-  "* return output_fix_trunc (insn, operands);")
+  "* return (char *) output_fix_trunc (insn, operands);")
 
 (define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=rm")
-	(fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
+      (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
    (clobber (match_operand:SI 2 "memory_operand" "m"))
    (clobber (match_operand:SI 3 "memory_operand" "m"))
    (clobber (match_scratch:SI 4 "=&q"))]
   "TARGET_80387"
-  "* return output_fix_trunc (insn, operands);")
+  "* return (char *) output_fix_trunc (insn, operands);")
 
 (define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=rm")
@@ -2229,7 +2008,7 @@
    (clobber (match_operand:SI 3 "memory_operand" "m"))
    (clobber (match_scratch:SI 4 "=&q"))]
   "TARGET_80387"
-  "* return output_fix_trunc (insn, operands);")
+  "* return (char *) output_fix_trunc (insn, operands);")
 
 ;; Conversion between fixed point and floating point.
 ;; The actual pattern that matches these is at the end of this file.
@@ -2262,13 +2041,13 @@
 
 (define_expand "floatsixf2"
   [(set (match_operand:XF 0 "register_operand" "")
-	(float:XF (match_operand:SI 1 "nonimmediate_operand" "")))]
+      (float:XF (match_operand:SI 1 "nonimmediate_operand" "")))]
   "TARGET_80387"
   "")
 
 (define_expand "floatdixf2"
   [(set (match_operand:XF 0 "register_operand" "")
-	(float:XF (match_operand:DI 1 "nonimmediate_operand" "")))]
+      (float:XF (match_operand:DI 1 "nonimmediate_operand" "")))]
   "TARGET_80387"
   "")
 
@@ -2276,7 +2055,7 @@
 
 (define_insn ""
   [(set (match_operand:XF 0 "register_operand" "=f")
-	(float:XF (match_operand:DI 1 "general_operand" "rm")))]
+      (float:XF (match_operand:DI 1 "general_operand" "rm")))]
   "TARGET_80387"
   "*
 {
@@ -2344,7 +2123,7 @@
 
 (define_insn ""
   [(set (match_operand:XF 0 "register_operand" "=f,f")
-	(float:XF (match_operand:SI 1 "general_operand" "m,!*r")))]
+      (float:XF (match_operand:SI 1 "general_operand" "m,!*r")))]
   "TARGET_80387"
   "*
 {
@@ -2379,83 +2158,34 @@
 ;;- add instructions
 
 (define_insn "adddi3"
-  [(set (match_operand:DI 0 "general_operand" "=&r,ro,o,&r,ro,o,&r,o,o,o")
-	(plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,o,riF,o,or,riF,riF,o")
-		 (match_operand:DI 2 "general_operand" "o,riF,o,0,0,0,oriF,riF,o,o")))
-   (clobber (match_scratch:SI 3 "=X,X,&r,X,X,&r,X,X,&r,&r"))]
+  [(set (match_operand:DI 0 "general_operand" "=&r,ro")
+	(plus:DI (match_operand:DI 1 "general_operand" "%0,0")
+		 (match_operand:DI 2 "general_operand" "o,riF")))]
   ""
   "*
 {
-  rtx low[3], high[3], xops[7], temp;
+  rtx low[3], high[3];
 
   CC_STATUS_INIT;
 
-  if (rtx_equal_p (operands[0], operands[2]))
-    {
-      temp = operands[1];
-      operands[1] = operands[2];
-      operands[2] = temp;
-    }
-
   split_di (operands, 3, low, high);
-  if (!rtx_equal_p (operands[0], operands[1]))
-    {
-      xops[0] = high[0];
-      xops[1] = low[0];
-      xops[2] = high[1];
-      xops[3] = low[1];
-
-      if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
-	{
-	  output_asm_insn (AS2 (mov%L1,%3,%1), xops);
-	  output_asm_insn (AS2 (mov%L0,%2,%0), xops);
-	}
-      else
-	{
-	  xops[4] = high[2];
-	  xops[5] = low[2];
-	  xops[6] = operands[3];
-	  output_asm_insn (AS2 (mov%L6,%3,%6), xops);
-	  output_asm_insn (AS2 (add%L6,%5,%6), xops);
-	  output_asm_insn (AS2 (mov%L1,%6,%1), xops);
-	  output_asm_insn (AS2 (mov%L6,%2,%6), xops);
-	  output_asm_insn (AS2 (adc%L6,%4,%6), xops);
-	  output_asm_insn (AS2 (mov%L0,%6,%0), xops);
-	  RET;
-	}
-    }
 
-  if (GET_CODE (operands[3]) == REG && GET_CODE (operands[2]) != REG)
-    {
-      xops[0] = high[0];
-      xops[1] = low[0];
-      xops[2] = high[2];
-      xops[3] = low[2];
-      xops[4] = operands[3];
-
-      output_asm_insn (AS2 (mov%L4,%3,%4), xops);
-      output_asm_insn (AS2 (add%L1,%4,%1), xops);
-      output_asm_insn (AS2 (mov%L4,%2,%4), xops);
-      output_asm_insn (AS2 (adc%L0,%4,%0), xops);
-    }
-
-  else if (GET_CODE (low[2]) != CONST_INT || INTVAL (low[2]) != 0)
+  if (GET_CODE (low[2]) != CONST_INT || INTVAL (low[2]) != 0)
     {
       output_asm_insn (AS2 (add%L0,%2,%0), low);
       output_asm_insn (AS2 (adc%L0,%2,%0), high);
     }
-
   else
     output_asm_insn (AS2 (add%L0,%2,%0), high);
-
   RET;
 }")
 
 ;; On a 486, it is faster to do movl/addl than to do a single leal if
 ;; operands[1] and operands[2] are both registers.
 
+; intel1 removed ? from first constraint
 (define_insn "addsi3"
-  [(set (match_operand:SI 0 "general_operand" "=?r,rm,r")
+  [(set (match_operand:SI 0 "general_operand" "=r,rm,r")
 	(plus:SI (match_operand:SI 1 "general_operand" "%r,0,0")
 		 (match_operand:SI 2 "general_operand" "ri,ri,rm")))]
   ""
@@ -2466,20 +2196,23 @@
       if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
 	return AS2 (add%L0,%1,%0);
 
-      if (operands[2] == stack_pointer_rtx)
-	{
-	  rtx temp;
+      if (! (TARGET_486 || TARGET_PENTIUM) || ! REG_P (operands[2]))
+        {
+	  CC_STATUS_INIT;
 
-	  temp = operands[1];
-	  operands[1] = operands[2];
-	  operands[2] = temp;
-	}
+	  if (operands[2] == stack_pointer_rtx)
+	    {
+	      rtx temp;
 
-      if (operands[2] != stack_pointer_rtx)
-	{
-	  CC_STATUS_INIT;
-	  operands[1] = SET_SRC (PATTERN (insn));
-	  return AS2 (lea%L0,%a1,%0);
+	      temp = operands[1];
+	      operands[1] = operands[2];
+	      operands[2] = temp;
+	    }
+	  if (operands[2] != stack_pointer_rtx)
+	    {
+	      operands[1] = SET_SRC (PATTERN (insn));
+	      return AS2 (lea%L0,%a1,%0);
+	    }
 	}
 
       output_asm_insn (AS2 (mov%L0,%1,%0), operands);
@@ -2510,24 +2243,23 @@
       && GET_CODE (operands[2]) == CONST_INT
       && (INTVAL (operands[2]) & 0xff) == 0)
     {
-      int byteval = (INTVAL (operands[2]) >> 8) & 0xff;
       CC_STATUS_INIT;
 
-      if (byteval == 1)
-	return AS1 (inc%B0,%h0);
-      else if (byteval == 255)
-	return AS1 (dec%B0,%h0);
+       operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff);
+
+      if (operands[2] == const1_rtx)
+      return AS1 (inc%B0,%h0);
+
+      if (operands[2] == constm1_rtx)
+      return AS1 (dec%B0,%h0);
 
-      operands[2] = GEN_INT (byteval);
       return AS2 (add%B0,%2,%h0);
     }
 
   if (operands[2] == const1_rtx)
     return AS1 (inc%W0,%0);
 
-  if (operands[2] == constm1_rtx
-      || (GET_CODE (operands[2]) == CONST_INT
-	  && INTVAL (operands[2]) == 65535))
+  if (operands[2] == constm1_rtx)
     return AS1 (dec%W0,%0);
 
   return AS2 (add%W0,%2,%0);
@@ -2543,9 +2275,7 @@
   if (operands[2] == const1_rtx)
     return AS1 (inc%B0,%0);
 
-  if (operands[2] == constm1_rtx
-      || (GET_CODE (operands[2]) == CONST_INT
-	  && INTVAL (operands[2]) == 255))
+  if (operands[2] == constm1_rtx)
     return AS1 (dec%B0,%0);
 
   return AS2 (add%B0,%2,%0);
@@ -2578,7 +2308,7 @@
 
 ;; addsi3 is faster, so put this after.
 
-(define_insn "movsi_lea"
+(define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
         (match_operand:QI 1 "address_operand" "p"))]
   ""
@@ -2608,8 +2338,8 @@
 
 (define_expand "addxf3"
   [(set (match_operand:XF 0 "register_operand" "")
-	(plus:XF (match_operand:XF 1 "nonimmediate_operand" "")
-		 (match_operand:XF 2 "nonimmediate_operand" "")))]
+      (plus:XF (match_operand:XF 1 "nonimmediate_operand" "")
+               (match_operand:XF 2 "nonimmediate_operand" "")))]
   "TARGET_80387"
   "")
 
@@ -2630,66 +2360,23 @@
 ;;- subtract instructions
 
 (define_insn "subdi3"
-  [(set (match_operand:DI 0 "general_operand" "=&r,ro,&r,o,o")
-	(minus:DI (match_operand:DI 1 "general_operand" "0,0,roiF,riF,o")
-		  (match_operand:DI 2 "general_operand" "o,riF,roiF,riF,o")))
-   (clobber (match_scratch:SI 3 "=X,X,X,X,&r"))]
+  [(set (match_operand:DI 0 "general_operand" "=&r,ro")
+	(minus:DI (match_operand:DI 1 "general_operand" "0,0")
+		  (match_operand:DI 2 "general_operand" "o,riF")))]
   ""
   "*
 {
-  rtx low[3], high[3], xops[7];
+  rtx low[3], high[3];
 
   CC_STATUS_INIT;
 
   split_di (operands, 3, low, high);
 
-  if (!rtx_equal_p (operands[0], operands[1]))
-    {
-      xops[0] = high[0];
-      xops[1] = low[0];
-      xops[2] = high[1];
-      xops[3] = low[1];
-
-      if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
-	{
-	  output_asm_insn (AS2 (mov%L1,%3,%1), xops);
-	  output_asm_insn (AS2 (mov%L0,%2,%0), xops);
-	}
-      else
-	{
-	  xops[4] = high[2];
-	  xops[5] = low[2];
-	  xops[6] = operands[3];
-	  output_asm_insn (AS2 (mov%L6,%3,%6), xops);
-	  output_asm_insn (AS2 (sub%L6,%5,%6), xops);
-	  output_asm_insn (AS2 (mov%L1,%6,%1), xops);
-	  output_asm_insn (AS2 (mov%L6,%2,%6), xops);
-	  output_asm_insn (AS2 (sbb%L6,%4,%6), xops);
-	  output_asm_insn (AS2 (mov%L0,%6,%0), xops);
-	  RET;
-	}
-    }
-
-  if (GET_CODE (operands[3]) == REG)
-    {
-      xops[0] = high[0];
-      xops[1] = low[0];
-      xops[2] = high[2];
-      xops[3] = low[2];
-      xops[4] = operands[3];
-
-      output_asm_insn (AS2 (mov%L4,%3,%4), xops);
-      output_asm_insn (AS2 (sub%L1,%4,%1), xops);
-      output_asm_insn (AS2 (mov%L4,%2,%4), xops);
-      output_asm_insn (AS2 (sbb%L0,%4,%0), xops);
-    }
-
-  else if (GET_CODE (low[2]) != CONST_INT || INTVAL (low[2]) != 0)
+  if (GET_CODE (low[2]) != CONST_INT || INTVAL (low[2]) != 0)
     {
       output_asm_insn (AS2 (sub%L0,%2,%0), low);
       output_asm_insn (AS2 (sbb%L0,%2,%0), high);
     }
-
   else
     output_asm_insn (AS2 (sub%L0,%2,%0), high);
 
@@ -2721,8 +2408,8 @@
 
 (define_expand "subxf3"
   [(set (match_operand:XF 0 "register_operand" "")
-	(minus:XF (match_operand:XF 1 "nonimmediate_operand" "")
-		  (match_operand:XF 2 "nonimmediate_operand" "")))]
+      (minus:XF (match_operand:XF 1 "nonimmediate_operand" "")
+                (match_operand:XF 2 "nonimmediate_operand" "")))]
   "TARGET_80387"
   "")
 
@@ -2751,14 +2438,14 @@
 
 (define_insn ""
   [(set (match_operand:HI 0 "general_operand" "=r")
-	(mult:HI (match_operand:HI 1 "general_operand" "%0")
+	(mult:SI (match_operand:HI 1 "general_operand" "%0")
 		 (match_operand:HI 2 "general_operand" "r")))]
   "GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x80"
   "* return AS2 (imul%W0,%2,%0);")
 
 (define_insn "mulhi3"
   [(set (match_operand:HI 0 "general_operand" "=r,r")
-	(mult:HI (match_operand:HI 1 "general_operand" "%0,rm")
+	(mult:SI (match_operand:HI 1 "general_operand" "%0,rm")
 		 (match_operand:HI 2 "general_operand" "g,i")))]
   ""
   "*
@@ -2793,58 +2480,21 @@
   return AS3 (imul%L0,%2,%1,%0);
 }")
 
-(define_insn "umulqihi3"
+(define_insn ""
   [(set (match_operand:HI 0 "general_operand" "=a")
-	(mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
-		 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))]
+	(mult:SI (zero_extend:HI
+		  (match_operand:QI 1 "nonimmediate_operand" "%0"))
+		 (zero_extend:HI
+		  (match_operand:QI 2 "nonimmediate_operand" "qm"))))]
   ""
   "mul%B0 %2")
 
-(define_insn "mulqihi3"
-  [(set (match_operand:HI 0 "general_operand" "=a")
-	(mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
-		 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))]
-  ""
-  "imul%B0 %2")
-
-(define_insn "umulsidi3"
-  [(set (match_operand:DI 0 "register_operand" "=A")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
-		 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))]
-  "TARGET_WIDE_MULTIPLY"
-  "mul%L0 %2")
-
-(define_insn "mulsidi3"
-  [(set (match_operand:DI 0 "register_operand" "=A")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
-		 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))]
-  "TARGET_WIDE_MULTIPLY"
-  "imul%L0 %2")
-
-(define_insn "umulsi3_highpart"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%a"))
-					   (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm")))
-				  (const_int 32))))
-   (clobber (match_scratch:SI 3 "=a"))]
-  "TARGET_WIDE_MULTIPLY"
-  "mul%L0 %2")
-
-(define_insn "smulsi3_highpart"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%a"))
-					   (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm")))
-				  (const_int 32))))
-   (clobber (match_scratch:SI 3 "=a"))]
-  "TARGET_WIDE_MULTIPLY"
-  "imul%L0 %2")
-
 ;; The patterns that match these are at the end of this file.
 
 (define_expand "mulxf3"
   [(set (match_operand:XF 0 "register_operand" "")
-	(mult:XF (match_operand:XF 1 "nonimmediate_operand" "")
-		 (match_operand:XF 2 "nonimmediate_operand" "")))]
+      (mult:XF (match_operand:XF 1 "nonimmediate_operand" "")
+               (match_operand:XF 2 "nonimmediate_operand" "")))]
   "TARGET_80387"
   "")
 
@@ -2882,8 +2532,8 @@
 
 (define_expand "divxf3"
   [(set (match_operand:XF 0 "register_operand" "")
-	(div:XF (match_operand:XF 1 "nonimmediate_operand" "")
-		(match_operand:XF 2 "nonimmediate_operand" "")))]
+      (div:XF (match_operand:XF 1 "nonimmediate_operand" "")
+              (match_operand:XF 2 "nonimmediate_operand" "")))]
   "TARGET_80387"
   "")
 
@@ -2988,20 +2638,37 @@
 ;; optional reloads to be generated if op 3 is a pseudo in a stack slot.
 
 ;; ??? What if we only change one byte of an offsettable memory reference?
+;;(define_insn "andsi3"
+;;  [(set (match_operand:SI 0 "general_operand" "=r,r,rm,r")
+;;	(and:SI (match_operand:SI 1 "general_operand" "%rm,qm,0,0")
+;;		(match_operand:SI 2 "general_operand" "L,K,ri,rm")))]
+;;  ""
+;;  "*
+;;{
+;intel1
 (define_insn "andsi3"
-  [(set (match_operand:SI 0 "general_operand" "=r,r,rm,r")
-	(and:SI (match_operand:SI 1 "general_operand" "%rm,qm,0,0")
-		(match_operand:SI 2 "general_operand" "L,K,ri,rm")))]
+  [(set (match_operand:SI 0 "general_operand" "=rm,r,r")
+	(and:SI (match_operand:SI 1 "general_operand" "0,0,rm")
+		(match_operand:SI 2 "general_operand" "ri,rm,0")))]
   ""
   "*
 {
+  /* intel1 */
+  if (!rtx_equal_p (operands[0], operands[1])
+      && rtx_equal_p (operands[0], operands[2]))
+    {
+      rtx tmp;
+      tmp = operands[1];
+      operands[1] = operands[2];
+      operands[2] = tmp;
+    }
   if (GET_CODE (operands[2]) == CONST_INT
       && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
     {
       if (INTVAL (operands[2]) == 0xffff && REG_P (operands[0])
 	  && (! REG_P (operands[1])
 	      || REGNO (operands[0]) != 0 || REGNO (operands[1]) != 0)
-	  && (TARGET_386 || ! rtx_equal_p (operands[0], operands[1])))
+	  && (! (TARGET_486 || TARGET_PENTIUM) || ! rtx_equal_p (operands[0], operands[1])))
 	{
 	  /* ??? tege: Should forget CC_STATUS only if we clobber a
 	     remembered operand.  Fix that later.  */
@@ -3017,7 +2684,7 @@
 	  && !(REG_P (operands[1]) && NON_QI_REG_P (operands[1]))
 	  && (! REG_P (operands[1])
 	      || REGNO (operands[0]) != 0 || REGNO (operands[1]) != 0)
-	  && (TARGET_386 || ! rtx_equal_p (operands[0], operands[1])))
+	  && (! (TARGET_486 || TARGET_PENTIUM) || ! rtx_equal_p (operands[0], operands[1])))
 	{
 	  /* ??? tege: Should forget CC_STATUS only if we clobber a
 	     remembered operand.  Fix that later.  */
@@ -3146,14 +2813,23 @@
 
 ;;- Bit set (inclusive or) instructions
 
+;intel1 added last constaints
 ;; ??? What if we only change one byte of an offsettable memory reference?
 (define_insn "iorsi3"
-  [(set (match_operand:SI 0 "general_operand" "=rm,r")
-	(ior:SI (match_operand:SI 1 "general_operand" "%0,0")
-		(match_operand:SI 2 "general_operand" "ri,rm")))]
+  [(set (match_operand:SI 0 "general_operand" "=rm,r,r")
+	(ior:SI (match_operand:SI 1 "general_operand" "%0,0,rm")
+		(match_operand:SI 2 "general_operand" "ri,rm,0")))]
   ""
   "*
 {
+  /* intel1 */
+  if (!rtx_equal_p (operands[0], operands[1]))
+    {
+      rtx tmp;
+      tmp = operands[1];
+      operands[1] = operands[2];
+      operands[2] = tmp;
+    }
   if (GET_CODE (operands[2]) == CONST_INT
       && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
     {
@@ -3183,13 +2859,22 @@
   return AS2 (or%L0,%2,%0);
 }")
 
+;intel1 added last constraint
 (define_insn "iorhi3"
-  [(set (match_operand:HI 0 "general_operand" "=rm,r")
-	(ior:HI (match_operand:HI 1 "general_operand" "%0,0")
-		(match_operand:HI 2 "general_operand" "ri,rm")))]
+  [(set (match_operand:HI 0 "general_operand" "=rm,r,r")
+	(ior:HI (match_operand:HI 1 "general_operand" "%0,0,rm")
+		(match_operand:HI 2 "general_operand" "ri,rm,0")))]
   ""
   "*
 {
+  /* intel1 */
+  if (!rtx_equal_p (operands[0], operands[1]))
+    {
+      rtx tmp;
+      tmp = operands[1];
+      operands[1] = operands[2];
+      operands[2] = tmp;
+    }
   if (GET_CODE (operands[2]) == CONST_INT
       && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
     {
@@ -3225,12 +2910,24 @@
   return AS2 (or%W0,%2,%0);
 }")
 
+;intel1 added last constraint 
 (define_insn "iorqi3"
-  [(set (match_operand:QI 0 "general_operand" "=qm,q")
-	(ior:QI (match_operand:QI 1 "general_operand" "%0,0")
-		(match_operand:QI 2 "general_operand" "qn,qmn")))]
+  [(set (match_operand:QI 0 "general_operand" "=qm,q,q")
+	(ior:QI (match_operand:QI 1 "general_operand" "%0,0,qm")
+		(match_operand:QI 2 "general_operand" "qn,qmn,0")))]
   ""
-  "* return AS2 (or%B0,%2,%0);")
+  "* 
+{
+  /* intel1 */
+  if (!rtx_equal_p (operands[0], operands[1]))
+    {
+      rtx tmp;
+      tmp = operands[1];
+      operands[1] = operands[2];
+      operands[2] = tmp;
+    }
+  return AS2 (or%B0,%2,%0);
+}")
 
 ;;- xor instructions
 
@@ -3271,13 +2968,22 @@
   return AS2 (xor%L0,%2,%0);
 }")
 
+;intel1 added last constraint 
 (define_insn "xorhi3"
-  [(set (match_operand:HI 0 "general_operand" "=rm,r")
-	(xor:HI (match_operand:HI 1 "general_operand" "%0,0")
-		(match_operand:HI 2 "general_operand" "ri,rm")))]
+  [(set (match_operand:HI 0 "general_operand" "=rm,r,r")
+	(xor:HI (match_operand:HI 1 "general_operand" "%0,0,rm")
+		(match_operand:HI 2 "general_operand" "ri,rm,0")))]
   ""
   "*
 {
+  /* intel1 */
+  if (!rtx_equal_p (operands[0], operands[1]))
+    {
+      rtx tmp;
+      tmp = operands[1];
+      operands[1] = operands[2];
+      operands[2] = tmp;
+    }
   if (GET_CODE (operands[2]) == CONST_INT
       && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
     {
@@ -3313,12 +3019,24 @@
   return AS2 (xor%W0,%2,%0);
 }")
 
+;intel1 added last constraint 
 (define_insn "xorqi3"
-  [(set (match_operand:QI 0 "general_operand" "=qm,q")
-	(xor:QI (match_operand:QI 1 "general_operand" "%0,0")
-		(match_operand:QI 2 "general_operand" "qn,qm")))]
-  ""
-  "* return AS2 (xor%B0,%2,%0);")
+  [(set (match_operand:QI 0 "general_operand" "=qm,q,q")
+	(xor:QI (match_operand:QI 1 "general_operand" "%0,0,qm")
+		(match_operand:QI 2 "general_operand" "qn,qm,0")))]
+  ""
+  "* 
+ {
+  /* intel1 */
+  if (!rtx_equal_p (operands[0], operands[1]))
+    {
+      rtx tmp;
+      tmp = operands[1];
+      operands[1] = operands[2];
+      operands[2] = tmp;
+    }
+ return AS2 (xor%B0,%2,%0);
+ }")
 
 ;;- negation instructions
 
@@ -3380,13 +3098,13 @@
 
 (define_insn "negxf2"
   [(set (match_operand:XF 0 "register_operand" "=f")
-	(neg:XF (match_operand:XF 1 "general_operand" "0")))]
+      (neg:XF (match_operand:XF 1 "general_operand" "0")))]
   "TARGET_80387"
   "fchs")
 
 (define_insn ""
   [(set (match_operand:XF 0 "register_operand" "=f")
-	(neg:XF (float_extend:XF (match_operand:DF 1 "general_operand" "0"))))]
+      (neg:XF (float_extend:XF (match_operand:DF 1 "general_operand" "0"))))]
   "TARGET_80387"
   "fchs")
 
@@ -3396,120 +3114,108 @@
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(abs:SF (match_operand:SF 1 "general_operand" "0")))]
   "TARGET_80387"
-  "fabs")
+  "fabs"[(set_attr "type" "fpop")])
 
 (define_insn "absdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(abs:DF (match_operand:DF 1 "general_operand" "0")))]
   "TARGET_80387"
-  "fabs")
+  "fabs"[(set_attr "type" "fpop")])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(abs:DF (float_extend:DF (match_operand:SF 1 "general_operand" "0"))))]
   "TARGET_80387"
-  "fabs")
+  "fabs"[(set_attr "type" "fpop")])
 
 (define_insn "absxf2"
   [(set (match_operand:XF 0 "register_operand" "=f")
-	(abs:XF (match_operand:XF 1 "general_operand" "0")))]
+      (abs:XF (match_operand:XF 1 "general_operand" "0")))]
   "TARGET_80387"
-  "fabs")
+  "fabs"[(set_attr "type" "fpop")])
 
 (define_insn ""
   [(set (match_operand:XF 0 "register_operand" "=f")
-	(abs:XF (float_extend:XF (match_operand:DF 1 "general_operand" "0"))))]
+      (abs:XF (float_extend:XF (match_operand:DF 1 "general_operand" "0"))))]
   "TARGET_80387"
-  "fabs")
+  "fabs"[(set_attr "type" "fpop")])
 
 (define_insn "sqrtsf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(sqrt:SF (match_operand:SF 1 "general_operand" "0")))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && (TARGET_IEEE_FP || flag_fast_math) "
-  "fsqrt")
+  "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
+  "fsqrt"[(set_attr "type" "fpop")])
 
 (define_insn "sqrtdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(sqrt:DF (match_operand:DF 1 "general_operand" "0")))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && (TARGET_IEEE_FP || flag_fast_math) "
-  "fsqrt")
+  "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
+  "fsqrt"[(set_attr "type" "fpop")])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(sqrt:DF (float_extend:DF
 		  (match_operand:SF 1 "general_operand" "0"))))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 
-   && (TARGET_IEEE_FP || flag_fast_math) "
-  "fsqrt")
+  "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
+  "fsqrt"[(set_attr "type" "fpop")])
 
 (define_insn "sqrtxf2"
   [(set (match_operand:XF 0 "register_operand" "=f")
-	(sqrt:XF (match_operand:XF 1 "general_operand" "0")))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 
-   && (TARGET_IEEE_FP || flag_fast_math) "
-  "fsqrt")
+      (sqrt:XF (match_operand:XF 1 "general_operand" "0")))]
+  "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
+  "fsqrt"[(set_attr "type" "fpop")])
 
 (define_insn ""
   [(set (match_operand:XF 0 "register_operand" "=f")
-	(sqrt:XF (float_extend:XF
-		  (match_operand:DF 1 "general_operand" "0"))))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 
-   && (TARGET_IEEE_FP || flag_fast_math) "
-  "fsqrt")
+      (sqrt:XF (float_extend:XF
+                (match_operand:DF 1 "general_operand" "0"))))]
+  "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
+  "fsqrt"[(set_attr "type" "fpop")])
 
 (define_insn ""
   [(set (match_operand:XF 0 "register_operand" "=f")
-	(sqrt:XF (float_extend:XF
-		  (match_operand:SF 1 "general_operand" "0"))))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 
-   && (TARGET_IEEE_FP || flag_fast_math) "
-  "fsqrt")
+      (sqrt:XF (float_extend:XF
+                (match_operand:SF 1 "general_operand" "0"))))]
+  "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
+  "fsqrt"[(set_attr "type" "fpop")])
 
 (define_insn "sindf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 
-   && (TARGET_IEEE_FP || flag_fast_math) "
-  "fsin")
+  "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
+  "fsin"[(set_attr "type" "fpop")])
 
 (define_insn "sinsf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 
-   && (TARGET_IEEE_FP || flag_fast_math) "
-  "fsin")
+  "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
+  "fsin"[(set_attr "type" "fpop")])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(unspec:DF [(float_extend:DF
 		     (match_operand:SF 1 "register_operand" "0"))] 1))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 
-   && (TARGET_IEEE_FP || flag_fast_math) "
-  "fsin")
+  "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
+  "fsin"[(set_attr "type" "fpop")])
 
 (define_insn "cosdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 
-   && (TARGET_IEEE_FP || flag_fast_math) "
-  "fcos")
+  "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
+  "fcos"[(set_attr "type" "fpop")])
 
 (define_insn "cossf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 
-   && (TARGET_IEEE_FP || flag_fast_math) "
-  "fcos")
+  "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
+  "fcos"[(set_attr "type" "fpop")])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(unspec:DF [(float_extend:DF
 		     (match_operand:SF 1 "register_operand" "0"))] 2))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 
-   && (TARGET_IEEE_FP || flag_fast_math) "
-  "fcos")
+  "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
+  "fcos"[(set_attr "type" "fpop")])
 
 ;;- one complement instructions
 
@@ -3660,7 +3366,7 @@
 {
   if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1]))
     {
-      if (!TARGET_386 && INTVAL (operands[2]) == 1)
+      if ((TARGET_486 || TARGET_PENTIUM) && INTVAL (operands[2]) == 1)
 	{
 	  output_asm_insn (AS2 (mov%L0,%1,%0), operands);
 	  return AS2 (add%L0,%1,%0);
@@ -4161,7 +3867,7 @@
 			 (const_int 1)
 			 (match_operand:SI 2 "general_operand" "r"))
 	(match_operand:SI 3 "const_int_operand" "n"))]
-  "TARGET_386 && GET_CODE (operands[2]) != CONST_INT"
+  "! (TARGET_486 || TARGET_PENTIUM) && GET_CODE (operands[2]) != CONST_INT"
   "*
 {
   CC_STATUS_INIT;
@@ -4179,7 +3885,7 @@
 	(xor:SI (ashift:SI (const_int 1)
 			   (match_operand:SI 1 "general_operand" "r"))
 		(match_operand:SI 2 "general_operand" "0")))]
-  "TARGET_386 && GET_CODE (operands[1]) != CONST_INT"
+  "! (TARGET_486 || TARGET_PENTIUM) && GET_CODE (operands[1]) != CONST_INT"
   "*
 {
   CC_STATUS_INIT;
@@ -4192,7 +3898,7 @@
 	(xor:SI (match_operand:SI 1 "general_operand" "0")
 		(ashift:SI (const_int 1)
 			   (match_operand:SI 2 "general_operand" "r"))))]
-  "TARGET_386 && GET_CODE (operands[2]) != CONST_INT"
+  "! (TARGET_486 || TARGET_PENTIUM) && GET_CODE (operands[2]) != CONST_INT"
   "*
 {
   CC_STATUS_INIT;
@@ -4537,6 +4243,15 @@
   if (cc_prev_status.flags & CC_Z_IN_NOT_C)
     return \"jnc %l0\";
   else
+  /* intel1 */
+  if (cc_prev_status.flags & CC_TEST_AX)
+    {
+      operands[1] = gen_rtx (REG, SImode, 0);
+      operands[2] = GEN_INT (0x4000);
+      output_asm_insn (AS2 (testl,%2,%1), operands);
+      return AS1 (jne,%l0);
+    }
+
     return \"je %l0\";
 }")
 
@@ -4569,6 +4284,15 @@
   if (cc_prev_status.flags & CC_Z_IN_NOT_C)
     return \"jc %l0\";
   else
+  /* intel1 */
+  if (cc_prev_status.flags & CC_TEST_AX)
+    {
+      operands[1] = gen_rtx (REG, SImode, 0);
+      operands[2] = GEN_INT (0x4000);
+      output_asm_insn (AS2 (testl,%2,%1), operands);
+      return AS1 (je,%l0);
+    }
+
     return \"jne %l0\";
 }")
 
@@ -4594,6 +4318,13 @@
   if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
     return AS1 (je,%l0);
 
+  if (cc_prev_status.flags & CC_TEST_AX)
+    {
+      operands[1] = gen_rtx (REG, SImode, 0);
+      operands[2] = GEN_INT (0x4100);
+      output_asm_insn (AS2 (testl,%2,%1), operands);
+      return AS1 (je,%l0);
+    }
   OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", NULL_PTR);
 }")
 
@@ -4638,6 +4369,14 @@
   if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
     return AS1 (je,%l0);
 
+  /* intel1 */
+  if (cc_prev_status.flags & CC_TEST_AX)
+    {
+      operands[1] = gen_rtx (REG, SImode, 0);
+      operands[2] = GEN_INT (0x100);
+      output_asm_insn (AS2 (testl,%2,%1), operands);
+      return AS1 (jne,%l0);
+    }
   OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\");
 }")
 
@@ -4681,7 +4420,14 @@
 {
   if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
     return AS1 (je,%l0);
-
+  /* intel1 */
+  if (cc_prev_status.flags & CC_TEST_AX)
+    {
+      operands[1] = gen_rtx (REG, SImode, 0);
+      operands[2] = GEN_INT (0x100);
+      output_asm_insn (AS2 (testl,%2,%1), operands);
+      return AS1 (je,%l0);
+    }
   OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\");
 }")
 
@@ -4725,6 +4471,14 @@
 {
   if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
     return AS1 (jb,%l0);
+  /* intel1 */
+  if (cc_prev_status.flags & CC_TEST_AX)
+    {
+      operands[1] = gen_rtx (REG, SImode, 0);
+      operands[2] = GEN_INT (0x4100);
+      output_asm_insn (AS2 (testl,%2,%1), operands);
+      return AS1 (jne,%l0);
+    }
 
   OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", NULL_PTR);
 }")
@@ -4762,6 +4516,14 @@
   if (cc_prev_status.flags & CC_Z_IN_NOT_C)
     return \"jc %l0\";
   else
+  /* intel1 */
+  if (cc_prev_status.flags & CC_TEST_AX)
+    {
+      operands[1] = gen_rtx (REG, SImode, 0);
+      operands[2] = GEN_INT (0x4000);
+      output_asm_insn (AS2 (testl,%2,%1), operands);
+      return AS1 (je,%l0);
+    }
     return \"jne %l0\";
 }")
 
@@ -4777,6 +4539,14 @@
   if (cc_prev_status.flags & CC_Z_IN_NOT_C)
     return \"jnc %l0\";
   else
+  /* intel1 */
+  if (cc_prev_status.flags & CC_TEST_AX)
+    {
+      operands[1] = gen_rtx (REG, SImode, 0);
+      operands[2] = GEN_INT (0x4000);
+      output_asm_insn (AS2 (testl,%2,%1), operands);
+      return AS1 (jne,%l0);
+    }
     return \"je %l0\";
 }")
 
@@ -4791,7 +4561,14 @@
 {
   if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
     return AS1 (jne,%l0);
-
+  /* intel1 */
+  if (cc_prev_status.flags & CC_TEST_AX)
+    {
+      operands[1] = gen_rtx (REG, SImode, 0);
+      operands[2] = GEN_INT (0x4100);
+      output_asm_insn (AS2 (testl,%2,%1), operands);
+      return AS1 (jne,%l0);
+    }
   OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", NULL_PTR);
 }")
 
@@ -4815,6 +4592,14 @@
 {
   if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
     return AS1 (jne,%l0);
+  /* intel1 */
+  if (cc_prev_status.flags & CC_TEST_AX)
+    {
+      operands[1] = gen_rtx (REG, SImode, 0);
+      operands[2] = GEN_INT (0x100);
+      output_asm_insn (AS2 (testl,%2,%1), operands);
+      return AS1 (je,%l0);
+    }
 
   OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\");
 }")
@@ -4839,7 +4624,14 @@
 {
   if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
     return AS1 (jne,%l0);
-
+  /* intel1 */
+  if (cc_prev_status.flags & CC_TEST_AX)
+    {
+      operands[1] = gen_rtx (REG, SImode, 0);
+      operands[2] = GEN_INT (0x100);
+      output_asm_insn (AS2 (testl,%2,%1), operands);
+      return AS1 (jne,%l0);
+    }
   OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\");
 }")
 
@@ -4864,6 +4656,14 @@
   if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
     return AS1 (jae,%l0);
 
+  /* intel1 */
+  if (cc_prev_status.flags & CC_TEST_AX)
+    {
+      operands[1] = gen_rtx (REG, SImode, 0);
+      operands[2] = GEN_INT (0x4100);
+      output_asm_insn (AS2 (testl,%2,%1), operands);
+      return AS1 (je,%l0);
+    }
   OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", NULL_PTR);
 }")
 
@@ -5210,42 +5010,126 @@
   "!HALF_PIC_P ()"
   "call %P1")
 
-;; Call subroutine returning any type.
-
 (define_expand "untyped_call"
-  [(parallel [(call (match_operand 0 "" "")
+  [(parallel [(call (match_operand:QI 0 "indirect_operand" "")
 		    (const_int 0))
-	      (match_operand 1 "" "")
+	      (match_operand:BLK 1 "memory_operand" "")
 	      (match_operand 2 "" "")])]
   ""
   "
 {
-  int i;
+  rtx addr;
+
+  if (flag_pic)
+    current_function_uses_pic_offset_table = 1;
+
+  /* With half-pic, force the address into a register.  */
+  addr = XEXP (operands[0], 0);
+  if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr))
+    XEXP (operands[0], 0) = force_reg (Pmode, addr);
 
-  emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
+  operands[1] = change_address (operands[1], DImode, XEXP (operands[1], 0));
+  if (! expander_call_insn_operand (operands[1], QImode))
+    operands[1]
+      = change_address (operands[1], VOIDmode,
+			copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
+}")
+
+(define_insn ""
+  [(call (match_operand:QI 0 "call_insn_operand" "m")
+	 (const_int 0))
+   (match_operand:DI 1 "memory_operand" "o")
+   (match_operand 2 "" "")]
+  ""
+  "*
+{
+  rtx addr = operands[1];
 
-  for (i = 0; i < XVECLEN (operands[2], 0); i++)
+  if (GET_CODE (operands[0]) == MEM
+      && ! CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
     {
-      rtx set = XVECEXP (operands[2], 0, i);
-      emit_move_insn (SET_DEST (set), SET_SRC (set));
+      operands[0] = XEXP (operands[0], 0);
+      output_asm_insn (AS1 (call,%*%0), operands);
     }
+  else
+    output_asm_insn (AS1 (call,%P0), operands);
 
-  /* The optimizer does not know that the call sets the function value
-     registers we stored in the result block.  We avoid problems by
-     claiming that all hard registers are used and clobbered at this
-     point.  */
-  emit_insn (gen_blockage ());
+  operands[2] = gen_rtx (REG, SImode, 0);
+  output_asm_insn (AS2 (mov%L2,%2,%1), operands);
 
-  DONE;
+  operands[2] = gen_rtx (REG, SImode, 1);
+  operands[1] = adj_offsettable_operand (addr, 4);
+  output_asm_insn (AS2 (mov%L2,%2,%1), operands);
+
+  operands[1] = adj_offsettable_operand (addr, 8);
+  return AS1 (fnsave,%1);
 }")
 
-;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
-;; all of memory.  This blocks insns from being moved across this point.
+(define_insn ""
+  [(call (mem:QI (match_operand:SI 0 "symbolic_operand" ""))
+	 (const_int 0))
+   (match_operand:DI 1 "memory_operand" "o")
+   (match_operand 2 "" "")]
+  "!HALF_PIC_P ()"
+  "*
+{
+  rtx addr = operands[1];
+
+  output_asm_insn (AS1 (call,%P0), operands);
 
-(define_insn "blockage"
-  [(unspec_volatile [(const_int 0)] 0)]
+  operands[2] = gen_rtx (REG, SImode, 0);
+  output_asm_insn (AS2 (mov%L2,%2,%1), operands);
+
+  operands[2] = gen_rtx (REG, SImode, 1);
+  operands[1] = adj_offsettable_operand (addr, 4);
+  output_asm_insn (AS2 (mov%L2,%2,%1), operands);
+
+  operands[1] = adj_offsettable_operand (addr, 8);
+  return AS1 (fnsave,%1);
+}")
+
+;; We use fnsave and frstor to save and restore the floating point result.
+;; These are expensive instructions and require a large space to save the
+;; FPU state.  An more complicated alternative is to use fnstenv to store
+;; the FPU environment and test whether the stack top is valid.  Store the
+;; result of the test, and if it is valid, pop and save the value.  The
+;; untyped_return would check the test and optionally push the saved value.
+
+(define_expand "untyped_return"
+  [(match_operand:BLK 0 "memory_operand" "")
+   (match_operand 1 "" "")]
   ""
-  "")
+  "
+{
+  rtx valreg1 = gen_rtx (REG, SImode, 0);
+  rtx valreg2 = gen_rtx (REG, SImode, 1);
+  rtx result = operands[0];
+
+  /* Restore the FPU state.  */
+  emit_insn (gen_update_return (change_address (result, SImode,
+						plus_constant (XEXP (result, 0),
+							       8))));
+
+  /* Reload the function value registers.  */
+  emit_move_insn (valreg1, change_address (result, SImode, XEXP (result, 0)));
+  emit_move_insn (valreg2,
+		  change_address (result, SImode,
+				  plus_constant (XEXP (result, 0), 4)));
+
+  /* Put USE insns before the return.  */
+  emit_insn (gen_rtx (USE, VOIDmode, valreg1));
+  emit_insn (gen_rtx (USE, VOIDmode, valreg2));
+
+  /* Construct the return.  */
+  expand_null_return ();
+
+  DONE;
+}")
+
+(define_insn "update_return"
+  [(unspec:SI [(match_operand:SI 0 "memory_operand" "m")] 0)]
+  ""
+  "frstor %0")
 
 ;; Insn emitted into the body of a function to return from a function.
 ;; This is only done if the function's epilogue is known to be simple.
@@ -5294,7 +5178,7 @@
 ;; It might seem that operands 0 & 1 could use predicate register_operand.
 ;; But strength reduction might offset the MEM expression.  So we let
 ;; reload put the address into %edi & %esi.
-
+;; intel1 "e" used to be "S"
 (define_insn ""
   [(set (mem:BLK (match_operand:SI 0 "address_operand" "D"))
 	(mem:BLK (match_operand:SI 1 "address_operand" "S")))
@@ -5370,6 +5254,7 @@
 ;; possible to know that the length is non-zero, and to avoid the extra
 ;; code to handle zero-length compares.
 
+;; intel1 "e" used to be "S"
 (define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=&r")
 	(compare:SI (mem:BLK (match_operand:SI 1 "address_operand" "S"))
@@ -5406,6 +5291,7 @@
   RET;
 }")
 
+;; intel1 "e" used to be "S"
 (define_insn ""
   [(set (cc0)
 	(compare:SI (mem:BLK (match_operand:SI 0 "address_operand" "S"))
@@ -5457,19 +5343,19 @@
   output_asm_insn (AS2 (bsf%L0,%1,%0), xops);
 #ifdef LOCAL_LABEL_PREFIX
   sprintf (buffer, \"jnz %sLFFSSI%d\",
-	   LOCAL_LABEL_PREFIX, ffssi_label_number);
+         LOCAL_LABEL_PREFIX, ffssi_label_number);
 #else
   sprintf (buffer, \"jnz %sLFFSSI%d\",
-	   \"\", ffssi_label_number);
+         \"\", ffssi_label_number);
 #endif
   output_asm_insn (buffer, xops);
   output_asm_insn (AS2 (mov%L0,%2,%0), xops);
 #ifdef LOCAL_LABEL_PREFIX
   sprintf (buffer, \"%sLFFSSI%d:\",
-	   LOCAL_LABEL_PREFIX, ffssi_label_number);
+         LOCAL_LABEL_PREFIX, ffssi_label_number);
 #else
   sprintf (buffer, \"%sLFFSSI%d:\",
-	   \"\", ffssi_label_number);
+         \"\", ffssi_label_number);
 #endif
   output_asm_insn (buffer, xops);
 
@@ -5503,19 +5389,19 @@
   output_asm_insn (AS2 (bsf%W0,%1,%0), xops);
 #ifdef LOCAL_LABEL_PREFIX
   sprintf (buffer, \"jnz %sLFFSHI%d\",
-	   LOCAL_LABEL_PREFIX, ffshi_label_number);
+         LOCAL_LABEL_PREFIX, ffshi_label_number);
 #else
   sprintf (buffer, \"jnz %sLFFSHI%d\",
-	   \"\", ffshi_label_number);
+         \"\", ffshi_label_number);
 #endif
   output_asm_insn (buffer, xops);
   output_asm_insn (AS2 (mov%W0,%2,%0), xops);
 #ifdef LOCAL_LABEL_PREFIX
   sprintf (buffer, \"%sLFFSHI%d:\",
-	   LOCAL_LABEL_PREFIX, ffshi_label_number);
+         LOCAL_LABEL_PREFIX, ffshi_label_number);
 #else
   sprintf (buffer, \"%sLFFSHI%d:\",
-	   \"\", ffshi_label_number);
+         \"\", ffshi_label_number);
 #endif
   output_asm_insn (buffer, xops);
 
@@ -5530,14 +5416,23 @@
 ;; the other operand a conversion.  The conversion may be SFmode or
 ;; SImode if the target mode DFmode, but only SImode if the target mode
 ;; is SFmode.
-
+;; intel1 2 changed from nonimmediate operand to general operand
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f,f")
 	(match_operator:DF 3 "binary_387_op"
 			[(match_operand:DF 1 "nonimmediate_operand" "0,fm")
-			 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
+			 (match_operand:DF 2 "general_operand" "fm,0")]))]
   "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);")
+  "* return (char *) output_387_binary_op (insn, operands);"
+  [(set (attr "type") 
+        (cond [(match_operand:DF 3 "is_mul" "") 
+                 (const_string "fpop")
+               (match_operand:DF 3 "is_div" "") 
+                 (const_string "fpdiv")
+              ]
+               (const_string "fpop")
+        )
+  )])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -5545,7 +5440,7 @@
 	   [(float:DF (match_operand:SI 1 "general_operand" "rm"))
 	    (match_operand:DF 2 "general_operand" "0")]))]
   "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);")
+  "* return (char *) output_387_binary_op (insn, operands);")
 
 (define_insn ""
   [(set (match_operand:XF 0 "register_operand" "=f,f")
@@ -5553,7 +5448,7 @@
 			[(match_operand:XF 1 "nonimmediate_operand" "0,f")
 			 (match_operand:XF 2 "nonimmediate_operand" "f,0")]))]
   "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);")
+  "* return (char *) output_387_binary_op (insn, operands);")
 
 (define_insn ""
   [(set (match_operand:XF 0 "register_operand" "=f")
@@ -5561,7 +5456,7 @@
 	   [(float:XF (match_operand:SI 1 "general_operand" "rm"))
 	    (match_operand:XF 2 "general_operand" "0")]))]
   "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);")
+  "* return (char *) output_387_binary_op (insn, operands);")
 
 (define_insn ""
   [(set (match_operand:XF 0 "register_operand" "=f,f")
@@ -5569,7 +5464,7 @@
 	   [(float_extend:XF (match_operand:SF 1 "general_operand" "fm,0"))
 	    (match_operand:XF 2 "general_operand" "0,f")]))]
   "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);")
+  "* return (char *) output_387_binary_op (insn, operands);")
 
 (define_insn ""
   [(set (match_operand:XF 0 "register_operand" "=f")
@@ -5577,7 +5472,7 @@
 	  [(match_operand:XF 1 "general_operand" "0")
 	   (float:XF (match_operand:SI 2 "general_operand" "rm"))]))]
   "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);")
+  "* return (char *) output_387_binary_op (insn, operands);")
 
 (define_insn ""
   [(set (match_operand:XF 0 "register_operand" "=f,f")
@@ -5585,8 +5480,18 @@
 	  [(match_operand:XF 1 "general_operand" "0,f")
 	   (float_extend:XF
 	    (match_operand:SF 2 "general_operand" "fm,0"))]))]
+
   "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);")
+  "* return (char *) output_387_binary_op (insn, operands);"
+  [(set (attr "type") 
+        (cond [(match_operand:DF 3 "is_mul" "") 
+                 (const_string "fpop")
+               (match_operand:DF 3 "is_div" "") 
+                 (const_string "fpdiv")
+              ]
+               (const_string "fpop")
+        )
+  )])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f,f")
@@ -5594,7 +5499,16 @@
 	   [(float_extend:DF (match_operand:SF 1 "general_operand" "fm,0"))
 	    (match_operand:DF 2 "general_operand" "0,f")]))]
   "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);")
+  "* return (char *) output_387_binary_op (insn, operands);"
+  [(set (attr "type") 
+        (cond [(match_operand:DF 3 "is_mul" "") 
+                 (const_string "fpop")
+               (match_operand:DF 3 "is_div" "") 
+                 (const_string "fpdiv")
+              ]
+               (const_string "fpop")
+        )
+  )])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -5602,7 +5516,16 @@
 	  [(match_operand:DF 1 "general_operand" "0")
 	   (float:DF (match_operand:SI 2 "general_operand" "rm"))]))]
   "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);")
+  "* return (char *) output_387_binary_op (insn, operands);"
+  [(set (attr "type") 
+        (cond [(match_operand:DF 3 "is_mul" "") 
+                 (const_string "fpop")
+               (match_operand:DF 3 "is_div" "") 
+                 (const_string "fpdiv")
+              ]
+               (const_string "fpop")
+        )
+  )])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f,f")
@@ -5611,15 +5534,34 @@
 	   (float_extend:DF
 	    (match_operand:SF 2 "general_operand" "fm,0"))]))]
   "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);")
+  "* return (char *) output_387_binary_op (insn, operands);"
+  [(set (attr "type") 
+        (cond [(match_operand:DF 3 "is_mul" "") 
+                 (const_string "fpop")
+               (match_operand:DF 3 "is_div" "") 
+                 (const_string "fpdiv")
+              ]
+               (const_string "fpop")
+        )
+  )])
 
+;; intel1 1 and 2 changed from nonimmediate operand to general operand
 (define_insn ""
   [(set (match_operand:SF 0 "register_operand" "=f,f")
 	(match_operator:SF 3 "binary_387_op"
-			[(match_operand:SF 1 "nonimmediate_operand" "0,fm")
-			 (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
+			[(match_operand:SF 1 "general_operand" "0,fm")
+			 (match_operand:SF 2 "general_operand" "fm,0")]))]
   "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);")
+  "* return (char *) output_387_binary_op (insn, operands);"
+  [(set (attr "type") 
+        (cond [(match_operand:DF 3 "is_mul" "") 
+                 (const_string "fpop")
+               (match_operand:DF 3 "is_div" "") 
+                 (const_string "fpdiv")
+              ]
+               (const_string "fpop")
+        )
+  )])
 
 (define_insn ""
   [(set (match_operand:SF 0 "register_operand" "=f")
@@ -5627,7 +5569,16 @@
 	  [(float:SF (match_operand:SI 1 "general_operand" "rm"))
 	   (match_operand:SF 2 "general_operand" "0")]))]
   "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);")
+  "* return (char *) output_387_binary_op (insn, operands);"
+  [(set (attr "type") 
+        (cond [(match_operand:DF 3 "is_mul" "") 
+                 (const_string "fpop")
+               (match_operand:DF 3 "is_div" "") 
+                 (const_string "fpdiv")
+              ]
+               (const_string "fpop")
+        )
+  )])
 
 (define_insn ""
   [(set (match_operand:SF 0 "register_operand" "=f")
@@ -5635,7 +5586,16 @@
 	  [(match_operand:SF 1 "general_operand" "0")
 	   (float:SF (match_operand:SI 2 "general_operand" "rm"))]))]
   "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);")
+  "* return (char *) output_387_binary_op (insn, operands);"
+  [(set (attr "type") 
+        (cond [(match_operand:DF 3 "is_mul" "") 
+                 (const_string "fpop")
+               (match_operand:DF 3 "is_div" "") 
+                 (const_string "fpdiv")
+              ]
+               (const_string "fpop")
+        )
+  )])
 
 (define_expand "strlensi"
   [(parallel [(set (match_dup 4)
@@ -5677,3 +5637,812 @@
   output_asm_insn (AS2 (mov%L0,%1,%0), xops);
   return \"repnz\;scas%B2\";
 }")
+
+;; intel1 peepholes
+;; change fstp mem1
+;;        fld  mem1
+;;        fop  mem2
+;; to
+;;        fst  mem1
+;;        fop  mem2
+
+(define_peephole
+ [(set (match_operand:DF 0 "memory_operand" "g")
+       (reg:DF 8))
+  (set (reg:DF 8)
+       (match_operand:DF 1 "memory_operand" "g"))
+  (set (reg:DF 8)
+	(mult:DF (reg:DF 8)
+		 (match_dup 0)))
+ ]
+ "TARGET_80387"
+ "*
+ {
+  extern int flag_float_store;
+  if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
+    {
+      if (flag_float_store)
+        {
+          output_asm_insn (AS1 (fstpl,%0),operands);
+          output_asm_insn (AS1 (fldl,%1),operands);
+          return AS1(fmull,%0);
+        }
+      output_asm_insn (AS1 (fstl,%0),operands);
+      return AS1(fmull,%1);
+    }
+  else
+    {
+      output_asm_insn (AS1 (fstl,%0),operands);
+      output_asm_insn (AS1 (fldl,%1),operands);
+      return AS1(fmull,%0);
+    }
+ }"
+);
+ 
+ 
+ 
+(define_peephole
+ [(set (match_operand:DF 0 "memory_operand" "g")
+       (reg:DF 8))
+  (set (reg:DF 8)
+       (match_operand:DF 1 "memory_operand" "g"))
+  (set (reg:DF 8)
+	(plus:DF (reg:DF 8)
+		 (match_dup 0)))
+ ]
+ "TARGET_80387"
+ "*
+ {
+  extern int flag_float_store;
+  if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
+    {
+      if (flag_float_store)
+        {
+          output_asm_insn (AS1 (fstpl,%0),operands);
+          output_asm_insn (AS1 (fldl,%1),operands);
+          return AS1(faddl,%0);
+        }
+      output_asm_insn (AS1 (fstl,%0),operands);
+      return AS1(faddl,%1);
+    }
+  else
+    {
+      output_asm_insn (AS1 (fstl,%0),operands);
+      output_asm_insn (AS1 (fldl,%1),operands);
+      return AS1(faddl,%0);
+    }
+ }"
+);
+ 
+ 
+ 
+(define_peephole
+ [(set (match_operand:DF 0 "memory_operand" "g")
+       (reg:DF 8))
+  (set (reg:DF 8)
+       (match_operand:DF 1 "memory_operand" "g"))
+  (set (reg:DF 8)
+	(minus:DF (reg:DF 8)
+		 (match_dup 0)))
+ ]
+ "TARGET_80387"
+ "*
+ {
+  extern int flag_float_store;
+  if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
+    {
+      if (flag_float_store)
+        {
+          output_asm_insn (AS1 (fstpl,%0),operands);
+          output_asm_insn (AS1 (fldl,%1),operands);
+          return AS1(fsubl,%0);
+        }
+      output_asm_insn (AS1 (fstl,%0),operands);
+      return AS1(fsubrl,%1);
+    }
+  else
+    {
+      output_asm_insn (AS1 (fstl,%0),operands);
+      output_asm_insn (AS1 (fldl,%1),operands);
+      return AS1(fsubl,%0);
+    }
+ }"
+);
+ 
+ 
+ 
+(define_peephole
+ [(set (match_operand:DF 0 "memory_operand" "g")
+       (reg:DF 8))
+  (set (reg:DF 8)
+       (match_operand:DF 1 "memory_operand" "g"))
+  (set (reg:DF 8)
+	(div:DF (reg:DF 8)
+		 (match_dup 0)))
+ ]
+ "TARGET_80387"
+ "*
+ {
+  extern int flag_float_store;
+  if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
+    {
+      if (flag_float_store)
+        {
+          output_asm_insn (AS1 (fstpl,%0),operands);
+          output_asm_insn (AS1 (fldl,%1),operands);
+          return AS1(fdivl,%0);
+        }
+      output_asm_insn (AS1 (fstl,%0),operands);
+      return AS1(fdivrl,%1);
+    }
+  else
+    {
+      output_asm_insn (AS1 (fstl,%0),operands);
+      output_asm_insn (AS1 (fldl,%1),operands);
+      return AS1(fdivl,%0);
+    }
+ }"
+);
+ 
+ 
+(define_peephole
+ [(set (match_operand:SF 0 "memory_operand" "g")
+       (reg:SF 8))
+  (set (reg:SF 8)
+       (match_operand:SF 1 "memory_operand" "g"))
+  (set (reg:SF 8)
+	(mult:SF (reg:SF 8)
+		 (match_dup 0)))
+ ]
+ "TARGET_80387"
+ "*
+ {
+  extern int flag_float_store;
+  if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
+    {
+      if (flag_float_store)
+        {
+          output_asm_insn (AS1 (fstps,%0),operands);
+          output_asm_insn (AS1 (flds,%1),operands);
+          return AS1(fmuls,%0);
+        }
+      output_asm_insn (AS1 (fsts,%0),operands);
+      return AS1(fmuls,%1);
+    }
+  else
+    {
+      output_asm_insn (AS1 (fsts,%0),operands);
+      output_asm_insn (AS1 (flds,%1),operands);
+      return AS1(fmuls,%0);
+    }
+ }"
+);
+ 
+ 
+ 
+(define_peephole
+ [(set (match_operand:SF 0 "memory_operand" "g")
+       (reg:SF 8))
+  (set (reg:SF 8)
+       (match_operand:SF 1 "memory_operand" "g"))
+  (set (reg:SF 8)
+	(plus:SF (reg:SF 8)
+		 (match_dup 0)))
+ ]
+ "TARGET_80387"
+ "*
+ {
+  extern int flag_float_store;
+  if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
+    {
+      if (flag_float_store)
+        {
+          output_asm_insn (AS1 (fstps,%0),operands);
+          output_asm_insn (AS1 (flds,%1),operands);
+          return AS1(fadds,%0);
+        }
+      output_asm_insn (AS1 (fsts,%0),operands);
+      return AS1(fadds,%1);
+    }
+  else
+    {
+      output_asm_insn (AS1 (fsts,%0),operands);
+      output_asm_insn (AS1 (flds,%1),operands);
+      return AS1(fadds,%0);
+    }
+ }"
+);
+ 
+ 
+ 
+(define_peephole
+ [(set (match_operand:SF 0 "memory_operand" "g")
+       (reg:SF 8))
+  (set (reg:SF 8)
+       (match_operand:SF 1 "memory_operand" "g"))
+  (set (reg:SF 8)
+	(minus:SF (reg:SF 8)
+		 (match_dup 0)))
+ ]
+ "TARGET_80387"
+ "*
+ {
+  extern int flag_float_store;
+  if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
+    {
+      if (flag_float_store)
+        {
+          output_asm_insn (AS1 (fstps,%0),operands);
+          output_asm_insn (AS1 (flds,%1),operands);
+          return AS1(fsubs,%0);
+        }
+      output_asm_insn (AS1 (fsts,%0),operands);
+      return AS1(fsubrs,%1);
+    }
+  else
+    {
+      output_asm_insn (AS1 (fsts,%0),operands);
+      output_asm_insn (AS1 (flds,%1),operands);
+      return AS1(fsubs,%0);
+    }
+ }"
+);
+ 
+ 
+ 
+(define_peephole
+ [(set (match_operand:SF 0 "memory_operand" "g")
+       (reg:SF 8))
+  (set (reg:SF 8)
+       (match_operand:SF 1 "memory_operand" "g"))
+  (set (reg:SF 8)
+	(div:SF (reg:SF 8)
+		 (match_dup 0)))
+ ]
+ "TARGET_80387"
+ "*
+ {
+  extern int flag_float_store;
+  if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
+    {
+      if (flag_float_store)
+        {
+          output_asm_insn (AS1 (fstps,%0),operands);
+          output_asm_insn (AS1 (flds,%1),operands);
+          return AS1(fdivs,%0);
+        }
+      output_asm_insn (AS1 (fsts,%0),operands);
+      return AS1(fdivrs,%1);
+    }
+  else
+    {
+      output_asm_insn (AS1 (fsts,%0),operands);
+      output_asm_insn (AS1 (flds,%1),operands);
+      return AS1(fdivs,%0);
+    }
+ }"
+);
+ 
+ 
+;; change fstp mem1
+;;        fld  mem1
+;; to
+;;        fst  mem1
+ 
+(define_peephole
+ [(set (match_operand:DF 0 "memory_operand" "g")
+       (reg:DF 8))
+  (set (reg:DF 8)
+       (match_dup 0))]
+ "TARGET_80387"
+ "*
+ {
+  extern int flag_float_store;
+  if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
+    {
+      if(!MEM_VOLATILE_P (operands[0]) && !flag_float_store)
+        {
+          return AS1 (fstl,%0);
+        }
+      else
+        {
+         output_asm_insn (AS1 (fstpl,%0),operands);
+         return AS1 (fldl,%0);
+        }
+    }
+  else
+    {
+      output_asm_insn (AS1 (fstl,%0),operands);
+      return AS1 (fldl,%0);
+    }
+ }"
+);
+
+(define_peephole
+ [(set (match_operand:SF 0 "memory_operand" "g")
+       (reg:SF 8))
+  (set (reg:SF 8)
+       (match_dup 0))]
+ "TARGET_80387"
+ "*
+ {
+  extern int flag_float_store;
+  if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
+    {
+      if(!MEM_VOLATILE_P (operands[0]) && !flag_float_store)
+        {
+          return AS1 (fsts,%0);
+        }
+      else
+        {
+         output_asm_insn (AS1 (fstps,%0),operands);
+         return AS1 (flds,%0);
+        }
+    }
+  else
+    {
+      output_asm_insn (AS1 (fsts,%0),operands);
+      return AS1 (flds,%0);
+    }
+ }"
+);
+
+(define_peephole
+ [(set (match_operand:SF 0 "memory_operand" "g")
+       (reg:SF 8))
+  (set (reg:DF 8)
+       (float_extend:DF (match_dup 0)))]
+ "TARGET_80387"
+ "*
+ {
+  extern int flag_float_store;
+  if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) && !flag_float_store)
+    {
+      return AS1 (fsts,%0);
+    }
+  else
+    {
+      output_asm_insn (AS1 (fsts,%0),operands);
+      return AS1 (flds,%0);
+    }
+ }"
+);
+
+;; see if compare can be deleted
+(define_peephole
+  [
+   (set (cc0)
+	(compare (const_int 0)
+		 (match_operand:SI 0 "general_operand" "g")))
+   (set (pc)
+	(if_then_else (ne (cc0)
+			  (const_int 0))
+			  (label_ref (match_operand 1 "" ""))
+		      (pc)))
+  ]
+  ""
+  "*
+{
+      if(!last_to_set_cc(operands[0]),insn)
+      {
+        operands[2] = const0_rtx;
+        output_asm_insn (AS2 (cmp%L0,%2,%0),operands);
+        return \"jne %l1\";
+      }
+      else
+      {
+        return \"jne %l1\";
+      }
+}");
+  
+(define_peephole
+  [
+   (set (cc0)
+	(compare (match_operand:SI 0 "general_operand" "g")
+		 (const_int 0)))
+   (set (pc)
+	(if_then_else (ne (cc0)
+			  (const_int 0))
+			  (label_ref (match_operand 1 "" ""))
+		      (pc)))
+  ]
+  ""
+  "*
+{
+      if(!last_to_set_cc(operands[0],insn))
+      {
+        operands[2] = const0_rtx;
+        output_asm_insn (AS2 (cmp%L0,%2,%0),operands);
+        return \"jne %l1\";
+      }
+      else
+      {
+        return \"jne %l1\";
+      }
+}");
+
+;; optimization of sign_extend combined with and
+(define_peephole
+  [
+   (set (match_operand:HI 0 "register_operand" "")
+	(and:HI (match_dup 0)
+		(match_operand:HI 1 "immediate_operand" "")))
+   (set (match_operand:SI 2 "register_operand" "")
+	(sign_extend:SI
+	 (match_dup 0)))
+  ]
+  ""
+  "*
+{
+      int no_sign_extend = 0;
+      rtx note;
+      if ((INTVAL (operands[1]) & 0x8000) == 0)
+        { /* Don't need to do sign extend */
+          no_sign_extend = 1;
+        }
+      CC_STATUS_INIT;
+      if (no_sign_extend)
+        {
+	  if (REGNO (operands[0]) == REGNO (operands[2]))
+	    {
+              operands [0] = gen_rtx (REG, SImode, REGNO (operands[0]));
+	      output_asm_insn (AS2 (and%L0,%1,%0), operands);
+	    }
+	  else
+	    {
+	      output_asm_insn (AS2 (and%W0,%1,%w0), operands);
+              operands [0] = gen_rtx (REG, SImode, REGNO (operands[0]));
+	      output_asm_insn (AS2 (mov%L0,%0,%2), operands);
+	      operands [1] = gen_rtx (CONST_INT, 0, 0xffff);
+	      output_asm_insn (AS2 (and%L0,%1,%2), operands);
+	    }
+	  RET;
+        }
+      /* Can we ignore the upper byte? */
+      else if (QI_REG_P (operands[0])
+	  && (INTVAL (operands[1]) & 0xff00) == 0xff00)
+	{
+	  if ((INTVAL (operands[1]) & 0xff) == 0)
+	    {
+	      operands[1] = const0_rtx;
+	      output_asm_insn (AS2 (mov%B0,%1,%b0), operands);
+	    }
+	  else
+	    {
+	      operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
+	      output_asm_insn (AS2 (and%B0,%1,%b0), operands);
+	    }
+	}
+      else if (!no_sign_extend && QI_REG_P (operands[0]) 
+               && (INTVAL (operands[1]) & 0xff) == 0xff)
+	{
+	  if ((INTVAL (operands[1]) & 0xff00) == 0)
+	    {
+	      operands[1] = const0_rtx;
+	      output_asm_insn (AS2 (mov%B0,%1,%h0), operands);
+	    }
+
+	  operands[1] = GEN_INT ((INTVAL (operands[1]) >> 8) & 0xff);
+	  output_asm_insn (AS2 (and%B0,%1,%b0), operands);
+	}
+  if (REGNO (operands[2]) == 0 && REGNO (operands[0]) == 0)
+#ifdef INTEL_SYNTAX
+    return \"cwde\";
+#else
+    return \"cwtl\";
+#endif
+
+#ifdef INTEL_SYNTAX
+  return AS2 (movsx,%0,%2);
+#else
+  return AS2 (movs%W0%L0,%0,%2);
+#endif
+}");
+
+(define_peephole
+  [
+   (set (match_operand:HI 0 "register_operand" "")
+	(match_operand:HI 1 "memory_operand" ""))
+   (set (match_dup 0)
+	(and:HI (match_dup 0)
+		(match_operand:HI 2 "immediate_operand" "")))
+   (set (match_operand:SI 3 "register_operand" "")
+	(sign_extend:SI
+	 (match_dup 0)))
+  ]
+  ""
+  "*
+{
+      int no_sign_extend = 0;
+      if ((INTVAL (operands[2]) & 0xff00) == 0
+          && QI_REG_P (operands[0]))
+        {
+          output_asm_insn (AS2 (mov%B0,%b1,%b0), operands);
+        }
+      else
+        {
+          output_asm_insn (AS2 (mov%W0,%1,%0), operands);
+        }
+      if ((INTVAL (operands[2]) & 0x8000) == 0)
+        { /* Don't need to do sign extend */
+          no_sign_extend = 1;
+        }
+      CC_STATUS_INIT;
+      if (no_sign_extend)
+        {
+	  if (REGNO (operands[0]) == REGNO (operands[3]))
+	    {
+              operands [0] = gen_rtx (REG, SImode, REGNO (operands[0]));
+	      output_asm_insn (AS2 (and%L0,%2,%0), operands);
+	    }
+	  else
+	    {
+	      output_asm_insn (AS2 (and%W0,%2,%w0), operands);
+              operands [0] = gen_rtx (REG, SImode, REGNO (operands[0]));
+	      output_asm_insn (AS2 (mov%L0,%0,%3), operands);
+	      operands [2] = gen_rtx (CONST_INT, 0, 0xffff);
+	      output_asm_insn (AS2 (and%L0,%2,%3), operands);
+	    }
+	  RET;
+        }
+      /* Can we ignore the upper byte? */
+      else if (QI_REG_P (operands[0])
+	  && (INTVAL (operands[2]) & 0xff00) == 0xff00)
+	{
+	  if ((INTVAL (operands[2]) & 0xff) == 0)
+	    {
+	      operands[2] = const0_rtx;
+	      output_asm_insn (AS2 (mov%B0,%2,%b0), operands);
+	    }
+	  else
+	    {
+	      operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
+	      output_asm_insn (AS2 (and%B0,%2,%b0), operands);
+	    }
+	}
+      else if (!no_sign_extend && QI_REG_P (operands[0]) 
+               && (INTVAL (operands[2]) & 0xff) == 0xff)
+	{
+	  if ((INTVAL (operands[2]) & 0xff00) == 0)
+	    {
+	      operands[2] = const0_rtx;
+	      output_asm_insn (AS2 (mov%B0,%2,%h0), operands);
+	    }
+
+	  operands[1] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff);
+	  output_asm_insn (AS2 (and%B0,%2,%b0), operands);
+	}
+      else
+        {
+          output_asm_insn (AS2 (and%W0,%2,%0), operands);
+        }
+  if (REGNO (operands[3]) == 0 && REGNO (operands[0]) == 0)
+#ifdef INTEL_SYNTAX
+    return \"cwde\";
+#else
+    return \"cwtl\";
+#endif
+
+#ifdef INTEL_SYNTAX
+  return AS2 (movsx,%0,%3);
+#else
+  return AS2 (movs%W0%L0,%0,%3);
+#endif
+}");
+
+(define_peephole
+  [
+   (set (match_operand:HI 0 "register_operand" "")
+	(sign_extend:HI
+	 (match_operand:QI 1 "memory_operand" "")))
+   (set (match_dup 0)
+	(and:HI (match_dup 0)
+		(match_operand:HI 2 "immediate_operand" "")))
+   (set (match_operand:SI 3 "register_operand" "")
+	(sign_extend:SI
+	 (match_dup 0)))
+  ]
+  ""
+  "*
+{
+      int no_sign_extend = 0;
+      if ((INTVAL (operands[2]) & 0xff00) == 0
+          && QI_REG_P (operands[0]))
+        {
+          output_asm_insn (AS2 (mov%B0,%b1,%b0), operands);
+        }
+      else
+        {
+#ifdef INTEL_SYNTAX
+          output_asm_insn( AS2 (movsx,%1,%0), operands);
+#else
+          output_asm_insn( AS2 (movs%B0%W0,%1,%0), operands);
+#endif
+        }
+      if ((INTVAL (operands[2]) & 0x8000) == 0)
+        { /* Don't need to do sign extend */
+          no_sign_extend = 1;
+        }
+      CC_STATUS_INIT;
+      if (no_sign_extend)
+        {
+	  if (REGNO (operands[0]) == REGNO (operands[3]))
+	    {
+              operands [0] = gen_rtx (REG, SImode, REGNO (operands[0]));
+	      output_asm_insn (AS2 (and%L0,%2,%0), operands);
+	    }
+	  else
+	    {
+	      output_asm_insn (AS2 (and%W0,%2,%w0), operands);
+              operands [0] = gen_rtx (REG, SImode, REGNO (operands[0]));
+	      output_asm_insn (AS2 (mov%L0,%0,%3), operands);
+	      operands [2] = gen_rtx (CONST_INT, 0, 0xffff);
+	      output_asm_insn (AS2 (and%L0,%2,%3), operands);
+	    }
+	  RET;
+        }
+      /* Can we ignore the upper byte? */
+      else if (QI_REG_P (operands[0])
+	  && (INTVAL (operands[2]) & 0xff00) == 0xff00)
+	{
+	  if ((INTVAL (operands[2]) & 0xff) == 0)
+	    {
+	      operands[2] = const0_rtx;
+	      output_asm_insn (AS2 (mov%B0,%2,%b0), operands);
+	    }
+	  else
+	    {
+	      operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
+	      output_asm_insn (AS2 (and%B0,%2,%b0), operands);
+	    }
+	}
+      else if (!no_sign_extend && QI_REG_P (operands[0]) 
+               && (INTVAL (operands[2]) & 0xff) == 0xff)
+	{
+	  if ((INTVAL (operands[2]) & 0xff00) == 0)
+	    {
+	      operands[2] = const0_rtx;
+	      output_asm_insn (AS2 (mov%B0,%2,%h0), operands);
+	    }
+
+	  operands[1] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff);
+	  output_asm_insn (AS2 (and%B0,%2,%b0), operands);
+	}
+      else
+        {
+          output_asm_insn (AS2 (and%W0,%2,%0), operands);
+        }
+  if (REGNO (operands[3]) == 0 && REGNO (operands[0]) == 0)
+#ifdef INTEL_SYNTAX
+    return \"cwde\";
+#else
+    return \"cwtl\";
+#endif
+
+#ifdef INTEL_SYNTAX
+  return AS2 (movsx,%0,%3);
+#else
+  return AS2 (movs%W0%L0,%0,%3);
+#endif
+}");
+
+(define_peephole
+  [
+   (set (match_operand:HI 0 "register_operand" "")
+	(sign_extend:HI
+	 (match_operand:QI 1 "memory_operand" "")))
+   (set (match_dup 0)
+	(and:HI (match_dup 0)
+		(match_operand:HI 2 "immediate_operand" "")))
+  ]
+  ""
+  "*
+{
+      if ((INTVAL (operands[2]) & 0xff00) == 0
+          && QI_REG_P (operands[0]))
+        {
+          output_asm_insn (AS2 (mov%B0,%b1,%b0), operands);
+        }
+      else
+        {
+#ifdef INTEL_SYNTAX
+          output_asm_insn( AS2 (movsx,%1,%0), operands);
+#else
+          output_asm_insn( AS2 (movs%B0%W0,%1,%0), operands);
+#endif
+        }
+      /* Can we ignore the upper byte? */
+      if (QI_REG_P (operands[0])
+	  && (INTVAL (operands[2]) & 0xff00) == 0xff00)
+	{
+	  if ((INTVAL (operands[2]) & 0xff) == 0)
+	    {
+	      operands[2] = const0_rtx;
+	      output_asm_insn (AS2 (mov%B0,%2,%b0), operands);
+	    }
+	  else
+	    {
+	      operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
+	      output_asm_insn (AS2 (and%B0,%2,%b0), operands);
+	    }
+	}
+      else if (QI_REG_P (operands[0]) 
+               && (INTVAL (operands[2]) & 0xff) == 0xff)
+	{
+	  if ((INTVAL (operands[2]) & 0xff00) == 0)
+	    {
+	      operands[2] = const0_rtx;
+	      output_asm_insn (AS2 (mov%B0,%2,%h0), operands);
+	    }
+
+	  operands[1] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff);
+	  output_asm_insn (AS2 (and%B0,%2,%b0), operands);
+	}
+      else
+        {
+          output_asm_insn (AS2 (and%W0,%2,%0), operands);
+        }
+   RET;
+}");
+
+(define_peephole
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+	(sign_extend:SI
+	 (match_operand:QI 1 "memory_operand" "")))
+   (set (match_dup 0)
+	(and:SI (match_dup 0)
+		(match_operand:SI 2 "immediate_operand" "")))
+  ]
+  ""
+  "*
+{
+      if ((INTVAL (operands[2]) & 0xffffff00) == 0
+          && QI_REG_P (operands[0]))
+        {
+          output_asm_insn (AS2 (mov%B0,%b1,%b0), operands);
+        }
+      else
+        {
+#ifdef INTEL_SYNTAX
+          output_asm_insn( AS2 (movsx,%1,%0), operands);
+#else
+          output_asm_insn( AS2 (movs%B0%L0,%1,%0), operands);
+#endif
+        }
+      output_asm_insn (AS2 (and%L0,%2,%0), operands);
+   RET;
+}");
+
+(define_peephole
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+	(sign_extend:SI
+	 (match_operand:HI 1 "memory_operand" "")))
+   (set (match_dup 0)
+	(and:SI (match_dup 0)
+		(match_operand:SI 2 "immediate_operand" "")))
+  ]
+  ""
+  "*
+{
+      if ((INTVAL (operands[2]) & 0xffffff00) == 0
+          && QI_REG_P (operands[0]))
+        {
+          output_asm_insn (AS2 (mov%B0,%b1,%b0), operands);
+        }
+      else if ((INTVAL (operands[2]) & 0xffff0000) == 0)
+        {
+          output_asm_insn (AS2 (mov%W0,%h1,%h0), operands);
+        }
+      else
+        {
+#ifdef INTEL_SYNTAX
+          output_asm_insn( AS2 (movsx,%1,%0), operands);
+#else
+          output_asm_insn( AS2 (movs%B0%W0,%1,%0), operands);
+#endif
+        }
+      output_asm_insn (AS2 (and%L0,%2,%0), operands);
+   RET;
+}");
diff -r -u -H -N gcc-2.6.3/config/i386/osfrose.h gcc-i2.6.3/config/i386/osfrose.h
--- gcc-2.6.3/config/i386/osfrose.h	Wed Oct 26 17:14:11 1994
+++ gcc-i2.6.3/config/i386/osfrose.h	Wed Feb 15 22:46:52 1995
@@ -468,6 +468,10 @@
    defined, is executed once just after all the command options have
    been parsed.  */
 
+#ifdef OVERRIDE_OPTIONS
+#undef OVERRIDE_OPTIONS
+#endif
+
 #undef  SUBTARGET_OVERRIDE_OPTIONS
 #define SUBTARGET_OVERRIDE_OPTIONS					\
 {									\
diff -r -u -H -N gcc-2.6.3/config.sub gcc-i2.6.3/config.sub
--- gcc-2.6.3/config.sub	Wed Oct 26 14:23:05 1994
+++ gcc-i2.6.3/config.sub	Wed Feb 15 23:11:03 1995
@@ -120,7 +120,7 @@
 	# Recognize the basic CPU types without company name.
 	# Some are omitted here because they have special meanings below.
 	tahoe | i[345]86 | i860 | m68k | m68000 | m88k | ns32k | arm | pyramid \
-		| tron | a29k | 580 | i960 | h8300 | hppa1.0 | hppa1.1 \
+		| pentium | tron | a29k | 580 | i960 | h8300 | hppa1.0 | hppa1.1 \
 		| alpha | we32k | ns16k | clipper | sparclite | i370 | sh \
 		| powerpc | sparc64 | 1750a | dsp16xx | mips64 | mipsel \
 		| pdp11 | mips64el | mips64orion | mips64orionel )
@@ -133,7 +133,7 @@
 		;;
 	# Recognize the basic CPU types with company name.
 	vax-* | tahoe-* | i[345]86-* | i860-* | m68k-* | m68000-* | m88k-* \
-	      | sparc-* | ns32k-* | fx80-* | arm-* | c[123]* \
+	      | pentium-* | sparc-* | ns32k-* | fx80-* | arm-* | c[123]* \
 	      | mips-* | pyramid-* | tron-* | a29k-* | romp-* | rs6000-* \
 	      | none-* | 580-* | cray2-* | h8300-* | i960-* | xmp-* | ymp-* \
 	      | hppa1.0-* | hppa1.1-* | alpha-* | we32k-* | cydra-* | ns16k-* \
@@ -300,18 +300,34 @@
 		basic_machine=`echo $1 | sed -e 's/86.*/86-unknown/'`
 		os=-sysv32
 		;;
+	pentiumv32)
+		basic_machine=`echo $1 | sed -e 's/pentium.*/pentium-unknown/'`
+		os=-sysv32
+		;;
 	i[345]86v4*)
 		basic_machine=`echo $1 | sed -e 's/86.*/86-unknown/'`
 		os=-sysv4
 		;;
+  pentiumv4*)
+      basic_machine=`echo $1 | sed -e 's/pentium.*/pentium-unknown/'`
+      os=-sysv4
+      ;;
 	i[345]86v)
 		basic_machine=`echo $1 | sed -e 's/86.*/86-unknown/'`
 		os=-sysv
 		;;
+  pentiumv)
+      basic_machine=`echo $1 | sed -e 's/pentium.*/pentium-unknown/'`
+      os=-sysv
+      ;;
 	i[345]86sol2)
 		basic_machine=`echo $1 | sed -e 's/86.*/86-unknown/'`
 		os=-solaris2
 		;;
+  pentiumsol2)
+      basic_machine=`echo $1 | sed -e 's/pentium.*/pentium-unknown/'`
+      os=-solaris2
+      ;;
 	iris | iris4d)
 		basic_machine=mips-sgi
 		case $os in
diff -r -u -H -N gcc-2.6.3/configure gcc-i2.6.3/configure
--- gcc-2.6.3/configure	Wed Nov 23 17:26:27 1994
+++ gcc-i2.6.3/configure	Wed Feb 15 23:56:29 1995
@@ -664,7 +664,7 @@
 		xm_file=i370/xm-mvs.h
 		out_file=i370/mvs370.c
 		;;
-	i[345]86-ibm-aix*)		# IBM PS/2 running AIX
+	pentium-ibm-aix* | i[345]86-ibm-aix*)		# IBM PS/2 running AIX
 		cpu_type=i386
                 if [ x$gas = xyes ]
 		then
@@ -685,7 +685,7 @@
 		tm_file=i386/sysv4.h
 		tmake_file=t-svr4
 		;;
-	i[345]86-next-*)
+	pentium-next-* | i[345]86-next-*)
 		cpu_type=i386
 		tm_file=i386/next.h
 		out_file=i386/next.c
@@ -693,7 +693,7 @@
 		tmake_file=i386/t-next
 		xmake_file=i386/x-next
 		;;
-	i[345]86-sequent-bsd*) 		# 80386 from Sequent
+	pentium-sequent-bsd* | i[345]86-sequent-bsd*) 		# 80386 from Sequent
 		cpu_type=i386
 		use_collect2=yes
 		if [ x$gas = xyes ]
@@ -703,7 +703,7 @@
 			tm_file=i386/sequent.h
 		fi
 		;;
-	i[345]86-sequent-ptx1*)
+	pentium-sequent-ptx1* | i[345]86-sequent-ptx1*)
 		cpu_type=i386
 		xm_file=i386/xm-sysv3.h
 		xmake_file=i386/x-sysv3
@@ -730,7 +730,7 @@
 		tm_file=i386/sun.h
 		use_collect2=yes
 		;;
-	i[345]86-*-bsdi* | i[345]86-*-bsd386*)
+	pentium-*-bsd* | i[345]86-*-bsdi* | i[345]86-*-bsd386*)
 		cpu_type=i386
 		tm_file=i386/bsd386.h
 #		tmake_file=t-libc-ok
@@ -742,21 +742,21 @@
 # Next line turned off because both 386BSD and BSD/386 use GNU ld.
 #		use_collect2=yes
 		;;
-	i[345]86-*-freebsd*)
+	pentium-*-freebsd* | i[345]86-*-freebsd*)
 		cpu_type=i386
 		tm_file=i386/freebsd.h
 		# On FreeBSD, the headers are already ok.
 		fixincludes=Makefile.in
 		xmake_file=i386/x-freebsd
 		;;
-	i[345]86-*-netbsd*)
+	pentium-*-netbsd* | i[345]86-*-netbsd*)
 		cpu_type=i386
 		tm_file=i386/netbsd-i386.h
 		# On NetBSD, the headers are already okay.
 		fixincludes=Makefile.in
 		xmake_file=x-netbsd
 		;;
-	i[345]86-*-gnu*)
+	pentium-*-gnu* | i[345]86-*-gnu*)
 		cpu_type=i386
 		xm_file=i386/xm-gnu.h
 		tm_file=i386/gnu.h
@@ -790,7 +790,7 @@
 		install_headers_dir=install-headers-cpio
 		broken_install=yes
 		;;
-	i[345]86-*-linux*)		# Intel 80386's running Linux
+	pentium-*-linux* | i[345]86-*-linux*)		# Intel 80386's running Linux
 		cpu_type=i386
 		xm_file=i386/xm-linux.h
 		xmake_file=i386/x-linux
@@ -803,7 +803,7 @@
 		fixincludes=Makefile.in #On Linux, the headers are ok already.
 		broken_install=yes
 		;;
-	i[345]86-*-lynxos*)
+	pentium-*-lynxos* | i[345]86-*-lynxos*)
 		cpu_type=i386
 		if [ x$gas = xyes ]
 		then
@@ -814,13 +814,13 @@
 		xm_file=xm-lynx.h
 		xmake_file=x-lynx
 		;;
-	i[345]86-*-mach*)
+	pentium-*-mach* | i[345]86-*-mach*)
 		cpu_type=i386
 		tm_file=i386/mach.h
 #		tmake_file=t-libc-ok
 		use_collect2=yes
 		;;
-	i[345]86-*-osfrose*)		# 386 using OSF/rose
+	pentium-*-osfrose* | i[345]86-*-osfrose*)		# 386 using OSF/rose
 		cpu_type=i386
                 if [ x$elf = xyes ]
 		then
@@ -876,7 +876,7 @@
 		fixincludes=fixinc.svr4
 		broken_install=yes
 		;;
-	i[345]86-*-sysv4*)		# Intel 80386's running system V.4
+	pentium-*-sysv4* | i[345]86-*-sysv4*)	# Intel 80386's running system V.4
 		cpu_type=i386
 		xm_file=i386/xm-sysv4.h
 		if [ x$stabs = xyes ]
@@ -888,7 +888,7 @@
 		tmake_file=t-svr4
 		xmake_file=x-svr4
 		;;
-	i[345]86-*-sysv*)		# Intel 80386's running system V
+	pentium-*-sysv* | i[345]86-*-sysv*)		# Intel 80386's running system V
 		cpu_type=i386
 		xm_file=i386/xm-sysv3.h
 		xmake_file=i386/x-sysv3
@@ -907,7 +907,7 @@
 			extra_parts="crtbegin.o crtend.o"
 		fi
 		;;
-	i[345]86-*-winnt3*)
+	pentium-*-winnt3* | i[345]86-*-winnt3*)
 		cpu_type=i386
 		tm_file=i386/winnt.h
 		out_file=i386/i386.c
@@ -1896,10 +1896,16 @@
 	esac
 
 	# Distinguish i386 from i486/i586.
-	# ??? For the moment we treat i586 as an i486.
+	# ??? For the moment we treat i586 as an i486. (NOT!)
 	# Also, do not run mips-tfile on MIPS if using gas.
 	case $machine in
-	i[45]86-*-*)
+	pentium-*-*)
+		target_cpu_default=4
+		;;
+	i586-*-*)
+		target_cpu_default=4
+		;;
+	i486-*-*)
 		target_cpu_default=2
 		;;
 	mips-*-*)
diff -r -u -H -N gcc-2.6.3/cp/parse.c gcc-i2.6.3/cp/parse.c
--- gcc-2.6.3/cp/parse.c	Fri Oct 14 14:51:23 1994
+++ gcc-i2.6.3/cp/parse.c	Tue Dec 20 16:53:24 1994
@@ -190,7 +190,7 @@
 
 
 
-#define	YYFINAL		1356
+#define	YYFINAL		1350
 #define	YYFLAG		-32768
 #define	YYNTBASE	106
 
@@ -257,59 +257,59 @@
    630,   635,   640,   642,   646,   650,   654,   658,   662,   666,
    670,   674,   678,   682,   686,   690,   694,   698,   702,   706,
    710,   714,   718,   724,   728,   732,   734,   737,   741,   743,
-   745,   747,   749,   751,   753,   755,   758,   761,   765,   767,
-   769,   771,   775,   777,   779,   781,   783,   787,   791,   792,
-   797,   798,   805,   808,   813,   816,   819,   821,   826,   828,
-   836,   844,   852,   860,   865,   870,   873,   876,   878,   883,
-   886,   889,   892,   898,   902,   908,   912,   917,   924,   926,
-   929,   931,   934,   936,   938,   940,   943,   944,   947,   950,
-   954,   958,   962,   966,   970,   973,   976,   978,   980,   982,
-   985,   988,   991,   994,   996,   998,  1000,  1002,  1005,  1008,
-  1012,  1016,  1021,  1023,  1026,  1029,  1031,  1033,  1036,  1039,
-  1041,  1044,  1047,  1051,  1053,  1056,  1058,  1060,  1062,  1067,
-  1072,  1077,  1082,  1084,  1086,  1088,  1090,  1094,  1096,  1100,
-  1102,  1106,  1107,  1112,  1113,  1121,  1126,  1127,  1135,  1140,
-  1141,  1149,  1154,  1155,  1163,  1168,  1169,  1171,  1173,  1176,
-  1183,  1185,  1189,  1190,  1192,  1197,  1204,  1209,  1211,  1213,
-  1215,  1217,  1219,  1223,  1225,  1228,  1232,  1237,  1239,  1241,
-  1245,  1250,  1257,  1261,  1267,  1268,  1276,  1281,  1282,  1289,
-  1293,  1296,  1299,  1304,  1306,  1307,  1309,  1310,  1312,  1314,
-  1317,  1320,  1323,  1326,  1330,  1333,  1336,  1339,  1343,  1347,
-  1349,  1352,  1353,  1354,  1358,  1362,  1365,  1367,  1369,  1370,
-  1372,  1375,  1377,  1381,  1383,  1386,  1388,  1393,  1398,  1400,
-  1402,  1405,  1408,  1410,  1411,  1413,  1418,  1422,  1424,  1427,
-  1430,  1433,  1436,  1439,  1442,  1445,  1448,  1453,  1456,  1458,
-  1464,  1468,  1469,  1471,  1475,  1476,  1478,  1482,  1484,  1486,
-  1488,  1490,  1495,  1502,  1507,  1512,  1519,  1524,  1528,  1533,
-  1540,  1545,  1550,  1557,  1562,  1566,  1568,  1572,  1574,  1578,
-  1581,  1583,  1590,  1591,  1594,  1596,  1599,  1600,  1603,  1607,
-  1611,  1614,  1617,  1621,  1623,  1625,  1627,  1630,  1636,  1642,
-  1646,  1652,  1657,  1661,  1665,  1668,  1670,  1674,  1678,  1681,
-  1684,  1688,  1690,  1694,  1698,  1701,  1704,  1708,  1710,  1716,
-  1722,  1726,  1732,  1736,  1741,  1745,  1748,  1751,  1753,  1756,
-  1761,  1766,  1769,  1771,  1773,  1775,  1778,  1781,  1784,  1786,
-  1789,  1791,  1794,  1797,  1801,  1803,  1807,  1810,  1814,  1817,
-  1820,  1824,  1826,  1830,  1835,  1839,  1842,  1845,  1847,  1851,
-  1854,  1857,  1859,  1862,  1866,  1868,  1872,  1874,  1880,  1884,
-  1889,  1893,  1898,  1901,  1904,  1908,  1911,  1913,  1915,  1918,
-  1921,  1924,  1925,  1926,  1928,  1930,  1933,  1937,  1939,  1942,
-  1946,  1952,  1959,  1965,  1966,  1967,  1974,  1976,  1979,  1981,
-  1983,  1985,  1988,  1989,  1994,  1996,  1997,  1998,  2005,  2006,
-  2007,  2015,  2016,  2017,  2018,  2029,  2030,  2031,  2032,  2043,
-  2044,  2052,  2053,  2059,  2060,  2068,  2069,  2074,  2077,  2080,
-  2083,  2087,  2094,  2103,  2114,  2127,  2132,  2136,  2139,  2142,
-  2144,  2146,  2147,  2148,  2156,  2158,  2161,  2164,  2165,  2166,
-  2172,  2174,  2176,  2180,  2184,  2187,  2190,  2193,  2197,  2202,
-  2207,  2211,  2216,  2223,  2230,  2231,  2233,  2234,  2236,  2238,
-  2239,  2241,  2243,  2247,  2252,  2254,  2258,  2259,  2261,  2263,
-  2265,  2268,  2271,  2274,  2276,  2278,  2281,  2284,  2287,  2290,
-  2292,  2296,  2299,  2302,  2307,  2310,  2313,  2316,  2319,  2322,
-  2325,  2327,  2330,  2332,  2336,  2338,  2340,  2341,  2342,  2344,
-  2345,  2350,  2352,  2354,  2358,  2359,  2363,  2367,  2371,  2373,
-  2376,  2379,  2382,  2385,  2388,  2391,  2394,  2397,  2400,  2403,
-  2406,  2409,  2412,  2415,  2418,  2421,  2424,  2427,  2430,  2433,
-  2436,  2439,  2442,  2446,  2449,  2452,  2455,  2458,  2462,  2465,
-  2468,  2473,  2478,  2482
+   745,   747,   749,   751,   753,   755,   758,   761,   763,   765,
+   767,   769,   771,   773,   775,   779,   783,   784,   789,   790,
+   797,   800,   805,   808,   811,   813,   818,   820,   828,   836,
+   844,   852,   857,   862,   865,   868,   870,   875,   878,   881,
+   884,   890,   894,   900,   904,   909,   916,   918,   921,   923,
+   926,   928,   930,   932,   935,   936,   939,   942,   946,   950,
+   954,   958,   962,   965,   968,   970,   972,   974,   977,   980,
+   983,   986,   988,   990,   992,   994,   997,  1000,  1004,  1008,
+  1013,  1015,  1018,  1021,  1023,  1025,  1028,  1031,  1033,  1036,
+  1039,  1043,  1045,  1048,  1050,  1052,  1054,  1059,  1064,  1069,
+  1074,  1076,  1078,  1080,  1082,  1086,  1088,  1092,  1094,  1098,
+  1099,  1104,  1105,  1113,  1118,  1119,  1127,  1132,  1133,  1141,
+  1146,  1147,  1155,  1160,  1161,  1163,  1165,  1168,  1175,  1177,
+  1181,  1182,  1184,  1189,  1196,  1201,  1203,  1205,  1207,  1209,
+  1211,  1215,  1217,  1220,  1224,  1229,  1231,  1233,  1237,  1242,
+  1249,  1253,  1259,  1260,  1268,  1273,  1274,  1281,  1285,  1288,
+  1291,  1296,  1298,  1299,  1301,  1302,  1304,  1306,  1309,  1312,
+  1315,  1318,  1322,  1325,  1328,  1331,  1335,  1339,  1341,  1344,
+  1345,  1346,  1350,  1354,  1357,  1359,  1361,  1362,  1364,  1367,
+  1369,  1373,  1375,  1378,  1380,  1385,  1390,  1392,  1394,  1397,
+  1400,  1402,  1403,  1405,  1410,  1414,  1416,  1419,  1422,  1425,
+  1428,  1431,  1434,  1437,  1440,  1445,  1448,  1450,  1456,  1460,
+  1461,  1463,  1467,  1468,  1470,  1474,  1476,  1478,  1480,  1482,
+  1487,  1494,  1499,  1504,  1511,  1516,  1520,  1525,  1532,  1537,
+  1542,  1549,  1554,  1558,  1560,  1564,  1566,  1570,  1573,  1575,
+  1582,  1583,  1586,  1588,  1591,  1592,  1595,  1599,  1603,  1606,
+  1609,  1613,  1615,  1617,  1619,  1622,  1628,  1634,  1638,  1644,
+  1649,  1653,  1657,  1660,  1662,  1666,  1670,  1673,  1676,  1680,
+  1682,  1686,  1690,  1693,  1696,  1700,  1702,  1708,  1714,  1718,
+  1724,  1728,  1732,  1737,  1741,  1744,  1747,  1749,  1752,  1757,
+  1762,  1765,  1767,  1769,  1771,  1774,  1777,  1780,  1782,  1785,
+  1787,  1790,  1793,  1797,  1799,  1803,  1806,  1810,  1813,  1816,
+  1820,  1822,  1826,  1831,  1835,  1838,  1841,  1843,  1847,  1850,
+  1853,  1855,  1858,  1862,  1864,  1868,  1870,  1876,  1880,  1885,
+  1889,  1894,  1897,  1900,  1904,  1907,  1909,  1911,  1914,  1917,
+  1920,  1921,  1922,  1924,  1926,  1929,  1933,  1935,  1938,  1942,
+  1948,  1955,  1961,  1962,  1963,  1970,  1972,  1975,  1977,  1979,
+  1981,  1984,  1985,  1990,  1992,  1993,  1994,  2001,  2002,  2003,
+  2011,  2012,  2013,  2014,  2025,  2026,  2027,  2028,  2039,  2040,
+  2048,  2049,  2055,  2056,  2064,  2065,  2070,  2073,  2076,  2079,
+  2083,  2090,  2099,  2110,  2123,  2128,  2132,  2135,  2138,  2140,
+  2142,  2143,  2144,  2152,  2154,  2157,  2160,  2161,  2162,  2168,
+  2170,  2172,  2176,  2180,  2183,  2186,  2189,  2193,  2198,  2203,
+  2207,  2212,  2219,  2226,  2227,  2229,  2230,  2232,  2234,  2235,
+  2237,  2239,  2243,  2248,  2250,  2254,  2255,  2257,  2259,  2261,
+  2264,  2267,  2270,  2272,  2274,  2277,  2280,  2283,  2286,  2288,
+  2292,  2295,  2298,  2303,  2306,  2309,  2312,  2315,  2318,  2321,
+  2323,  2326,  2328,  2332,  2334,  2336,  2337,  2338,  2340,  2341,
+  2346,  2348,  2350,  2354,  2355,  2359,  2363,  2367,  2369,  2372,
+  2375,  2378,  2381,  2384,  2387,  2390,  2393,  2396,  2399,  2402,
+  2405,  2408,  2411,  2414,  2417,  2420,  2423,  2426,  2429,  2432,
+  2435,  2438,  2442,  2445,  2448,  2451,  2454,  2458,  2461,  2464,
+  2469,  2474,  2478
 };
 
 static const short yyrhs[] = {    -1,
@@ -389,179 +389,178 @@
      0,    92,     0,    92,   169,     0,    83,   330,   139,     0,
    337,     0,     3,     0,    53,     0,   170,     0,     4,     0,
    170,     0,   263,     0,    75,   172,     0,    65,   172,     0,
-    88,   172,   102,     0,   261,     0,   170,     0,   263,     0,
-    88,   172,   102,     0,   170,     0,     8,     0,   179,     0,
-   180,     0,    88,   153,   102,     0,    88,     1,   102,     0,
-     0,    88,   175,   284,   102,     0,     0,   174,    88,   161,
-   102,   176,   151,     0,   174,    44,     0,   174,    89,   153,
-   105,     0,   174,    81,     0,   174,    82,     0,    40,     0,
-     7,    88,   161,   102,     0,   265,     0,    47,    69,   186,
-    70,    88,   153,   102,     0,    48,    69,   186,    70,    88,
-   153,   102,     0,    49,    69,   186,    70,    88,   153,   102,
-     0,    50,    69,   186,    70,    88,   153,   102,     0,    46,
-    88,   153,   102,     0,    46,    88,   186,   102,     0,   272,
-     3,     0,   272,   337,     0,   264,     0,   264,    88,   161,
-   102,     0,   264,    44,     0,   182,   171,     0,   182,   262,
-     0,   182,   171,    88,   161,   102,     0,   182,   171,    44,
-     0,   182,   262,    88,   161,   102,     0,   182,   262,    44,
-     0,   182,    83,     6,    44,     0,   182,     6,    51,    83,
-     6,    44,     0,    38,     0,   272,    38,     0,    37,     0,
-   272,   178,     0,    42,     0,    43,     0,     9,     0,   180,
-     9,     0,     0,   174,    87,     0,   174,    86,     0,   193,
-   184,    56,     0,   187,   184,    56,     0,   193,   195,    56,
-     0,   187,   195,    56,     0,   190,   196,    56,     0,   187,
-    56,     0,   190,    56,     0,   255,     0,   259,     0,    44,
-     0,   185,    44,     0,   191,   275,     0,   252,   275,     0,
-   193,   275,     0,   191,     0,   252,     0,   191,     0,   188,
-     0,   190,   193,     0,   193,   189,     0,   190,   193,   189,
-     0,   190,   193,   192,     0,   190,   193,   192,   189,     0,
-     5,     0,   189,   194,     0,   189,     5,     0,   252,     0,
-     5,     0,   190,     7,     0,   190,     5,     0,   193,     0,
-   252,   193,     0,   193,   192,     0,   252,   193,   192,     0,
-   194,     0,   192,   194,     0,   216,     0,     6,     0,   269,
-     0,    27,    88,   153,   102,     0,    27,    88,   186,   102,
-     0,    31,    88,   153,   102,     0,    31,    88,   186,   102,
-     0,     6,     0,     7,     0,   216,     0,   199,     0,   195,
-    55,   201,     0,   203,     0,   196,    55,   201,     0,   205,
-     0,   197,    55,   201,     0,     0,   111,    88,   180,   102,
-     0,     0,   184,   332,   198,   207,    58,   200,   214,     0,
-   184,   332,   198,   207,     0,     0,   184,   332,   198,   207,
-    58,   202,   214,     0,   184,   332,   198,   207,     0,     0,
-   259,   332,   198,   207,    58,   204,   214,     0,   259,   332,
-   198,   207,     0,     0,   259,   332,   198,   207,    58,   206,
-   214,     0,   259,   332,   198,   207,     0,     0,   208,     0,
-   209,     0,   208,   209,     0,    32,    88,    88,   210,   102,
-   102,     0,   211,     0,   210,    55,   211,     0,     0,   212,
-     0,   212,    88,     3,   102,     0,   212,    88,     3,    55,
-   161,   102,     0,   212,    88,   161,   102,     0,   139,     0,
-     5,     0,     6,     0,     7,     0,   139,     0,   213,    55,
-   139,     0,   169,     0,    54,   103,     0,    54,   215,   103,
-     0,    54,   215,    55,   103,     0,     1,     0,   214,     0,
-   215,    55,   214,     0,    89,   169,   105,   214,     0,   215,
-    55,    19,   169,    60,   214,     0,   139,    60,   214,     0,
-   215,    55,   139,    60,   214,     0,     0,    12,   139,    54,
-   217,   248,   220,   103,     0,    12,   139,    54,   103,     0,
-     0,    12,    54,   218,   248,   220,   103,     0,    12,    54,
-   103,     0,    12,   139,     0,    12,   270,     0,   229,   235,
-   236,   103,     0,   229,     0,     0,    55,     0,     0,    55,
-     0,    35,     0,   221,     5,     0,   221,     6,     0,   221,
-     7,     0,   221,    35,     0,   221,   144,    56,     0,   221,
-   139,     0,   221,   270,     0,   221,   143,     0,   221,   144,
-    54,     0,   221,   144,    60,     0,   222,     0,   221,   141,
-     0,     0,     0,   223,   225,   230,     0,   224,   226,   230,
-     0,   221,    54,     0,   228,     0,   227,     0,     0,    60,
-     0,    60,   231,     0,   232,     0,   231,    55,   232,     0,
-   233,     0,   234,   233,     0,   269,     0,    31,    88,   153,
-   102,     0,    31,    88,   186,   102,     0,    36,     0,     5,
-     0,   234,    36,     0,   234,     5,     0,    54,     0,     0,
-   237,     0,   236,    36,    60,   237,     0,   236,    36,    60,
-     0,   238,     0,   237,   238,     0,   237,    56,     0,   239,
-    56,     0,   239,   103,     0,   132,    60,     0,   132,    54,
-     0,   187,   240,     0,   190,   241,     0,   259,   332,   198,
-   207,     0,    60,   169,     0,     1,     0,   187,    88,   323,
-   102,   251,     0,   187,    44,   251,     0,     0,   242,     0,
-   240,    55,   243,     0,     0,   245,     0,   241,    55,   247,
-     0,   244,     0,   245,     0,   246,     0,   247,     0,   255,
+   261,     0,   170,     0,   263,     0,   170,     0,     8,     0,
+   179,     0,   180,     0,    88,   153,   102,     0,    88,     1,
+   102,     0,     0,    88,   175,   284,   102,     0,     0,   174,
+    88,   161,   102,   176,   151,     0,   174,    44,     0,   174,
+    89,   153,   105,     0,   174,    81,     0,   174,    82,     0,
+    40,     0,     7,    88,   161,   102,     0,   265,     0,    47,
+    69,   186,    70,    88,   153,   102,     0,    48,    69,   186,
+    70,    88,   153,   102,     0,    49,    69,   186,    70,    88,
+   153,   102,     0,    50,    69,   186,    70,    88,   153,   102,
+     0,    46,    88,   153,   102,     0,    46,    88,   186,   102,
+     0,   272,     3,     0,   272,   337,     0,   264,     0,   264,
+    88,   161,   102,     0,   264,    44,     0,   182,   171,     0,
+   182,   262,     0,   182,   171,    88,   161,   102,     0,   182,
+   171,    44,     0,   182,   262,    88,   161,   102,     0,   182,
+   262,    44,     0,   182,    83,     6,    44,     0,   182,     6,
+    51,    83,     6,    44,     0,    38,     0,   272,    38,     0,
+    37,     0,   272,   178,     0,    42,     0,    43,     0,     9,
+     0,   180,     9,     0,     0,   174,    87,     0,   174,    86,
+     0,   193,   184,    56,     0,   187,   184,    56,     0,   193,
+   195,    56,     0,   187,   195,    56,     0,   190,   196,    56,
+     0,   187,    56,     0,   190,    56,     0,   255,     0,   259,
+     0,    44,     0,   185,    44,     0,   191,   275,     0,   252,
+   275,     0,   193,   275,     0,   191,     0,   252,     0,   191,
+     0,   188,     0,   190,   193,     0,   193,   189,     0,   190,
+   193,   189,     0,   190,   193,   192,     0,   190,   193,   192,
+   189,     0,     5,     0,   189,   194,     0,   189,     5,     0,
+   252,     0,     5,     0,   190,     7,     0,   190,     5,     0,
+   193,     0,   252,   193,     0,   193,   192,     0,   252,   193,
+   192,     0,   194,     0,   192,   194,     0,   216,     0,     6,
+     0,   269,     0,    27,    88,   153,   102,     0,    27,    88,
+   186,   102,     0,    31,    88,   153,   102,     0,    31,    88,
+   186,   102,     0,     6,     0,     7,     0,   216,     0,   199,
+     0,   195,    55,   201,     0,   203,     0,   196,    55,   201,
+     0,   205,     0,   197,    55,   201,     0,     0,   111,    88,
+   180,   102,     0,     0,   184,   332,   198,   207,    58,   200,
+   214,     0,   184,   332,   198,   207,     0,     0,   184,   332,
+   198,   207,    58,   202,   214,     0,   184,   332,   198,   207,
+     0,     0,   259,   332,   198,   207,    58,   204,   214,     0,
+   259,   332,   198,   207,     0,     0,   259,   332,   198,   207,
+    58,   206,   214,     0,   259,   332,   198,   207,     0,     0,
+   208,     0,   209,     0,   208,   209,     0,    32,    88,    88,
+   210,   102,   102,     0,   211,     0,   210,    55,   211,     0,
+     0,   212,     0,   212,    88,     3,   102,     0,   212,    88,
+     3,    55,   161,   102,     0,   212,    88,   161,   102,     0,
+   139,     0,     5,     0,     6,     0,     7,     0,   139,     0,
+   213,    55,   139,     0,   169,     0,    54,   103,     0,    54,
+   215,   103,     0,    54,   215,    55,   103,     0,     1,     0,
+   214,     0,   215,    55,   214,     0,    89,   169,   105,   214,
+     0,   215,    55,    19,   169,    60,   214,     0,   139,    60,
+   214,     0,   215,    55,   139,    60,   214,     0,     0,    12,
+   139,    54,   217,   248,   220,   103,     0,    12,   139,    54,
+   103,     0,     0,    12,    54,   218,   248,   220,   103,     0,
+    12,    54,   103,     0,    12,   139,     0,    12,   270,     0,
+   229,   235,   236,   103,     0,   229,     0,     0,    55,     0,
+     0,    55,     0,    35,     0,   221,     5,     0,   221,     6,
+     0,   221,     7,     0,   221,    35,     0,   221,   144,    56,
+     0,   221,   139,     0,   221,   270,     0,   221,   143,     0,
+   221,   144,    54,     0,   221,   144,    60,     0,   222,     0,
+   221,   141,     0,     0,     0,   223,   225,   230,     0,   224,
+   226,   230,     0,   221,    54,     0,   228,     0,   227,     0,
+     0,    60,     0,    60,   231,     0,   232,     0,   231,    55,
+   232,     0,   233,     0,   234,   233,     0,   269,     0,    31,
+    88,   153,   102,     0,    31,    88,   186,   102,     0,    36,
+     0,     5,     0,   234,    36,     0,   234,     5,     0,    54,
+     0,     0,   237,     0,   236,    36,    60,   237,     0,   236,
+    36,    60,     0,   238,     0,   237,   238,     0,   237,    56,
+     0,   239,    56,     0,   239,   103,     0,   132,    60,     0,
+   132,    54,     0,   187,   240,     0,   190,   241,     0,   259,
+   332,   198,   207,     0,    60,   169,     0,     1,     0,   187,
+    88,   323,   102,   251,     0,   187,    44,   251,     0,     0,
+   242,     0,   240,    55,   243,     0,     0,   245,     0,   241,
+    55,   247,     0,   244,     0,   245,     0,   246,     0,   247,
+     0,   255,   332,   198,   207,     0,   255,   332,   198,   207,
+    58,   214,     0,     4,    60,   169,   207,     0,   259,   332,
+   198,   207,     0,   259,   332,   198,   207,    58,   214,     0,
+     3,    60,   169,   207,     0,    60,   169,   207,     0,   255,
    332,   198,   207,     0,   255,   332,   198,   207,    58,   214,
      0,     4,    60,   169,   207,     0,   259,   332,   198,   207,
      0,   259,   332,   198,   207,    58,   214,     0,     3,    60,
-   169,   207,     0,    60,   169,   207,     0,   255,   332,   198,
-   207,     0,   255,   332,   198,   207,    58,   214,     0,     4,
-    60,   169,   207,     0,   259,   332,   198,   207,     0,   259,
-   332,   198,   207,    58,   214,     0,     3,    60,   169,   207,
-     0,    60,   169,   207,     0,   249,     0,   248,    55,   249,
-     0,   139,     0,   139,    58,   169,     0,   312,   273,     0,
-   312,     0,    88,   186,   102,    89,   153,   105,     0,     0,
-   251,     7,     0,     7,     0,   252,     7,     0,     0,   254,
-   153,     0,    75,   252,   255,     0,    65,   252,   255,     0,
-    75,   255,     0,    65,   255,     0,   271,   251,   255,     0,
-   258,     0,   266,     0,   257,     0,   267,   266,     0,   258,
-    88,   161,   102,   251,     0,   258,    88,   323,   102,   251,
-     0,   258,    44,   251,     0,   258,    88,     1,   102,   251,
-     0,   258,    89,   253,   105,     0,   258,    89,   105,     0,
-    88,   255,   102,     0,   267,   266,     0,   266,     0,    75,
-   252,   259,     0,    65,   252,   259,     0,    75,   259,     0,
-    65,   259,     0,   271,   251,   259,     0,   173,     0,    75,
-   252,   259,     0,    65,   252,   259,     0,    75,   260,     0,
-    65,   260,     0,   271,   251,   259,     0,   261,     0,   173,
-    88,   161,   102,   251,     0,   173,    88,   323,   102,   251,
-     0,   173,    44,   251,     0,   173,    88,     1,   102,   251,
-     0,    88,   260,   102,     0,   173,    89,   253,   105,     0,
-   173,    89,   105,     0,   267,   171,     0,   267,   170,     0,
-   263,     0,   272,   263,     0,   193,    88,   161,   102,     0,
-   193,    88,   172,   102,     0,   193,   185,     0,     4,     0,
-   143,     0,   268,     0,   267,   268,     0,     4,    51,     0,
-   143,    51,     0,   256,     0,   272,   256,     0,   257,     0,
-   272,   256,     0,   267,    75,     0,   272,   267,    75,     0,
-    51,     0,    75,   251,   273,     0,    75,   251,     0,    65,
-   251,   273,     0,    65,   251,     0,   271,   251,     0,   271,
-   251,   273,     0,   274,     0,    89,   153,   105,     0,   274,
-    89,   253,   105,     0,    75,   252,   275,     0,    75,   275,
-     0,    75,   252,     0,    75,     0,    65,   252,   275,     0,
-    65,   275,     0,    65,   252,     0,    65,     0,   271,   251,
-     0,   271,   251,   275,     0,   276,     0,    88,   275,   102,
-     0,    85,     0,   276,    88,   323,   102,   251,     0,   276,
-    44,   251,     0,   276,    89,   253,   105,     0,   276,    89,
-   105,     0,    88,   324,   102,   251,     0,   166,   251,     0,
-   185,   251,     0,    89,   253,   105,     0,    89,   105,     0,
-   289,     0,   278,     0,   277,   289,     0,   277,   278,     0,
-     1,    56,     0,     0,     0,   281,     0,   282,     0,   281,
-   282,     0,    34,   213,    56,     0,   284,     0,     1,   284,
-     0,    54,   279,   103,     0,    54,   279,   280,   277,   103,
-     0,    54,   279,   280,   277,     1,   103,     0,    54,   279,
-   280,     1,   103,     0,     0,     0,    13,   286,   279,   155,
-   287,   288,     0,   284,     0,   279,   290,     0,   284,     0,
-   290,     0,   183,     0,   153,    56,     0,     0,   285,    14,
-   291,   288,     0,   285,     0,     0,     0,    15,   292,   279,
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-   105,     0,   336,    37,    89,   105,     0,   336,   312,   335,
-     0,   336,     1,     0
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+     0,   173,    89,   253,   105,     0,   173,    89,   105,     0,
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+     0,   272,   256,     0,   257,     0,   272,   256,     0,   267,
+    75,     0,   272,   267,    75,     0,    51,     0,    75,   251,
+   273,     0,    75,   251,     0,    65,   251,   273,     0,    65,
+   251,     0,   271,   251,     0,   271,   251,   273,     0,   274,
+     0,    89,   153,   105,     0,   274,    89,   253,   105,     0,
+    75,   252,   275,     0,    75,   275,     0,    75,   252,     0,
+    75,     0,    65,   252,   275,     0,    65,   275,     0,    65,
+   252,     0,    65,     0,   271,   251,     0,   271,   251,   275,
+     0,   276,     0,    88,   275,   102,     0,    85,     0,   276,
+    88,   323,   102,   251,     0,   276,    44,   251,     0,   276,
+    89,   253,   105,     0,   276,    89,   105,     0,    88,   324,
+   102,   251,     0,   166,   251,     0,   185,   251,     0,    89,
+   253,   105,     0,    89,   105,     0,   289,     0,   278,     0,
+   277,   289,     0,   277,   278,     0,     1,    56,     0,     0,
+     0,   281,     0,   282,     0,   281,   282,     0,    34,   213,
+    56,     0,   284,     0,     1,   284,     0,    54,   279,   103,
+     0,    54,   279,   280,   277,   103,     0,    54,   279,   280,
+   277,     1,   103,     0,    54,   279,   280,     1,   103,     0,
+     0,     0,    13,   286,   279,   155,   287,   288,     0,   284,
+     0,   279,   290,     0,   284,     0,   290,     0,   183,     0,
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+     0,     0,     0,    15,   292,   279,   155,   293,   159,     0,
+     0,     0,    16,   294,   288,    15,   295,   154,    56,     0,
+     0,     0,     0,   315,   296,   279,   156,    56,   297,   318,
+   102,   298,   159,     0,     0,     0,     0,   316,   299,   279,
+   156,    56,   300,   318,   102,   301,   159,     0,     0,    18,
+   279,    88,   157,   102,   302,   288,     0,     0,    19,   169,
+    60,   303,   289,     0,     0,    19,   169,    10,   169,    60,
+   304,   289,     0,     0,    20,    60,   305,   289,     0,    21,
+    56,     0,    22,    56,     0,    23,    56,     0,    23,   153,
+    56,     0,   111,   317,    88,   180,   102,    56,     0,   111,
+   317,    88,   180,    60,   319,   102,    56,     0,   111,   317,
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+   317,    88,   180,    60,   319,    60,   319,    60,   322,   102,
+    56,     0,    24,    75,   153,    56,     0,    24,   139,    56,
+     0,   314,   289,     0,   314,   103,     0,    56,     0,   306,
+     0,     0,     0,    90,    54,   279,   307,   309,   308,   310,
+     0,   103,     0,   277,   103,     0,     1,   103,     0,     0,
+     0,   310,    91,   311,   313,   284,     0,   191,     0,   252,
+     0,    88,    10,   102,     0,    88,   329,   102,     0,     3,
+    60,     0,    53,    60,     0,     4,    60,     0,    17,    88,
+    56,     0,    17,    88,   153,    56,     0,    17,    88,    54,
+   103,     0,    17,    88,   183,     0,    17,    88,     1,    56,
+     0,    17,    88,    54,   279,   277,   103,     0,    17,    88,
+    54,   279,     1,   103,     0,     0,     7,     0,     0,   153,
+     0,     1,     0,     0,   320,     0,   321,     0,   320,    55,
+   321,     0,     9,    88,   153,   102,     0,     9,     0,   322,
+    55,     9,     0,     0,   324,     0,   186,     0,   325,     0,
+   326,    10,     0,   325,    10,     0,   186,    10,     0,    10,
+     0,    93,     0,   325,    93,     0,   186,    93,     0,   325,
+    60,     0,   186,    60,     0,   327,     0,   329,    58,   214,
+     0,   326,   328,     0,   326,   331,     0,   326,   331,    58,
+   214,     0,   325,    55,     0,   186,    55,     0,   188,   184,
+     0,   191,   184,     0,   193,   184,     0,   188,   275,     0,
+   188,     0,   190,   259,     0,   329,     0,   329,    58,   214,
+     0,   327,     0,   186,     0,     0,     0,   259,     0,     0,
+    92,    88,   334,   102,     0,   186,     0,   333,     0,   334,
+    55,   333,     0,     0,    75,   251,   335,     0,    65,   251,
+   335,     0,   271,   251,   335,     0,    41,     0,   336,    75,
+     0,   336,    76,     0,   336,    77,     0,   336,    73,     0,
+   336,    74,     0,   336,    65,     0,   336,    63,     0,   336,
+    64,     0,   336,    83,     0,   336,    55,     0,   336,    68,
+     0,   336,    69,     0,   336,    70,     0,   336,    67,     0,
+   336,    57,     0,   336,    58,     0,   336,    71,     0,   336,
+    72,     0,   336,    81,     0,   336,    82,     0,   336,    62,
+     0,   336,    61,     0,   336,   104,     0,   336,    59,    60,
+     0,   336,    66,     0,   336,    86,     0,   336,    78,     0,
+   336,    44,     0,   336,    89,   105,     0,   336,    38,     0,
+   336,    37,     0,   336,    38,    89,   105,     0,   336,    37,
+    89,   105,     0,   336,   312,   335,     0,   336,     1,     0
 };
 
 #endif
@@ -590,59 +589,59 @@
   1144,  1146,  1163,  1166,  1168,  1170,  1172,  1174,  1176,  1178,
   1180,  1182,  1184,  1186,  1188,  1190,  1192,  1194,  1196,  1198,
   1200,  1202,  1204,  1206,  1208,  1215,  1217,  1234,  1237,  1238,
-  1239,  1242,  1244,  1247,  1249,  1250,  1252,  1254,  1258,  1260,
-  1261,  1264,  1268,  1288,  1289,  1290,  1292,  1294,  1296,  1304,
-  1325,  1330,  1337,  1344,  1346,  1355,  1360,  1383,  1427,  1428,
-  1431,  1434,  1437,  1440,  1442,  1445,  1484,  1491,  1493,  1495,
-  1497,  1499,  1501,  1516,  1531,  1542,  1554,  1561,  1610,  1612,
-  1616,  1618,  1622,  1625,  1630,  1632,  1636,  1649,  1650,  1656,
-  1667,  1675,  1681,  1686,  1688,  1693,  1700,  1702,  1706,  1710,
-  1716,  1719,  1721,  1723,  1725,  1733,  1735,  1737,  1740,  1742,
-  1744,  1746,  1751,  1757,  1759,  1770,  1773,  1775,  1778,  1793,
-  1796,  1798,  1800,  1804,  1807,  1815,  1816,  1817,  1818,  1822,
-  1826,  1840,  1858,  1859,  1860,  1863,  1865,  1868,  1870,  1873,
-  1875,  1878,  1881,  1885,  1902,  1904,  1922,  1928,  1929,  1935,
-  1943,  1945,  1954,  1962,  1964,  1975,  1978,  1982,  1985,  1989,
-  1994,  1997,  2001,  2004,  2006,  2008,  2010,  2017,  2019,  2020,
-  2021,  2025,  2028,  2032,  2034,  2037,  2040,  2043,  2049,  2052,
-  2055,  2057,  2059,  2061,  2065,  2069,  2073,  2076,  2079,  2083,
-  2086,  2088,  2092,  2143,  2158,  2160,  2163,  2165,  2169,  2170,
-  2172,  2174,  2176,  2180,  2189,  2192,  2194,  2196,  2202,  2204,
-  2207,  2212,  2215,  2218,  2227,  2238,  2243,  2243,  2245,  2248,
-  2250,  2254,  2256,  2260,  2288,  2319,  2321,  2343,  2367,  2369,
-  2373,  2399,  2408,  2470,  2473,  2480,  2491,  2500,  2504,  2517,
-  2520,  2522,  2527,  2529,  2533,  2541,  2545,  2548,  2550,  2561,
-  2566,  2574,  2577,  2578,  2589,  2592,  2593,  2604,  2606,  2609,
-  2611,  2614,  2619,  2623,  2629,  2634,  2638,  2642,  2648,  2652,
-  2655,  2660,  2664,  2667,  2670,  2679,  2681,  2685,  2688,  2693,
-  2696,  2700,  2709,  2712,  2716,  2719,  2727,  2729,  2734,  2737,
-  2739,  2741,  2743,  2747,  2750,  2764,  2767,  2772,  2775,  2777,
-  2779,  2781,  2783,  2785,  2787,  2791,  2797,  2800,  2802,  2804,
-  2806,  2810,  2813,  2816,  2818,  2820,  2822,  2826,  2829,  2832,
-  2834,  2836,  2838,  2840,  2842,  2846,  2852,  2858,  2860,  2864,
-  2867,  2869,  2873,  2875,  2878,  2880,  2886,  2889,  2903,  2905,
-  2909,  2911,  2915,  2918,  2924,  2930,  2933,  2935,  2937,  2939,
-  2943,  2947,  2951,  2954,  2959,  2962,  2964,  2966,  2968,  2970,
-  2972,  2974,  2976,  2980,  2984,  2988,  2992,  2993,  2995,  2997,
-  2999,  3001,  3003,  3005,  3007,  3009,  3017,  3019,  3020,  3021,
-  3024,  3031,  3041,  3043,  3048,  3050,  3053,  3067,  3070,  3073,
-  3077,  3081,  3085,  3091,  3094,  3098,  3100,  3103,  3109,  3112,
-  3115,  3118,  3131,  3134,  3139,  3145,  3150,  3153,  3158,  3162,
-  3165,  3171,  3176,  3179,  3184,  3193,  3197,  3200,  3206,  3216,
-  3223,  3229,  3254,  3254,  3286,  3286,  3302,  3302,  3306,  3310,
-  3313,  3318,  3325,  3334,  3343,  3352,  3355,  3361,  3363,  3367,
-  3369,  3372,  3376,  3379,  3382,  3390,  3394,  3400,  3402,  3404,
-  3408,  3410,  3413,  3426,  3431,  3439,  3441,  3445,  3448,  3450,
-  3454,  3457,  3459,  3461,  3467,  3471,  3475,  3478,  3479,  3485,
-  3487,  3490,  3492,  3496,  3501,  3504,  3514,  3521,  3522,  3529,
-  3535,  3540,  3544,  3549,  3556,  3560,  3564,  3569,  3580,  3594,
-  3597,  3599,  3601,  3603,  3607,  3609,  3617,  3634,  3636,  3638,
-  3640,  3642,  3646,  3649,  3653,  3655,  3658,  3680,  3686,  3693,
-  3696,  3700,  3705,  3707,  3714,  3717,  3719,  3721,  3727,  3731,
+  1239,  1242,  1244,  1247,  1249,  1250,  1252,  1256,  1258,  1259,
+  1264,  1284,  1285,  1286,  1288,  1290,  1292,  1300,  1321,  1326,
+  1333,  1340,  1342,  1351,  1356,  1379,  1423,  1424,  1427,  1430,
+  1433,  1436,  1438,  1441,  1480,  1487,  1489,  1491,  1493,  1495,
+  1497,  1512,  1527,  1538,  1550,  1557,  1606,  1608,  1612,  1614,
+  1618,  1621,  1626,  1628,  1632,  1645,  1646,  1652,  1663,  1671,
+  1677,  1682,  1684,  1689,  1696,  1698,  1702,  1706,  1712,  1715,
+  1717,  1719,  1721,  1729,  1731,  1733,  1736,  1738,  1740,  1742,
+  1747,  1753,  1755,  1766,  1769,  1771,  1774,  1789,  1792,  1794,
+  1796,  1800,  1803,  1811,  1812,  1813,  1814,  1818,  1822,  1836,
+  1854,  1855,  1856,  1859,  1861,  1864,  1866,  1869,  1871,  1874,
+  1877,  1881,  1898,  1900,  1918,  1924,  1925,  1931,  1939,  1941,
+  1950,  1958,  1960,  1971,  1974,  1978,  1981,  1985,  1990,  1993,
+  1997,  2000,  2002,  2004,  2006,  2013,  2015,  2016,  2017,  2021,
+  2024,  2028,  2030,  2033,  2036,  2039,  2045,  2048,  2051,  2053,
+  2055,  2057,  2061,  2065,  2069,  2072,  2075,  2079,  2082,  2084,
+  2088,  2139,  2154,  2156,  2159,  2161,  2165,  2166,  2168,  2170,
+  2172,  2176,  2185,  2188,  2190,  2192,  2198,  2200,  2203,  2208,
+  2211,  2214,  2223,  2234,  2239,  2239,  2241,  2244,  2246,  2250,
+  2252,  2256,  2284,  2315,  2317,  2339,  2363,  2365,  2369,  2395,
+  2404,  2466,  2469,  2476,  2487,  2496,  2500,  2513,  2516,  2518,
+  2523,  2525,  2529,  2537,  2541,  2544,  2546,  2557,  2562,  2570,
+  2573,  2574,  2585,  2588,  2589,  2600,  2602,  2605,  2607,  2610,
+  2615,  2619,  2625,  2630,  2634,  2638,  2644,  2648,  2651,  2656,
+  2660,  2663,  2666,  2675,  2677,  2681,  2684,  2689,  2692,  2696,
+  2705,  2708,  2712,  2715,  2723,  2725,  2730,  2733,  2735,  2737,
+  2739,  2743,  2746,  2760,  2763,  2768,  2771,  2773,  2775,  2777,
+  2779,  2781,  2783,  2787,  2793,  2796,  2798,  2800,  2802,  2806,
+  2809,  2812,  2814,  2816,  2818,  2822,  2825,  2828,  2830,  2832,
+  2834,  2836,  2838,  2840,  2844,  2850,  2856,  2858,  2862,  2865,
+  2867,  2871,  2873,  2876,  2878,  2884,  2887,  2901,  2903,  2907,
+  2909,  2913,  2916,  2922,  2928,  2931,  2933,  2935,  2937,  2941,
+  2945,  2949,  2952,  2957,  2960,  2962,  2964,  2966,  2968,  2970,
+  2972,  2974,  2978,  2982,  2986,  2990,  2991,  2993,  2995,  2997,
+  2999,  3001,  3003,  3005,  3007,  3015,  3017,  3018,  3019,  3022,
+  3029,  3039,  3041,  3046,  3048,  3051,  3065,  3068,  3071,  3075,
+  3079,  3083,  3089,  3092,  3096,  3098,  3101,  3107,  3110,  3113,
+  3116,  3129,  3132,  3137,  3143,  3148,  3151,  3156,  3160,  3163,
+  3169,  3174,  3177,  3182,  3191,  3195,  3198,  3204,  3214,  3221,
+  3227,  3252,  3252,  3284,  3284,  3300,  3300,  3304,  3308,  3311,
+  3316,  3323,  3332,  3341,  3350,  3353,  3359,  3361,  3365,  3367,
+  3370,  3374,  3377,  3380,  3388,  3392,  3398,  3400,  3402,  3406,
+  3408,  3411,  3424,  3429,  3437,  3439,  3443,  3446,  3448,  3452,
+  3455,  3457,  3459,  3465,  3469,  3473,  3476,  3477,  3483,  3485,
+  3488,  3490,  3494,  3499,  3502,  3512,  3519,  3520,  3527,  3533,
+  3538,  3542,  3547,  3554,  3558,  3562,  3567,  3578,  3592,  3595,
+  3597,  3599,  3601,  3605,  3607,  3615,  3632,  3634,  3636,  3638,
+  3640,  3644,  3647,  3651,  3653,  3656,  3678,  3684,  3691,  3694,
+  3698,  3703,  3705,  3712,  3715,  3717,  3719,  3725,  3729,  3732,
   3734,  3736,  3738,  3740,  3742,  3744,  3746,  3748,  3750,  3752,
   3754,  3756,  3758,  3760,  3762,  3764,  3766,  3768,  3770,  3772,
   3774,  3776,  3778,  3780,  3782,  3784,  3786,  3788,  3790,  3792,
-  3794,  3796,  3799,  3801
+  3794,  3797,  3799
 };
 
 static const char * const yytname[] = {   "$","error","$illegal.","IDENTIFIER",
@@ -727,59 +726,59 @@
    168,   168,   169,   169,   169,   169,   169,   169,   169,   169,
    169,   169,   169,   169,   169,   169,   169,   169,   169,   169,
    169,   169,   169,   169,   169,   169,   169,   170,   170,   170,
-   170,   171,   171,   172,   172,   172,   172,   172,   173,   173,
-   173,   173,   174,   174,   174,   174,   174,   174,   175,   174,
-   176,   174,   174,   174,   174,   174,   174,   174,   174,   174,
+   170,   171,   171,   172,   172,   172,   172,   173,   173,   173,
+   174,   174,   174,   174,   174,   174,   175,   174,   176,   174,
    174,   174,   174,   174,   174,   174,   174,   174,   174,   174,
-   174,   174,   174,   174,   174,   174,   174,   174,   177,   177,
-   178,   178,   179,   179,   180,   180,   181,   182,   182,   183,
-   183,   183,   183,   183,   183,   183,   184,   184,   185,   185,
-   186,   186,   186,   186,   186,   187,   187,   188,   188,   188,
-   188,   188,   189,   189,   189,   190,   190,   190,   190,   191,
-   191,   191,   191,   192,   192,   193,   193,   193,   193,   193,
-   193,   193,   194,   194,   194,   195,   195,   196,   196,   197,
-   197,   198,   198,   200,   199,   199,   202,   201,   201,   204,
-   203,   203,   206,   205,   205,   207,   207,   208,   208,   209,
-   210,   210,   211,   211,   211,   211,   211,   212,   212,   212,
-   212,   213,   213,   214,   214,   214,   214,   214,   215,   215,
-   215,   215,   215,   215,   217,   216,   216,   218,   216,   216,
-   216,   216,   216,   216,   219,   219,   220,   220,   221,   221,
-   221,   221,   221,   222,   223,   223,   223,   223,   223,   223,
-   224,   225,   226,   227,   227,   228,   229,   229,   230,   230,
-   230,   231,   231,   232,   232,   233,   233,   233,   234,   234,
-   234,   234,   235,   236,   236,   236,   236,   237,   237,   237,
-   238,   238,   238,   238,   239,   239,   239,   239,   239,   239,
-   239,   240,   240,   240,   241,   241,   241,   242,   242,   243,
-   243,   244,   244,   244,   245,   245,   245,   245,   246,   246,
-   246,   247,   247,   247,   247,   248,   248,   249,   249,   250,
-   250,   250,   251,   251,   252,   252,   254,   253,   255,   255,
-   255,   255,   255,   255,   256,   256,   257,   258,   258,   258,
-   258,   258,   258,   258,   258,   258,   259,   259,   259,   259,
-   259,   259,   260,   260,   260,   260,   260,   260,   261,   261,
-   261,   261,   261,   261,   261,   262,   263,   264,   264,   265,
-   265,   265,   266,   266,   267,   267,   268,   268,   269,   269,
-   270,   270,   271,   271,   272,   273,   273,   273,   273,   273,
-   273,   273,   274,   274,   275,   275,   275,   275,   275,   275,
-   275,   275,   275,   275,   275,   276,   276,   276,   276,   276,
-   276,   276,   276,   276,   276,   276,   277,   277,   277,   277,
-   278,   279,   280,   280,   281,   281,   282,   283,   283,   284,
-   284,   284,   284,   286,   287,   285,   288,   288,   289,   289,
-   290,   290,   291,   290,   290,   292,   293,   290,   294,   295,
-   290,   296,   297,   298,   290,   299,   300,   301,   290,   302,
-   290,   303,   290,   304,   290,   305,   290,   290,   290,   290,
+   174,   174,   174,   174,   174,   174,   174,   174,   174,   174,
+   174,   174,   174,   174,   174,   174,   177,   177,   178,   178,
+   179,   179,   180,   180,   181,   182,   182,   183,   183,   183,
+   183,   183,   183,   183,   184,   184,   185,   185,   186,   186,
+   186,   186,   186,   187,   187,   188,   188,   188,   188,   188,
+   189,   189,   189,   190,   190,   190,   190,   191,   191,   191,
+   191,   192,   192,   193,   193,   193,   193,   193,   193,   193,
+   194,   194,   194,   195,   195,   196,   196,   197,   197,   198,
+   198,   200,   199,   199,   202,   201,   201,   204,   203,   203,
+   206,   205,   205,   207,   207,   208,   208,   209,   210,   210,
+   211,   211,   211,   211,   211,   212,   212,   212,   212,   213,
+   213,   214,   214,   214,   214,   214,   215,   215,   215,   215,
+   215,   215,   217,   216,   216,   218,   216,   216,   216,   216,
+   216,   216,   219,   219,   220,   220,   221,   221,   221,   221,
+   221,   222,   223,   223,   223,   223,   223,   223,   224,   225,
+   226,   227,   227,   228,   229,   229,   230,   230,   230,   231,
+   231,   232,   232,   233,   233,   233,   234,   234,   234,   234,
+   235,   236,   236,   236,   236,   237,   237,   237,   238,   238,
+   238,   238,   239,   239,   239,   239,   239,   239,   239,   240,
+   240,   240,   241,   241,   241,   242,   242,   243,   243,   244,
+   244,   244,   245,   245,   245,   245,   246,   246,   246,   247,
+   247,   247,   247,   248,   248,   249,   249,   250,   250,   250,
+   251,   251,   252,   252,   254,   253,   255,   255,   255,   255,
+   255,   255,   256,   256,   257,   258,   258,   258,   258,   258,
+   258,   258,   258,   258,   259,   259,   259,   259,   259,   259,
+   260,   260,   260,   260,   260,   260,   261,   261,   261,   261,
+   261,   261,   261,   261,   262,   263,   264,   264,   265,   265,
+   265,   266,   266,   267,   267,   268,   268,   269,   269,   270,
+   270,   271,   271,   272,   273,   273,   273,   273,   273,   273,
+   273,   274,   274,   275,   275,   275,   275,   275,   275,   275,
+   275,   275,   275,   275,   276,   276,   276,   276,   276,   276,
+   276,   276,   276,   276,   276,   277,   277,   277,   277,   278,
+   279,   280,   280,   281,   281,   282,   283,   283,   284,   284,
+   284,   284,   286,   287,   285,   288,   288,   289,   289,   290,
+   290,   291,   290,   290,   292,   293,   290,   294,   295,   290,
+   296,   297,   298,   290,   299,   300,   301,   290,   302,   290,
+   303,   290,   304,   290,   305,   290,   290,   290,   290,   290,
    290,   290,   290,   290,   290,   290,   290,   290,   290,   290,
-   290,   307,   308,   306,   309,   309,   309,   310,   311,   310,
-   312,   312,   313,   313,   314,   314,   314,   315,   315,   315,
-   316,   316,   316,   316,   317,   317,   318,   318,   318,   319,
-   319,   320,   320,   321,   322,   322,   323,   323,   323,   324,
-   324,   324,   324,   324,   324,   324,   324,   324,   324,   325,
-   325,   325,   325,   325,   326,   326,   327,   327,   327,   327,
-   327,   327,   328,   328,   329,   329,   330,   331,   331,   332,
-   332,   333,   334,   334,   335,   335,   335,   335,   336,   337,
+   307,   308,   306,   309,   309,   309,   310,   311,   310,   312,
+   312,   313,   313,   314,   314,   314,   315,   315,   315,   316,
+   316,   316,   316,   317,   317,   318,   318,   318,   319,   319,
+   320,   320,   321,   322,   322,   323,   323,   323,   324,   324,
+   324,   324,   324,   324,   324,   324,   324,   324,   325,   325,
+   325,   325,   325,   326,   326,   327,   327,   327,   327,   327,
+   327,   328,   328,   329,   329,   330,   331,   331,   332,   332,
+   333,   334,   334,   335,   335,   335,   335,   336,   337,   337,
    337,   337,   337,   337,   337,   337,   337,   337,   337,   337,
    337,   337,   337,   337,   337,   337,   337,   337,   337,   337,
    337,   337,   337,   337,   337,   337,   337,   337,   337,   337,
-   337,   337,   337,   337
+   337,   337,   337
 };
 
 static const short yyr2[] = {     0,
@@ -805,2029 +804,2024 @@
      4,     4,     1,     3,     3,     3,     3,     3,     3,     3,
      3,     3,     3,     3,     3,     3,     3,     3,     3,     3,
      3,     3,     5,     3,     3,     1,     2,     3,     1,     1,
-     1,     1,     1,     1,     1,     2,     2,     3,     1,     1,
-     1,     3,     1,     1,     1,     1,     3,     3,     0,     4,
-     0,     6,     2,     4,     2,     2,     1,     4,     1,     7,
-     7,     7,     7,     4,     4,     2,     2,     1,     4,     2,
-     2,     2,     5,     3,     5,     3,     4,     6,     1,     2,
-     1,     2,     1,     1,     1,     2,     0,     2,     2,     3,
-     3,     3,     3,     3,     2,     2,     1,     1,     1,     2,
-     2,     2,     2,     1,     1,     1,     1,     2,     2,     3,
-     3,     4,     1,     2,     2,     1,     1,     2,     2,     1,
-     2,     2,     3,     1,     2,     1,     1,     1,     4,     4,
-     4,     4,     1,     1,     1,     1,     3,     1,     3,     1,
-     3,     0,     4,     0,     7,     4,     0,     7,     4,     0,
-     7,     4,     0,     7,     4,     0,     1,     1,     2,     6,
-     1,     3,     0,     1,     4,     6,     4,     1,     1,     1,
-     1,     1,     3,     1,     2,     3,     4,     1,     1,     3,
-     4,     6,     3,     5,     0,     7,     4,     0,     6,     3,
-     2,     2,     4,     1,     0,     1,     0,     1,     1,     2,
-     2,     2,     2,     3,     2,     2,     2,     3,     3,     1,
-     2,     0,     0,     3,     3,     2,     1,     1,     0,     1,
-     2,     1,     3,     1,     2,     1,     4,     4,     1,     1,
-     2,     2,     1,     0,     1,     4,     3,     1,     2,     2,
-     2,     2,     2,     2,     2,     2,     4,     2,     1,     5,
-     3,     0,     1,     3,     0,     1,     3,     1,     1,     1,
-     1,     4,     6,     4,     4,     6,     4,     3,     4,     6,
-     4,     4,     6,     4,     3,     1,     3,     1,     3,     2,
-     1,     6,     0,     2,     1,     2,     0,     2,     3,     3,
-     2,     2,     3,     1,     1,     1,     2,     5,     5,     3,
-     5,     4,     3,     3,     2,     1,     3,     3,     2,     2,
-     3,     1,     3,     3,     2,     2,     3,     1,     5,     5,
-     3,     5,     3,     4,     3,     2,     2,     1,     2,     4,
-     4,     2,     1,     1,     1,     2,     2,     2,     1,     2,
-     1,     2,     2,     3,     1,     3,     2,     3,     2,     2,
-     3,     1,     3,     4,     3,     2,     2,     1,     3,     2,
-     2,     1,     2,     3,     1,     3,     1,     5,     3,     4,
-     3,     4,     2,     2,     3,     2,     1,     1,     2,     2,
-     2,     0,     0,     1,     1,     2,     3,     1,     2,     3,
-     5,     6,     5,     0,     0,     6,     1,     2,     1,     1,
-     1,     2,     0,     4,     1,     0,     0,     6,     0,     0,
-     7,     0,     0,     0,    10,     0,     0,     0,    10,     0,
-     7,     0,     5,     0,     7,     0,     4,     2,     2,     2,
-     3,     6,     8,    10,    12,     4,     3,     2,     2,     1,
-     1,     0,     0,     7,     1,     2,     2,     0,     0,     5,
-     1,     1,     3,     3,     2,     2,     2,     3,     4,     4,
-     3,     4,     6,     6,     0,     1,     0,     1,     1,     0,
-     1,     1,     3,     4,     1,     3,     0,     1,     1,     1,
-     2,     2,     2,     1,     1,     2,     2,     2,     2,     1,
-     3,     2,     2,     4,     2,     2,     2,     2,     2,     2,
-     1,     2,     1,     3,     1,     1,     0,     0,     1,     0,
-     4,     1,     1,     3,     0,     3,     3,     3,     1,     2,
+     1,     1,     1,     1,     1,     2,     2,     1,     1,     1,
+     1,     1,     1,     1,     3,     3,     0,     4,     0,     6,
+     2,     4,     2,     2,     1,     4,     1,     7,     7,     7,
+     7,     4,     4,     2,     2,     1,     4,     2,     2,     2,
+     5,     3,     5,     3,     4,     6,     1,     2,     1,     2,
+     1,     1,     1,     2,     0,     2,     2,     3,     3,     3,
+     3,     3,     2,     2,     1,     1,     1,     2,     2,     2,
+     2,     1,     1,     1,     1,     2,     2,     3,     3,     4,
+     1,     2,     2,     1,     1,     2,     2,     1,     2,     2,
+     3,     1,     2,     1,     1,     1,     4,     4,     4,     4,
+     1,     1,     1,     1,     3,     1,     3,     1,     3,     0,
+     4,     0,     7,     4,     0,     7,     4,     0,     7,     4,
+     0,     7,     4,     0,     1,     1,     2,     6,     1,     3,
+     0,     1,     4,     6,     4,     1,     1,     1,     1,     1,
+     3,     1,     2,     3,     4,     1,     1,     3,     4,     6,
+     3,     5,     0,     7,     4,     0,     6,     3,     2,     2,
+     4,     1,     0,     1,     0,     1,     1,     2,     2,     2,
+     2,     3,     2,     2,     2,     3,     3,     1,     2,     0,
+     0,     3,     3,     2,     1,     1,     0,     1,     2,     1,
+     3,     1,     2,     1,     4,     4,     1,     1,     2,     2,
+     1,     0,     1,     4,     3,     1,     2,     2,     2,     2,
+     2,     2,     2,     2,     4,     2,     1,     5,     3,     0,
+     1,     3,     0,     1,     3,     1,     1,     1,     1,     4,
+     6,     4,     4,     6,     4,     3,     4,     6,     4,     4,
+     6,     4,     3,     1,     3,     1,     3,     2,     1,     6,
+     0,     2,     1,     2,     0,     2,     3,     3,     2,     2,
+     3,     1,     1,     1,     2,     5,     5,     3,     5,     4,
+     3,     3,     2,     1,     3,     3,     2,     2,     3,     1,
+     3,     3,     2,     2,     3,     1,     5,     5,     3,     5,
+     3,     3,     4,     3,     2,     2,     1,     2,     4,     4,
+     2,     1,     1,     1,     2,     2,     2,     1,     2,     1,
+     2,     2,     3,     1,     3,     2,     3,     2,     2,     3,
+     1,     3,     4,     3,     2,     2,     1,     3,     2,     2,
+     1,     2,     3,     1,     3,     1,     5,     3,     4,     3,
+     4,     2,     2,     3,     2,     1,     1,     2,     2,     2,
+     0,     0,     1,     1,     2,     3,     1,     2,     3,     5,
+     6,     5,     0,     0,     6,     1,     2,     1,     1,     1,
+     2,     0,     4,     1,     0,     0,     6,     0,     0,     7,
+     0,     0,     0,    10,     0,     0,     0,    10,     0,     7,
+     0,     5,     0,     7,     0,     4,     2,     2,     2,     3,
+     6,     8,    10,    12,     4,     3,     2,     2,     1,     1,
+     0,     0,     7,     1,     2,     2,     0,     0,     5,     1,
+     1,     3,     3,     2,     2,     2,     3,     4,     4,     3,
+     4,     6,     6,     0,     1,     0,     1,     1,     0,     1,
+     1,     3,     4,     1,     3,     0,     1,     1,     1,     2,
+     2,     2,     1,     1,     2,     2,     2,     2,     1,     3,
+     2,     2,     4,     2,     2,     2,     2,     2,     2,     1,
+     2,     1,     3,     1,     1,     0,     0,     1,     0,     4,
+     1,     1,     3,     0,     3,     3,     3,     1,     2,     2,
      2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
      2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-     2,     2,     3,     2,     2,     2,     2,     3,     2,     2,
-     4,     4,     3,     2
+     2,     3,     2,     2,     2,     2,     3,     2,     2,     4,
+     4,     3,     2
 };
 
 static const short yydefact[] = {     3,
-    10,    10,     5,     0,     4,     0,   220,   523,   307,   317,
-   475,     0,     8,     9,     0,     0,   389,     0,   709,     0,
-   535,   221,    64,     0,     0,   697,     0,    76,    21,     0,
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+   627,   571,   571,     0,     0,   335,   415,   416,   455,   452,
+   438,     0,     0,   344,   330,   330,   450,   453,   357,   358,
+   359,   356,     0,   349,   352,   342,     0,     0,     0,     0,
+   369,     0,     0,   126,   240,     0,   174,   543,   266,   557,
+   123,   361,     0,     0,     0,   586,     0,     0,   571,   647,
+     0,   650,     0,     0,   611,     0,   620,     0,   626,   631,
+     0,   279,   330,   281,   282,   330,     0,     0,     0,   278,
+   280,   581,   571,     0,     0,   333,   339,     0,    77,   344,
+   344,   463,   344,   344,     0,     0,   351,     0,     0,   248,
+   249,   250,   251,     0,   372,   127,   470,   137,     0,   584,
+   596,   587,   599,   651,   649,     0,   648,   144,     0,   308,
+     0,     0,     0,   616,   625,     0,     0,   593,   141,     0,
+   140,     0,   336,   462,   459,   457,   460,   451,   454,   350,
+   348,   220,     0,   370,     0,   571,     0,     0,     0,     0,
+   609,   699,   613,   612,     0,   634,     0,   632,   659,     0,
+   602,   606,     0,     0,     0,   353,   355,   138,   585,   572,
+   597,   148,   135,     0,     0,   653,     0,   652,   571,   330,
+     0,   636,   635,   637,     0,     0,   660,   661,   621,     0,
+     0,   458,   461,     0,   145,     0,     0,   600,   610,   344,
+   614,   633,     0,   659,     0,     0,     0,     0,   354,     0,
+     0,   136,     0,   638,     0,     0,   622,   662,   603,   607,
+   147,   146,   142,     0,   663,     0,     0,     0,     0,     0,
+     0,     0,   664,     0,   623,   604,   608,   143,     0,     0,
+   639,     0,     0,   642,   643,   665,   624,     0,     0,     0
 };
 
-static const short yydefgoto[] = {  1354,
-     1,     2,   120,   568,   987,     3,     4,    31,    32,    33,
-   300,   551,   552,   553,    34,    91,    35,   577,   579,   578,
-   580,   576,    36,    37,    38,   415,   129,   130,   131,   341,
-   586,   587,   539,   588,   177,    39,    40,    41,   135,   262,
-   263,   303,   813,   304,  1151,   264,   988,  1281,  1216,  1236,
-  1237,  1336,  1277,   293,   793,   265,   448,   500,   757,   266,
-   267,   268,   294,   270,   510,   313,    43,   271,   460,  1052,
-   272,   273,   274,   275,   132,   276,   989,   405,   520,   777,
-   990,    45,   162,   991,    47,   163,   443,   164,   144,   156,
-    49,   635,   145,  1120,   406,  1194,   157,  1121,    50,  1040,
-   687,   688,   689,  1139,  1140,  1141,   969,   720,   721,    51,
-   543,   289,   912,   802,    52,    53,    54,    55,   181,   182,
-    56,    57,    58,   411,   651,   652,   653,   654,   184,   418,
-   419,   420,   421,   665,   671,   666,  1027,   667,   668,  1028,
-  1029,   540,   541,   501,   783,    59,   374,   375,   146,    60,
-    61,   147,   148,   114,    63,   511,   281,   282,   283,    65,
-   284,    67,    68,   180,    69,   285,   762,   763,   778,   523,
-   993,   994,  1161,   836,   837,   838,   350,   995,   996,  1084,
-  1252,  1163,   997,   998,  1189,  1085,  1253,  1086,  1254,  1118,
-  1296,  1334,  1119,  1297,  1335,  1285,  1229,  1287,  1172,   999,
-  1232,  1290,  1264,  1308,  1330,  1227,  1338,  1000,  1001,  1002,
-  1100,   727,  1292,  1293,  1294,  1340,   367,   779,   369,   370,
-   371,   558,   372,   107,   625,  1179,   683,   684,   438,    71,
+static const short yydefgoto[] = {  1348,
+     1,     2,   119,   564,   982,     3,     4,    31,    32,    33,
+   299,   548,   549,   550,    34,    91,    35,   573,   575,   574,
+   576,   572,    36,    37,    38,   412,   128,   129,   130,   339,
+   582,   583,   536,   584,   176,    39,    40,    41,   134,   261,
+   262,   302,   809,   303,  1145,   263,   983,  1275,  1210,  1230,
+  1231,  1330,  1271,   292,   789,   264,   445,   497,   753,   265,
+   266,   267,   293,   269,   507,   312,    43,   270,   457,  1047,
+   271,   272,   273,   274,   131,   275,   984,   402,   517,   773,
+   985,    45,   161,   986,    47,   162,   440,   163,   143,   155,
+    49,   631,   144,  1114,   403,  1188,   156,  1115,    50,  1035,
+   683,   684,   685,  1133,  1134,  1135,   964,   716,   717,    51,
+   540,   288,   906,   798,    52,    53,    54,    55,   180,   181,
+    56,    57,    58,   408,   647,   648,   649,   650,   183,   415,
+   416,   417,   418,   661,   667,   662,  1022,   663,   664,  1023,
+  1024,   537,   538,   498,   779,    59,   372,   373,   145,    60,
+    61,   146,   147,   113,    63,   508,   280,   281,   282,    65,
+   283,    67,    68,   179,    69,   284,   758,   759,   770,   520,
+   988,   989,  1155,   832,   833,   834,   348,   990,   991,  1078,
+  1246,  1157,   992,   993,  1183,  1079,  1247,  1080,  1248,  1112,
+  1290,  1328,  1113,  1291,  1329,  1279,  1223,  1281,  1166,   994,
+  1226,  1284,  1258,  1302,  1324,  1221,  1332,   995,   996,   997,
+  1094,   723,  1286,  1287,  1288,  1334,   365,   775,   367,   368,
+   369,   555,   370,   107,   621,  1173,   679,   680,   435,    71,
     72
 };
 
-static const short yypact[] = {    64,
-    80,-32768,-32768,  2131,-32768,   130,-32768,   283,    48,-32768,
--32768,   556,-32768,-32768,    66,    87,-32768,   206,-32768,  2650,
--32768,   210,-32768,  1299,  1299,-32768,  1901,-32768,-32768,   292,
--32768,   333,  3137,-32768,-32768,-32768,-32768,   573,   353,   368,
--32768,-32768,   166,  1701,-32768,  2829,-32768,  1033,   294,-32768,
--32768,   540,-32768,-32768,-32768,-32768,-32768,   396,  1486,-32768,
--32768,   591,-32768,-32768,-32768,    82,-32768,-32768,-32768,   214,
-  6712,-32768,-32768,-32768,-32768,  8620,  2499,-32768,   283,   210,
-   355,   414,   368,-32768,   214,-32768,   214,  8620,  8620,-32768,
-   512,-32768,   210,-32768,  4042,  3298,     1,   214,  8446,   283,
-  2225,-32768,   361,   267,  2225,-32768,   262,  2706,  2706,  1901,
-   383,   435,   166,   453,   495,   498,-32768,   571,   446,  2532,
-   224,  4042,  3192,   680,   723,   521,   617,-32768,    55,    16,
-   143,   143,-32768,-32768,   546,-32768,  6059,   532,-32768,  3255,
-  3255,  4407,   641,   569,-32768,-32768,   255,-32768,-32768,    82,
--32768,-32768,-32768,-32768,  1033,   669,-32768,   998,-32768,-32768,
--32768,  1070,   673,-32768,-32768,  4042,-32768,-32768,-32768,-32768,
--32768,-32768,-32768,-32768,-32768,-32768,-32768,   368,   775,-32768,
-   609,   609,-32768,  2064,-32768,   673,-32768,   604,   970,-32768,
--32768,-32768,-32768,  3851,-32768,    50,-32768,   605,   633,-32768,
--32768,-32768,-32768,   640,-32768,-32768,-32768,-32768,-32768,-32768,
+static const short yypact[] = {   203,
+   236,-32768,-32768,  1874,-32768,    85,-32768,    55,   300,-32768,
+-32768,   590,-32768,-32768,   -23,   252,-32768,   365,-32768,  1493,
+-32768,   355,-32768,   963,   963,-32768,  2214,-32768,-32768,   349,
+-32768,   429,  3939,-32768,-32768,-32768,-32768,   279,   435,   443,
+-32768,-32768,   396,  1052,-32768,  9215,-32768,   704,    30,-32768,
+-32768,   698,-32768,-32768,-32768,-32768,-32768,   488,  1610,-32768,
+-32768,   410,-32768,-32768,-32768,   397,-32768,-32768,-32768,    89,
+  6309,-32768,-32768,-32768,-32768,  8124,  2133,-32768,    55,   355,
+   461,   515,   443,-32768,    89,-32768,    89,  8124,  8124,-32768,
+   363,-32768,   355,-32768,  3239,  4205,   230,    89,  7950,    55,
+  2347,-32768,   484,   103,  2347,-32768,    92,  2356,  2356,   479,
+   501,   396,   514,   519,   540,-32768,   629,   555,  2912,   144,
+  3239,  9396,   593,   706,   572,   666,-32768,   149,   306,    57,
+    57,-32768,-32768,   575,-32768,  4662,   589,-32768,  3833,  3833,
+  3542,  1266,   393,-32768,-32768,   408,-32768,-32768,   397,-32768,
+-32768,-32768,-32768,   704,   536,-32768,  1285,-32768,-32768,-32768,
+   907,   654,-32768,-32768,  3239,-32768,-32768,-32768,-32768,-32768,
+-32768,-32768,-32768,-32768,-32768,-32768,   443,   719,-32768,   617,
+   617,-32768,  2447,-32768,   654,-32768,   608,   875,-32768,-32768,
+-32768,-32768,  4014,-32768,    56,-32768,   609,   647,-32768,-32768,
+-32768,-32768,   683,-32768,-32768,-32768,-32768,-32768,-32768,-32768,
 -32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,
--32768,-32768,-32768,-32768,-32768,-32768,   601,-32768,-32768,   673,
-  1486,   654,   627,-32768,-32768,  9561,  9644,   659,   664,-32768,
--32768,-32768,-32768,-32768,-32768,   675,   689,   696,   698,   701,
-   262,  9312,-32768,-32768,  9312,-32768,-32768,  9312,  6796,  3961,
--32768,   422,-32768,  9312,-32768,  8707,-32768,-32768,  9780,-32768,
-   845,  1829,  8790,-32768,   781,   434,-32768,   126,  1601,  4144,
--32768,   160,-32768,   475,   813,  4042,     1,-32768,   262,   690,
--32768,   721,   743,  9688,   726,   728,   734,   800,-32768,  2499,
--32768,   609,-32768,-32768,-32768,   478,-32768,   125,-32768,-32768,
--32768,-32768,-32768,  2225,-32768,-32768,  2225,-32768,   758,-32768,
--32768,  3851,    47,-32768,   729,  2499,-32768,-32768,-32768,-32768,
-   521,   708,-32768,-32768,-32768,-32768,-32768,-32768,   712,-32768,
-   249,-32768,  6886,  8877,-32768,   143,   143,   803,-32768,-32768,
--32768,-32768,-32768,   855,   765,-32768,-32768,   743,   767,  9688,
-   296,  2466,  3192,  2466,  3043,  3464,   772,-32768,   100,  3351,
-   807,   819,-32768,   776,  8877,  3862,-32768,  3862,-32768,  4280,
-  4280,  4407,   785,-32768,-32768,-32768,   970,  4042,-32768,-32768,
-  6161,   792,-32768,  4311,  1070,  1033,  4042,-32768,-32768,-32768,
-   970,-32768,-32768,-32768,   521,-32768,-32768,-32768,-32768,   905,
--32768,-32768,-32768,  8877,   447,  1155,  3724,    60,  1544,-32768,
-   252,   521,   673,  2142,   802,   867,-32768,-32768,-32768,   796,
-   798,-32768,-32768,-32768,-32768,   164,-32768,-32768,  8877,   627,
-  6796,-32768,   229,  6796,-32768,  8877,  8964,  9312,  8620,  2142,
-  2142,  2142,  2142,-32768,-32768,-32768,-32768,   805,   809,   803,
-   810,-32768,  8620,-32768,-32768,  6623,  6796,-32768,  8877,  8877,
-  6976,  8877,  8877,  8877,  8877,  8877,  8877,  8877,  8877,  8877,
-  8877,  8877,  8877,  8877,  8877,  8877,  8877,  8877,  8877,  8877,
--32768,-32768,-32768,-32768,-32768,  8877,  8877,  8877,  8620,  1393,
-   564,   670,  7615,-32768,-32768,   283,   865,   912,-32768,   237,
-   244,   615,-32768,  1080,  1080,-32768,  3796,   814,   837,   884,
--32768,-32768,   490,  8090,   114,-32768,   188,-32768,-32768,  8877,
--32768,-32768,-32768,-32768,   626,-32768,-32768,-32768,   877,   874,
--32768,-32768,   262,-32768,  7438,  7528,-32768,-32768,-32768,-32768,
-   606,   879,-32768,-32768,  3594,   540,-32768,-32768,   887,-32768,
--32768,-32768,-32768,   844,-32768,   891,-32768,-32768,-32768,   712,
--32768,-32768,-32768,-32768,-32768,-32768,   893,   896,   897,   903,
-   867,-32768,-32768,   210,  8877,   906,-32768,   280,   420,   436,
--32768,  6263,  9757,-32768,   849,   143,-32768,-32768,-32768,    24,
--32768,-32768,-32768,-32768,-32768,-32768,   817,   817,  4802,-32768,
--32768,-32768,-32768,-32768,  8181,-32768,-32768,-32768,-32768,-32768,
--32768,-32768,-32768,-32768,   902,  6886,-32768,-32768,-32768,-32768,
-  3862,  3862,-32768,  4311,   867,-32768,   855,   861,   863,   866,
--32768,   872,-32768,  1070,-32768,   867,   712,-32768,   883,-32768,
-   923,-32768,-32768,   939,-32768,  9757,-32768,-32768,   922,    18,
--32768,  8877,  2818,   521,   930,-32768,-32768,-32768,   510,   611,
-   934,-32768,   521,   937,-32768,-32768,-32768,-32768,-32768,   748,
--32768,  3086,-32768,   281,   571,   916,   947,   867,-32768,-32768,
--32768,   282,   282,   282,   904,   908,  9051,   884,   913,   915,
-   192,   917,-32768,   918,   920,   938,   944,   948,   957,-32768,
--32768,   932,-32768,-32768,   975,   421,   338,  8877,   976,-32768,
-   987,   941,  9757,  9757,-32768,-32768,   988,  4588,  9818,  4862,
-  4703,  4168,  4535,  3669,  1937,  1937,  1937,  1334,  1334,  1050,
-  1050,   713,   713,   713,-32768,-32768,   955,   954,   959,   958,
-   961,  2142,   564,-32768,  6886,  8877,-32768,-32768,-32768,  8877,
--32768,-32768,   980,  9312,   967,   981,  1030,-32768,  8877,-32768,
-  8877,-32768,  1350,-32768,  1350,-32768,    71,   977,   978,-32768,
-   973,  2142,   855,-32768,   855,  1728,-32768,  1109,   983,  8272,
-  8272,  5855,   979,  8707,   383,   984,   498,   813,   989,  8877,
-   262,   982,   874,-32768,  9757,-32768,  9757,  2499,-32768,  2761,
-   662,  6886,   396,-32768,   867,-32768,-32768,-32768,-32768,   708,
-   994,-32768,   249,-32768,  8877,-32768,  8877,-32768,  8877,-32768,
-   116,-32768,-32768,   262,-32768,  5585,  1049,-32768,   855,   855,
-  1260,  1260,  1918,  1918,  4802,-32768,    82,-32768,  2412,  8359,
-  8359,  5957,   240,  1005,   341,   855,  6886,-32768,  1031,-32768,
--32768,-32768,-32768,  1051,   867,  8620,   905,-32768,-32768,-32768,
-  8877,  8877,   152,  4929,  1006,-32768,   401,   712,   712,  3568,
-   755,  2290,   867,  2142,-32768,    54,  1023,-32768,-32768,-32768,
--32768,-32768,-32768,-32768,  9395,  9395,  7066,-32768,-32768,-32768,
--32768,-32768,-32768,  1024,  1029,  1032,  1034,-32768,  4688,  6886,
-  6353,  1020,-32768,  8877,-32768,-32768,-32768,-32768,   474,  1035,
--32768,-32768,  1039,    44,   181,   181,  1027,   181,-32768,-32768,
-  9312,  1128,-32768,  1044,  1046,-32768,-32768,-32768,-32768,-32768,
--32768,   855,  1059,-32768,  1047,  1062,-32768,-32768,   452,-32768,
-  9757,-32768,-32768,  1063,-32768,-32768,-32768,  2064,   708,-32768,
--32768,-32768,  1068,  1071,  1073,  6443,-32768,-32768,   745,   289,
-  1075,   575,-32768,-32768,-32768,  1065,-32768,  8877,  1116,  1121,
-  1122,  8533,    67,   572,-32768,  1129,  1175,  1131,-32768,  2565,
-  4428,  2918,  5022,-32768,-32768,  1170,-32768,-32768,-32768,  7718,
--32768,-32768,-32768,  1260,  1260,-32768,  2412,  1408,-32768,-32768,
-   855,   855,   855,-32768,  1132,  1089,  1093,-32768,  4929,  4929,
--32768,-32768,-32768,  1138,   624,  8877,-32768,-32768,-32768,   521,
-   521,   867,   867,-32768,  2406,-32768,-32768,-32768,   583,  6886,
-  8877,  8877,  8877,  8877,  6886,-32768,  8877,  1140,-32768,-32768,
-  9801,   546,  8877,-32768,   474,-32768,-32768,-32768,-32768,-32768,
--32768,  1100,-32768,  1163,-32768,-32768,   855,-32768,-32768,-32768,
--32768,    73,-32768,-32768,-32768,-32768,-32768,   262,-32768,-32768,
--32768,-32768,-32768,-32768,-32768,   803,  6533,  1123,  4518,-32768,
--32768,-32768,-32768,  1153,  8877,  1158,-32768,-32768,-32768,  1130,
--32768,-32768,   191,   763,-32768,   788,   521,  9138,   427,   797,
-   307,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,  6886,
-  6886,-32768,-32768,-32768,-32768,-32768,   152,  8877,  8877,  4929,
-   712,   712,  1159,  1161,-32768,-32768,-32768,-32768,   315,-32768,
-  1133,-32768,  1120,  1126,  1127,  1137,-32768,  9711,  6886,   546,
--32768,  1119,-32768,-32768,-32768,   855,-32768,-32768,   462,   462,
-  8000,-32768,  1210,  1184,  1139,-32768,  1189,-32768,  8620,  8877,
--32768,  7820,-32768,  1190,-32768,-32768,   571,-32768,   712,-32768,
--32768,   712,  9478,  9478,  7156,-32768,-32768,-32768,   803,  7246,
-  7246,-32768,-32768,  6886,-32768,  4929,  4929,-32768,   867,   867,
-  6886,  6886,   583,  1146,  9225,-32768,-32768,-32768,-32768,  6886,
--32768,-32768,-32768,-32768,  8620,-32768,-32768,-32768,-32768,-32768,
--32768,  5675,-32768,-32768,  1148,   416,  4042,  9734,  7820,-32768,
--32768,  5141,    51,-32768,-32768,  1198,-32768,  1199,-32768,-32768,
--32768,  1174,  1200,-32768,-32768,-32768,-32768,   369,  1154,-32768,
-  1160,   803,  7910,   527,   370,  5273,-32768,   521,-32768,-32768,
-   379,-32768,  5377,-32768,  1248,  1204,-32768,-32768,  6886,  6886,
-  8877,-32768,-32768,-32768,-32768,    25,-32768,-32768,-32768,  8877,
-  1205,-32768,  1213,-32768,   803,   712,  7820,-32768,-32768,-32768,
-  1178,   271,  1216,-32768,-32768,  7336,  7336,-32768,-32768,  1171,
--32768,  5765,  1172,-32768,-32768,   867,-32768,  1181,  8877,  1248,
-  1222,  1248,  1177,  1187,-32768,   397,  5481,-32768,  1233,-32768,
-  1192,   365,-32768,-32768,-32768,-32768,-32768,-32768,-32768,  1208,
--32768,  1271,  1236,  7910,  7910,  6886,  3413,   803,-32768,   410,
--32768,-32768,-32768,-32768,  1195,  1197,-32768,  1296,  1251,-32768,
--32768,-32768,-32768,  1308,  1309,-32768
+-32768,-32768,-32768,-32768,-32768,   601,-32768,-32768,   654,  1610,
+   351,   657,-32768,-32768,  3117,  9065,   660,   662,-32768,-32768,
+-32768,-32768,-32768,-32768,   665,   690,   692,   699,   703,    92,
+  8816,-32768,-32768,  8816,-32768,-32768,  8816,  6393,  9148,-32768,
+    29,-32768,  8816,-32768,  8211,-32768,-32768,  9444,-32768,  1334,
+  2712,  8294,-32768,   767,   557,-32768,   160,  2819,  9439,-32768,
+   266,-32768,   579,   809,  3239,   230,-32768,    92,   685,-32768,
+   684,   738,  9497,   693,   697,   701,   808,-32768,  2133,-32768,
+   617,-32768,-32768,-32768,   154,-32768,   139,-32768,-32768,-32768,
+-32768,-32768,  2347,-32768,-32768,  2347,-32768,-32768,-32768,  4014,
+    50,-32768,   711,  2133,-32768,-32768,-32768,-32768,   572,   766,
+-32768,-32768,-32768,-32768,-32768,-32768,   656,-32768,   254,-32768,
+  6483,  8381,-32768,    57,    57,   765,-32768,-32768,-32768,-32768,
+-32768,   818,   730,-32768,-32768,   738,   735,  9497,   328,  1775,
+  9396,  1775,  4904,  4548,   737,-32768,    72,  9289,   763,   787,
+-32768,   746,  8381,  4250,-32768,  4250,-32768,  4314,  4314,   753,
+-32768,-32768,-32768,   875,  3239,-32768,-32768,  5854,   752,-32768,
+  4433,   907,   704,  3239,-32768,-32768,-32768,   875,-32768,-32768,
+-32768,   572,-32768,-32768,-32768,-32768,  1191,-32768,-32768,-32768,
+  8381,   156,  1389,  9306,    54,  2311,-32768,   167,   572,   654,
+  2569,   771,   831,-32768,-32768,-32768,   773,   777,-32768,-32768,
+-32768,-32768,   169,-32768,-32768,  8381,   657,  6393,-32768,   381,
+  6393,-32768,  8381,  8468,  8816,  8124,  2569,  2569,  2569,  2569,
+-32768,-32768,-32768,-32768,   782,   784,   765,   793,-32768,  8124,
+-32768,-32768,  3487,  6393,-32768,  8381,  8381,  3006,  8381,  8381,
+  8381,  8381,  8381,  8381,  8381,  8381,  8381,  8381,  8381,  8381,
+  8381,  8381,  8381,  8381,  8381,  8381,  8381,-32768,-32768,-32768,
+-32768,-32768,  8381,  8381,  8381,  8124,  3398,   497,   109,  7032,
+-32768,-32768,    55,   848,   896,-32768,   387,   415,   592,-32768,
+   388,   388,-32768,  3838,   798,   817,   864,-32768,-32768,   412,
+  7507,  1099,-32768,   251,-32768,-32768,  8381,-32768,-32768,-32768,
+-32768,   597,-32768,-32768,-32768,   851,   855,-32768,-32768,    92,
+-32768,  6855,  6945,-32768,-32768,-32768,-32768,   419,   859,-32768,
+-32768,  9200,   698,-32768,-32768,   862,-32768,-32768,-32768,-32768,
+-32768,   865,-32768,-32768,-32768,   656,-32768,-32768,-32768,-32768,
+-32768,-32768,   866,   868,   869,   870,   831,-32768,-32768,   355,
+  8381,   877,-32768,   434,   438,   462,-32768,  5956,  9590,-32768,
+   836,    57,-32768,-32768,-32768,    20,-32768,-32768,-32768,-32768,
+-32768,-32768,  1506,  1506,  3333,-32768,-32768,-32768,-32768,-32768,
+  7598,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,
+   887,  6483,-32768,-32768,-32768,-32768,  4250,  4250,-32768,  4433,
+   831,-32768,   818,   849,   856,   861,-32768,   863,-32768,   907,
+-32768,   831,   656,-32768,   881,-32768,   899,-32768,-32768,  1243,
+-32768,  9590,-32768,-32768,   912,   146,-32768,  8381,  2808,   572,
+   921,-32768,-32768,-32768,   368,   407,   922,-32768,   572,   920,
+-32768,-32768,-32768,-32768,-32768,   551,-32768,  4154,-32768,   187,
+   629,   897,   926,   831,-32768,-32768,-32768,   505,   505,   505,
+   885,   886,  8555,   864,   895,   900,   248,   901,-32768,   906,
+   909,   919,   942,   943,   945,-32768,-32768,   918,-32768,-32768,
+   962,   553,   136,  8381,   969,-32768,   968,   928,  9590,  9590,
+-32768,-32768,   973,  9629,  4583,  9645,  9660,  5903,  6801,  3406,
+  1324,  1324,  1324,  1664,  1664,   814,   814,   640,   640,   640,
+-32768,-32768,   932,   934,   940,   935,   946,  2569,   497,-32768,
+  6483,  8381,-32768,-32768,-32768,  8381,-32768,-32768,   955,  8816,
+   944,   964,  1008,-32768,  8381,-32768,  8381,-32768,   890,-32768,
+   890,-32768,    65,   951,   952,-32768,   953,  2569,   818,-32768,
+   818,  2046,-32768,  1065,   957,  7689,  7689,  4811,   966,  8211,
+   479,   972,   540,   809,   974,  8381,    92,   961,   855,-32768,
+  9590,-32768,  9590,  2133,-32768,   664,   520,  6483,   488,-32768,
+   831,-32768,-32768,-32768,-32768,   766,   978,-32768,   254,-32768,
+  8381,-32768,  8381,-32768,  8381,-32768,     9,-32768,-32768,    92,
+-32768,  5584,  1032,-32768,   818,   818,  2757,  2757,  3282,  3282,
+-32768,   397,-32768,  3954,  7776,  7776,  5016,   174,   979,   244,
+   818,  6483,-32768,  1030,-32768,-32768,-32768,-32768,  1037,   831,
+  8124,  1191,-32768,-32768,-32768,  8381,  8381,    74,  9521,   995,
+-32768,  2416,   656,   656,  3185,   603,  3228,   831,  2569,-32768,
+    52,  1011,-32768,-32768,-32768,-32768,-32768,-32768,-32768,  8899,
+  8899,-32768,-32768,-32768,-32768,-32768,-32768,  1013,  1014,  1019,
+  1022,-32768,  9472,  6483,  6046,  1009,-32768,  8381,-32768,-32768,
+-32768,-32768,   143,  1012,-32768,-32768,  1017,    75,   278,   278,
+  1006,   278,-32768,-32768,  8816,  1107,-32768,  1018,  1020,-32768,
+-32768,-32768,-32768,-32768,-32768,   818,  1023,-32768,  1010,  7863,
+  7863,-32768,-32768,   584,-32768,  9590,-32768,-32768,  1021,-32768,
+-32768,-32768,  2447,   766,-32768,-32768,-32768,  1024,  1026,  1036,
+  6136,-32768,-32768,   668,   231,  1061,   567,-32768,-32768,-32768,
+  1046,-32768,  8381,  1079,  1085,  1088,  8037,    73,   476,-32768,
+  1093,  1139,  1094,-32768,  1971,  9379,  2582,  3725,-32768,-32768,
+  1135,-32768,-32768,-32768,  7135,-32768,-32768,-32768,  2757,  2757,
+-32768,  3954,  1989,-32768,-32768,   818,   818,   818,-32768,  1095,
+  1053,  1054,-32768,  9521,  9521,-32768,-32768,-32768,  1103,   661,
+  8381,-32768,-32768,-32768,   572,   572,   831,   831,-32768,  2607,
+-32768,-32768,-32768,   801,  6483,  8381,  8381,  8381,  8381,  6483,
+-32768,  8381,  1104,-32768,-32768,  9611,   575,  8381,-32768,   143,
+-32768,-32768,-32768,-32768,-32768,-32768,  1062,-32768,  1122,-32768,
+-32768,   818,-32768,-32768,-32768,    66,-32768,-32768,-32768,-32768,
+-32768,    92,-32768,-32768,-32768,-32768,-32768,-32768,-32768,   765,
+  6226,  1082,  5075,-32768,-32768,-32768,-32768,  1115,  8381,  1121,
+-32768,-32768,-32768,  1090,-32768,-32768,   238,   672,-32768,   772,
+   572,  8642,   459,   774,   258,-32768,-32768,-32768,-32768,-32768,
+-32768,-32768,-32768,  6483,  6483,-32768,-32768,-32768,-32768,-32768,
+    74,  8381,  8381,  9521,   656,   656,  1124,  1126,-32768,-32768,
+-32768,-32768,   269,-32768,  1091,-32768,  1084,  1087,  1097,  1098,
+-32768,  9544,  6483,   575,-32768,  1089,-32768,-32768,-32768,   818,
+-32768,-32768,   509,   509,  7417,-32768,  1175,  1137,  1100,-32768,
+  1141,-32768,  8124,  8381,-32768,  7237,-32768,  1146,-32768,-32768,
+   629,-32768,   656,-32768,-32768,   656,  8982,  8982,  6573,-32768,
+-32768,-32768,   765,  6663,  6663,-32768,-32768,  6483,-32768,  9521,
+  9521,-32768,   831,   831,  6483,  6483,   801,  1102,  8729,-32768,
+-32768,-32768,-32768,  6483,-32768,-32768,-32768,-32768,  8124,-32768,
+-32768,-32768,-32768,-32768,-32768,  5674,-32768,-32768,  1109,   234,
+  3239,  9567,  7237,-32768,-32768,  5168,    48,-32768,-32768,  1149,
+-32768,  1150,-32768,-32768,-32768,  1160,  1163,-32768,-32768,-32768,
+-32768,   282,  1123,-32768,  1127,   765,  7327,   518,   295,  5272,
+-32768,   572,-32768,-32768,   296,-32768,  5376,-32768,  1214,  1168,
+-32768,-32768,  6483,  6483,  8381,-32768,-32768,-32768,-32768,    37,
+-32768,-32768,-32768,  8381,  1176,-32768,  1177,-32768,   765,   656,
+  7237,-32768,-32768,-32768,  1147,   201,  1181,-32768,-32768,  6753,
+  6753,-32768,-32768,  1143,-32768,  5764,  1148,-32768,-32768,   831,
+-32768,  1158,  8381,  1214,  1183,  1214,  1151,  1152,-32768,   317,
+  5480,-32768,  1198,-32768,  1156,   246,-32768,-32768,-32768,-32768,
+-32768,-32768,-32768,  1153,-32768,  1254,  1208,  7327,  7327,  6483,
+  1355,   765,-32768,   353,-32768,-32768,-32768,-32768,  1167,  1170,
+-32768,  1271,  1219,-32768,-32768,-32768,-32768,  1281,  1282,-32768
 };
 
 static const short yypgoto[] = {-32768,
-  1191,-32768,-32768,   986,     7,  1310,-32768,-32768,-32768,-32768,
--32768,-32768,-32768,   507,-32768,-32768,-32768,-32768,-32768,-32768,
--32768,  -770,  1196,  1207,-32768,-32768,-32768,-32768,  1201,-32768,
--32768,   496,   135,-32768,-32768,-32768,  2838,   -25,-32768,  1221,
-   888,  -999,-32768,   -88,   178,-32768,   895,-32768,   169,   139,
- -1101,-32768,  -524,  1474,   -99,   619,-32768,-32768,  -714,  3947,
-    43,  -240,  2252,  2872,   825,  1176,   432,-32768,-32768,-32768,
--32768,  -273,-32768,  -116,   -94,-32768,   266,    17,  -276,   132,
-    75,  -106,  -109,    -3,  1594,    27,  1371,  -118,  -752,   364,
--32768,   -82,-32768,-32768,   265,-32768,-32768,-32768,-32768,-32768,
-   327,-32768,   677,-32768,   155,-32768,-32768,   730,   769,    74,
--32768,-32768,-32768,   560,  -272,    13,  1335,  1336,-32768,-32768,
--32768,-32768,-32768,  -141,-32768,   500,   716,-32768,   559,   418,
-   497,  -414,-32768,-32768,-32768,-32768,-32768,-32768,   960,-32768,
-   501,   835,   582,   889,  2241,  1820,  -368,-32768,  3695,   -55,
-    10,-32768,  4252,   -90,   717,-32768,  3290,-32768,-32768,  3834,
-    -4,   245,  -328,  1372,  3416,   871,  -214,-32768,  4134,-32768,
- -1157,  -942,  -343,   117,-32768,   553,   -97,  -122,-32768,-32768,
--32768, -1137,  -860, -1112,-32768,-32768,-32768,-32768,-32768,-32768,
+  1165,-32768,-32768,   958,     7,  1283,-32768,-32768,-32768,-32768,
+-32768,-32768,-32768,   486,-32768,-32768,-32768,-32768,-32768,-32768,
+-32768,  -773,  1169,  1174,-32768,-32768,-32768,-32768,  1166,-32768,
+-32768,   478,   126,-32768,-32768,-32768,  4325,   -30,-32768,  1204,
+   844,  -998,-32768,   -96,   162,-32768,   171,-32768,   153,   124,
+  -980,-32768,  -480,   242,   564,   630,-32768,-32768,  -722,  3685,
+  1316,  -262,  2309,  2833,   804,   159,   431,-32768,-32768,-32768,
+-32768,  -278,-32768,  -110,   -90,-32768,   233,    34,  -210,    83,
+    11,   -91,  -121,    -3,  1446,   -82,  1348,  -127,  -674,   329,
+-32768,  -186,-32768,-32768,   180,-32768,-32768,-32768,-32768,-32768,
+  1092,-32768,   634,-32768,   122,-32768,-32768,   821,   742,    14,
+-32768,-32768,-32768,   526,  -285,    12,  1299,  1300,-32768,-32768,
+-32768,-32768,-32768,  -131,-32768,   473,   686,-32768,   533,   394,
+   469,  -411,-32768,-32768,-32768,-32768,-32768,-32768,   939,-32768,
+   482,   829,   573,   857,  1683,  1544,  -371,-32768,  1375,     0,
+     1,-32768,  4129,   -99,   646,-32768,  3274,-32768,-32768,  3935,
+    -4,   198,  -327,  1336,  3574,   852,  -188,-32768,  1912,-32768,
+ -1147,  -942,  -321,   101,-32768,   539,  -106,   -94,-32768,-32768,
+-32768, -1132,  -932, -1108,-32768,-32768,-32768,-32768,-32768,-32768,
 -32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,
--32768,-32768,-32768,-32768,-32768,   -37,-32768,-32768,-32768,-32768,
--32768,  -425,    86,-32768,    90,-32768,  -354,  -133,-32768,-32768,
-  -293,  1052,  -286,-32768,-32768,    40,   530,-32768,    57,-32768,
+-32768,-32768,-32768,-32768,-32768,   -43,-32768,-32768,-32768,-32768,
+-32768,  -421,    70,-32768,    69,-32768,  -369,  -132,-32768,-32768,
+  -258,  1015,  -247,-32768,-32768,    60,   500,-32768,   127,-32768,
   -260
 };
 
 
-#define	YYLAST		9897
+#define	YYLAST		9739
 
 
 static const short yytable[] = {    66,
-    46,   323,   525,   368,   677,   600,   557,    85,   351,   351,
-    30,   533,   590,   559,   195,    85,    96,   315,   318,   103,
-   103,    84,   103,   642,   536,   468,   179,   556,    66,   123,
-   362,   291,    97,   232,   352,   347,   640,   359,   921,   150,
-   412,    66,   195,   403,   404,   395,   353,    85,  1218,   960,
-  1113,  1234,  1150,     8,    85,   505,  -124,   834,   834,   505,
-   143,    84,   505,    -1,  1256,   196,    85,  1225,    75,    78,
-   310,   345,    85,    96,  1263,   128,   557,   872,    44,    -2,
-   603,   655,    85,   559,     7,     8,    76,   513,   525,   287,
-   150,    85,    77,    85,    95,   674,   103,   302,   342,   308,
-   103,   189,    93,   103,   103,   103,   426,   122,   674,   618,
-  1265,   301,   343,  1251,  1275,    66,    46,   150,    66,   311,
-  -473,   165,    19,  -473,   429,   604,   835,  1301,   100,   100,
-   605,   697,  1114,   363,    22,   150,   150,   150,   331,  1117,
-  1278,  1095,   344,   348,  1317,  1057,    82,  1305,   566,   781,
-  1150,   286,  1266,    88,   619,  1038,   190,   784,   427,   620,
-   560,   150,   675,   606,    26,   339,   698,   100,  -473,   513,
-   966,  -473,   713,  -473,    89,  1157,    21,    93,    93,    66,
-   417,   396,   387,  -473,   100,    73,   176,   427,  1073,   103,
-   514,     8,   621,   362,    44,   425,   349,   401,   538,   429,
-   515,  -473,  -473,   529,  1054,  -700,  -473,   277,    90,   136,
-   516,  -700,   423,   517,   518,  -473,    93,     8,   967,   295,
-   297,  1278,  1278,   351,   351,   599,    85,   436,   165,   195,
-   277,    21,    74,    93,   502,   165,   165,  1104,   190,  1110,
-    93,   312,    75,   188,   595,   758,  1178,   530,   597,   598,
-   596,   582,     8,   137,   138,   759,   581,   368,   416,   165,
-    76,   533,   190,   362,    78,   310,    93,    85,   361,   760,
-   100,   512,   513,   436,   436,   527,   403,   404,    99,   329,
-   768,   150,   188,  -230,   362,   100,   644,   770,   427,   315,
-   318,   639,   583,   900,   455,    85,   363,   456,   390,    21,
-   457,   584,   537,   165,   404,   603,   465,   678,   875,   103,
-   193,  1230,   103,  1113,   311,   504,   697,   103,   646,    93,
-  1113,    85,    96,   824,   769,   655,   330,  -230,  -230,   193,
-  1310,   771,    21,    75,    93,   884,   585,   712,    97,   695,
-  1153,  -224,   391,   392,  1080,   425,   434,   193,   166,   167,
-   604,    76,   165,  -696,   679,   605,   435,   150,    66,   150,
-   150,   527,  1080,     7,   100,    66,   363,   825,  1260,  1203,
-   570,   150,  1311,   150,  1113,   150,   150,   150,   610,   118,
-   614,   616,   885,   150,  -231,   454,   119,   363,   606,   150,
-   461,  1081,   150,   425,   193,  1114,   747,  -103,   749,   750,
-    95,    19,  1114,  1024,  1025,    85,    99,   425,   133,  1188,
-   362,   150,    66,    22,    66,   417,  1204,   362,   134,    85,
-   945,   160,   161,  1271,  1332,  1080,  1307,    12,  -231,  -231,
-   799,   554,   664,   943,  1080,   190,     7,   506,   165,   507,
-   193,    19,  -225,    26,   647,    85,    85,    85,    85,   183,
-    17,    21,  1080,    22,     7,     8,  1114,   288,   113,   513,
-  1026,   680,   502,   826,  1348,   140,  1333,   290,   165,   165,
-  1272,    75,  1282,   351,    19,   141,   463,     7,     8,   828,
-  -102,  1288,  1186,    26,  -224,   821,    22,   815,   142,    76,
-   703,   464,    19,   416,   590,    85,   165,   436,   833,  1327,
-   657,   554,   362,   697,    22,  1214,   658,   827,   362,   436,
-   436,  1349,   527,   363,   557,    19,   508,   754,   188,    66,
-   363,   559,   361,   829,   533,   403,   429,    22,   193,   368,
-   179,   755,   463,   787,    26,   556,   320,   536,   655,   113,
-   113,   113,    78,    79,   168,   169,   170,   561,   324,  1215,
-   150,    85,   193,   468,   321,   681,   362,    26,    78,    79,
-  1062,   756,  1053,  -287,   865,    84,   298,   299,   886,  -287,
-  1279,   616,   696,   113,   171,   699,   425,   788,   789,   235,
-   705,   706,   707,   708,   709,    78,   310,  1135,  1136,  1137,
-    21,   187,    80,   172,   277,   127,  -508,   883,   722,  -225,
-   719,   188,   150,   150,   847,   363,    21,   754,    80,    81,
-   847,   363,   188,  -700,  1280,  -700,  -700,     7,   506,   340,
-   677,   755,  -700,   388,   389,    75,   150,   150,   165,   150,
-   751,  1097,   128,  1088,  1083,   311,   373,   173,   174,   175,
-    99,   385,   302,    76,  -700,  -700,  -700,   698,  -700,    85,
-  -700,   756,   636,   425,   368,    19,   923,   100,   847,   363,
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-   253,   254,  1184,     0,     0,     0,     0,     0,   256,   257,
-   258,     0,     0,     7,     8,  1185,    10,   440,   234,   235,
-     0,   236,    12,     0,     0,     0,     0,     0,     0,     0,
-     0,   261,     0,     0,     0,     0,     0,    15,   237,     0,
-     0,    16,     0,   240,     0,    17,     0,   241,   242,     0,
-   243,    19,   244,   245,     0,     0,   246,   247,   248,   249,
-   250,    21,     0,    22,     0,     0,     0,     0,     0,     0,
-     0,     0,   251,     0,     0,   252,     0,     0,     0,     0,
-     0,     0,     0,   253,   254,   255,     0,     0,     0,     0,
-     0,   256,   257,   258,     0,     0,     7,     8,   441,    10,
-   440,   234,   235,     0,   236,    12,     0,     0,     0,     0,
-     0,     0,     0,     0,   261,     0,     0,     0,     0,     0,
-    15,   237,     0,     0,    16,     0,   240,     0,    17,     0,
-   241,   242,     0,   243,    19,   244,   245,     0,     0,   246,
-   247,   248,   249,   250,    21,     0,    22,     0,     0,     0,
-     0,     0,     0,     0,     0,   251,     0,     0,   252,     0,
-     0,     0,     0,     0,     0,     0,   253,   254,   255,     0,
-     0,     0,     0,     0,   256,   257,   258,     0,     0,     0,
-     0,   444,     0,     0,     0,     0,     0,     0,     0,     0,
-     0,     0,   546,     0,   469,   470,   471,   261,   472,   473,
-   474,   475,   476,   477,   478,   479,   480,   481,   482,   483,
-   484,   485,   486,   487,   488,   489,   490,   469,   470,   471,
-  1210,   472,   473,   474,   475,   476,   477,   478,   479,   480,
-   481,   482,   483,   484,   485,   486,   487,   488,   489,   490,
-   469,   470,   471,  1259,   472,   473,   474,   475,   476,   477,
+     0,   250,     0,     0,   251,     0,     0,     0,     0,   304,
+     0,     0,   252,   253,   254,     0,     0,     0,     0,     0,
+   255,   256,   257,     0,     0,     0,     0,   258,     0,     7,
+     8,   259,    10,   437,   233,   234,     0,   235,    12,     0,
+     0,     0,     0,   260,     0,     0,     0,     0,     0,     0,
+     0,     0,     0,    15,   236,   237,   238,    16,     0,   239,
+     0,    17,     0,   240,   241,     0,   242,    19,   243,   244,
+     0,     0,   245,   246,   247,   248,   249,    21,     0,    22,
+     0,     0,  1087,     0,     0,     0,     0,     0,   250,     0,
+     0,   251,     0,     0,     0,     0,     0,     0,     0,   252,
+   253,   254,     0,     0,     0,     0,     0,   255,   256,   257,
+     0,     0,     0,     0,   258,     0,     7,     8,   259,    10,
+   232,   233,   234,     0,   235,    12,     0,     0,     0,     0,
+   260,     0,     0,     0,     0,     0,     0,     0,     0,     0,
+    15,   236,   237,   238,    16,     0,   239,     0,    17,     0,
+   240,   241,     0,   242,    19,   243,   244,     0,     0,   245,
+   246,   247,   248,   249,    21,     0,    22,     0,     0,     0,
+     0,     0,     0,     0,     0,   250,     0,     0,   251,     0,
+     0,     0,     0,     0,     0,     0,   252,   253,   254,     0,
+     0,     0,     0,     0,   255,   256,   257,     0,     0,     0,
+     0,   258,     0,     7,     8,   259,    10,   437,   233,   234,
+     0,   235,    12,     0,     0,     0,     0,   260,     0,     0,
+     0,     0,     0,     0,     0,     0,     0,    15,   236,   237,
+   238,    16,     0,   239,     0,    17,     0,   240,   241,     0,
+   242,    19,   243,   244,     0,     0,   245,   246,   247,   248,
+   249,    21,     0,    22,   463,     0,     0,     0,     0,     0,
+     0,     0,   250,     0,     0,   251,     0,     0,     0,     0,
+     0,     0,     0,   252,   253,   254,     0,     0,     0,     0,
+     0,   255,   256,   257,     0,     0,     7,     8,   464,    10,
+   437,   233,   234,     0,   235,    12,     0,     0,     0,     0,
+     0,     0,     0,     0,   260,     0,     0,     0,     0,     0,
+    15,   236,   237,   238,    16,     0,   239,     0,    17,     0,
+   240,   241,     0,   242,    19,   243,   244,     0,     0,   245,
+   246,   247,   248,   249,    21,     0,    22,     0,     0,     0,
+     0,     0,     0,     0,     0,   250,     0,     0,   251,     0,
+     0,     0,     0,     0,     0,     0,   252,   253,   254,     0,
+     0,     0,     0,     0,   255,   256,   257,     0,     0,     0,
+     0,   258,   500,     7,     8,     0,    10,   437,   233,   234,
+     0,   235,    12,     0,     0,     0,     0,   260,     0,     0,
+     0,     0,     0,     0,     0,     0,     0,    15,   236,   237,
+   238,    16,     0,   239,     0,    17,     0,   240,   241,     0,
+   242,    19,   243,   244,     0,     0,   245,   246,   247,   248,
+   249,    21,     0,    22,     0,     0,     0,     0,     0,     0,
+     0,     0,   250,     0,     0,   251,     0,     0,     0,     0,
+     0,     0,     0,   252,   253,   254,     0,     0,     0,     0,
+     0,   255,   256,   257,     0,     0,     0,     0,   258,     0,
+     7,   697,   259,    10,   437,   233,   234,     0,   235,    12,
+     0,     0,     0,     0,   260,     0,     0,     0,     0,     0,
+     0,     0,     0,     0,    15,   236,   237,   238,    16,     0,
+   239,     0,    17,     0,   240,   241,     0,   242,    19,   243,
+   244,     0,     0,   245,   246,   247,   248,   249,    21,     0,
+    22,     0,     0,     0,     0,     0,     0,     0,     0,   250,
+     0,     0,   251,     0,     0,     0,     0,     0,     0,     0,
+   252,   253,   254,     0,     0,     0,     0,     0,   255,   256,
+   257,     0,     0,     0,     0,   258,     0,     7,     8,   259,
+    10,   437,   233,   234,     0,   235,    12,     0,     0,     0,
+     0,   260,     0,     0,     0,     0,     0,     0,     0,     0,
+     0,    15,   236,   237,   238,    16,     0,   239,     0,    17,
+     0,   240,   241,     0,   242,    19,   243,   244,     0,     0,
+   245,   246,   247,   248,   249,    21,     0,    22,     0,     0,
+     0,     0,     0,     0,     0,     0,   250,     0,     0,   890,
+     0,     0,     0,     0,     0,     0,     0,   252,   253,   891,
+     0,     0,     0,     0,     0,   255,   256,   257,     0,     0,
+     0,     0,   258,     0,     7,     8,   259,    10,   437,   233,
+   234,     0,   235,    12,     0,     0,     0,     0,   260,     0,
+     0,     0,     0,     0,     0,     0,     0,     0,    15,   236,
+   237,   238,    16,     0,   239,     0,    17,     0,   240,   241,
+     0,   242,    19,   243,   244,     0,     0,   245,   246,   247,
+   248,   249,    21,     0,    22,     0,     0,     0,     0,     0,
+     0,     0,     0,   250,     0,     0,  1177,     0,     0,     0,
+     0,     0,     0,     0,   252,   253,  1178,     0,     0,     0,
+     0,     0,   255,   256,   257,     0,     0,     0,     0,  1179,
+     0,  1242,     8,   259,    10,   437,   233,   234,     0,   235,
+    12,     0,     0,     0,     0,   260,     0,     0,     0,     0,
+     0,     0,     0,     0,     0,    15,   236,   237,   238,    16,
+     0,   239,     0,    17,     0,   240,   241,     0,   242,    19,
+   243,   244,     0,     0,   245,   246,   247,   248,   249,    21,
+     0,    22,     0,     0,     0,     0,     0,     0,     0,     0,
+   250,     0,     0,   251,     0,     0,     0,     0,     0,     0,
+     0,   252,   253,   254,     0,     0,     0,     0,     0,   255,
+   256,   257,     0,     0,     0,     0,   258,     0,     7,     8,
+   259,    10,   437,   233,   234,     0,   235,    12,     0,     0,
+     0,     0,   260,     0,     0,     0,     0,     0,     0,     0,
+     0,     0,    15,   236,   237,   238,    16,     0,   239,     0,
+    17,     0,   240,   241,     0,   242,    19,   243,   244,     0,
+     0,   245,   246,   247,   248,   249,    21,     0,    22,     0,
+     0,     0,     0,     0,     0,     0,     0,   250,     0,     0,
+   251,     0,     0,     0,     0,     0,     0,     0,   252,   253,
+   254,     0,     0,     0,     0,     0,   255,   256,   257,     0,
+     0,     7,     8,   258,    10,   437,   233,   234,     0,   235,
+    12,     0,     0,     0,     0,     0,     0,     0,     0,   260,
+     0,     0,     0,     0,     0,    15,   236,   237,   238,    16,
+     0,   239,     0,    17,     0,   240,   241,     0,   242,    19,
+   243,   244,     0,     0,   245,   246,   247,   248,   249,    21,
+     0,    22,     0,     0,     0,     0,     0,     0,     0,     0,
+   250,     0,     0,   890,     0,     0,     0,     0,     0,     0,
+     0,   252,   253,   891,     0,     0,     0,     0,     0,   255,
+   256,   257,     0,     0,     7,     8,   258,    10,   232,   233,
+   234,     0,   235,    12,     0,     0,     0,     0,     0,     0,
+     0,     0,   260,     0,     0,     0,     0,     0,    15,   236,
+   237,   238,    16,     0,   239,     0,    17,     0,   240,   241,
+     0,   242,    19,   243,   244,     0,     0,   245,   246,   247,
+   248,   249,    21,     0,    22,     0,     0,     0,     0,     0,
+     0,     0,     0,   250,     0,     0,  1177,     0,     0,     0,
+     0,     0,     0,     0,   252,   253,  1178,     0,     0,     0,
+     0,     0,   255,   256,   257,     0,     0,     7,     8,  1179,
+    10,   437,   233,   234,     0,   235,    12,     0,     0,     0,
+     0,     0,     0,     0,     0,   260,     0,     0,     0,     0,
+     0,    15,   236,     0,     0,    16,     0,   239,     0,    17,
+     0,   240,   241,     0,   242,    19,   243,   244,     0,     0,
+   245,   246,   247,   248,   249,    21,     0,    22,     0,     0,
+     0,     0,     0,     0,     0,     0,   250,     0,     0,   251,
+     0,     0,     0,     0,     0,     0,     0,   252,   253,   254,
+     0,     0,     0,     0,     0,   255,   256,   257,     0,     0,
+     7,     8,   441,    10,   437,   233,   234,     0,   235,    12,
+     0,     0,     0,     0,     0,     0,     0,     0,   260,     0,
+     0,     0,     0,     0,    15,   236,   237,   238,    16,     0,
+   239,     0,    17,     0,   240,   241,     0,   242,    19,   243,
+   244,     0,     0,   245,   246,   247,   248,   249,    21,     0,
+    22,     0,     7,     8,   158,   159,   160,     0,     0,     0,
+     0,    12,     0,     0,     0,     0,     0,     7,     8,   151,
+    10,   152,     0,     0,     0,     0,    12,     0,   255,   256,
+   257,     0,     0,     0,    17,   258,     0,     0,     0,   259,
+    19,    15,     0,   510,     0,    16,     0,     0,     0,    17,
+    21,   260,    22,     0,     0,    19,     0,     0,     0,     0,
+     0,     0,     0,     0,   603,    21,     0,    22,     0,     0,
+   153,     0,     0,     0,   604,     0,     0,     0,     0,    24,
+     0,     0,    26,     0,   513,     0,     0,   605,   515,    25,
+     0,     7,     8,    92,    10,    11,     0,    26,   618,     0,
+    12,     0,    27,     0,     0,     0,     0,     0,   655,     8,
+   151,    10,   152,     0,     0,    15,     0,    12,     0,    16,
+     0,     0,     0,    17,     0,     0,     0,     0,     0,    19,
+     0,     0,    15,     0,     0,     0,    16,     0,     0,    21,
+    17,    22,     0,     0,     0,     0,    19,     0,     0,     0,
+     0,     0,     0,    24,     0,     0,    21,     0,    22,     0,
+     0,     0,     0,    25,     0,   658,     0,     0,     0,     0,
+    24,    26,     0,     0,     0,     0,    27,     0,     0,     0,
+    25,     7,     8,   151,    10,   152,     0,     0,    26,     0,
+    12,     0,     0,    27,     0,     0,     0,     0,     7,     8,
+   151,    10,   152,     0,     0,    15,     0,    12,     0,    16,
+     0,     0,     0,    17,     0,     0,     0,     0,     0,    19,
+     0,     0,    15,     0,     0,     0,    16,     0,     0,    21,
+    17,    22,     0,     0,  1099,     0,    19,     0,     0,     0,
+     0,     0,     8,    24,    10,   184,    21,     0,    22,     0,
+    12,     0,     0,    25,     0,     0,     0,     0,     0,     0,
+    24,    26,     0,     0,     0,    15,    27,     0,     0,    16,
+    25,     0,     0,    17,     0,     0,     0,     0,    26,     0,
+     0,     0,   510,    27,     0,     0,     0,     0,     0,    21,
+     0,    93,     0,     0,     0,     0,     0,     0,     0,     0,
+   466,   467,   468,   511,   469,   470,   471,   472,   473,   474,
+   475,   476,   477,   512,   479,   480,   481,   482,   483,   484,
+   485,   486,   487,   513,     0,     0,   514,   515,   466,   467,
+   468,     0,   469,   470,   471,   472,   473,   474,   475,   476,
+   477,   478,   479,   480,   481,   482,   483,   484,   485,   486,
+   487,   543,   682,   466,   467,   468,     0,   469,   470,   471,
+   472,   473,   474,   475,   476,   477,   478,   479,   480,   481,
+   482,   483,   484,   485,   486,   487,  1040,   466,   467,   468,
+     0,   469,   470,   471,   472,   473,   474,   475,   476,   477,
    478,   479,   480,   481,   482,   483,   484,   485,   486,   487,
-   488,   489,   490,   469,   470,   471,     0,   472,   473,   474,
+   466,   467,   468,  1204,   469,   470,   471,   472,   473,   474,
    475,   476,   477,   478,   479,   480,   481,   482,   483,   484,
-   485,   486,   487,   488,   489,   490,   469,   470,   471,     0,
-   472,   473,   474,   475,   476,   477,   478,   479,   480,     0,
-   482,   483,   484,   485,   486,   487,   488,   489,   490,   471,
-     0,   472,   473,   474,   475,   476,   477,   478,   479,   480,
-   481,   482,   483,   484,   485,   486,   487,   488,   489,   490,
+   485,   486,   487,   466,   467,   468,  1253,   469,   470,   471,
+   472,   473,   474,   475,   476,   477,   478,   479,   480,   481,
+   482,   483,   484,   485,   486,   487,   466,   467,   468,     0,
+   469,   470,   471,   472,   473,   474,   475,   476,   477,   478,
+   479,   480,   481,   482,   483,   484,   485,   486,   487,   468,
+     0,   469,   470,   471,   472,   473,   474,   475,   476,   477,
+   478,   479,   480,   481,   482,   483,   484,   485,   486,   487,
+   470,   471,   472,   473,   474,   475,   476,   477,   478,   479,
+   480,   481,   482,   483,   484,   485,   486,   487,   472,   473,
    474,   475,   476,   477,   478,   479,   480,   481,   482,   483,
-   484,   485,   486,   487,   488,   489,   490
+   484,   485,   486,   487,   473,   474,   475,   476,   477,   478,
+   479,   480,   481,   482,   483,   484,   485,   486,   487
 };
 
 static const short yycheck[] = {     4,
-     4,   118,   279,   137,   419,   349,   300,    12,   131,   132,
-     4,   285,   341,   300,    70,    20,    20,   108,   109,    24,
-    25,    12,    27,   392,   285,   266,    52,   300,    33,    33,
-   137,    87,    20,    71,   132,   130,   391,   137,   753,    44,
-   182,    46,    98,   162,   163,   155,   135,    52,  1161,   820,
-   993,  1189,  1052,     4,    59,     9,    56,    34,    34,     9,
-    44,    52,     9,     0,  1222,    70,    71,  1169,    51,     3,
-     4,    56,    77,    77,  1232,    60,   370,    60,     4,     0,
-    10,   410,    87,   370,     3,     4,    69,    44,   365,    77,
-    95,    96,    45,    98,    20,    36,   101,    97,    44,   104,
-   105,    62,    53,   108,   109,   110,   189,    33,    36,    10,
-    60,    95,    58,  1215,  1252,   120,   120,   122,   123,    53,
-     7,    48,    41,    10,    75,    55,   103,   103,     4,     4,
-    60,    88,   993,   137,    53,   140,   141,   142,   122,  1000,
-  1253,    75,    88,     1,  1302,   102,    12,  1285,   102,   518,
-  1150,    77,   102,    88,    55,   102,    75,    44,     7,    60,
-   302,   166,   103,    93,    83,   126,   443,     4,    55,    44,
-    55,    58,   102,    60,    88,   103,    51,    53,    53,   184,
-   184,   155,   143,    70,     4,    56,    52,     7,   959,   194,
-    65,     4,    93,   300,   120,   189,    54,   158,   287,    75,
-    75,    88,    89,    44,   919,    54,    93,    76,     3,    44,
-    85,    60,   186,    88,    89,   102,    53,     4,   103,    88,
-    89,  1334,  1335,   346,   347,   348,   231,   232,   155,   285,
-    99,    51,   103,    53,   272,   162,   163,   990,    75,   992,
-    53,   107,    51,    92,   344,    65,    56,    88,   346,   347,
-   345,     3,     4,    88,    89,    75,   339,   391,   184,   186,
-    69,   535,    75,   370,     3,     4,    53,   272,   137,    89,
-     4,   276,    44,   278,   279,   280,   395,   396,    69,    56,
-    44,   286,    92,    44,   391,     4,   396,    44,     7,   380,
-   381,   391,    44,   102,   252,   300,   300,   255,    44,    51,
-   258,    53,   286,   230,   423,    10,   264,    56,   663,   314,
-    66,  1172,   317,  1256,    53,   273,    88,   322,   401,    53,
-  1263,   326,   326,    44,    88,   654,   103,    88,    89,    85,
-    60,    88,    51,    51,    53,    55,    88,   460,   326,   439,
-  1055,   102,    88,    89,    56,   339,    65,   103,    55,    56,
-    55,    69,   279,    58,   103,    60,    75,   362,   363,   364,
-   365,   366,    56,     3,     4,   370,   370,    88,  1229,    55,
-   331,   376,   102,   378,  1317,   380,   381,   382,   362,    88,
-   364,   365,   102,   388,    44,   251,    54,   391,    93,   394,
-   259,   103,   397,   387,   150,  1256,   496,    60,   498,   499,
-   326,    41,  1263,     3,     4,   410,    69,   401,    56,   103,
-   517,   416,   417,    53,   419,   419,   102,   524,    51,   424,
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      9,    -1,    11,    12,    13,    -1,    15,    16,    17,    18,
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+    88,    -1,    -1,     1,    92,     3,     4,    -1,     6,     7,
+     8,     9,    -1,    11,    12,    -1,   104,    -1,    -1,    -1,
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     48,    49,    50,    51,    -1,    53,    54,    -1,    -1,    -1,
@@ -2835,20 +2829,20 @@
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+    88,    -1,    -1,     1,    92,     3,     4,    -1,     6,     7,
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     -1,    -1,    -1,    81,    82,    83,    -1,    -1,    -1,    -1,
@@ -2857,177 +2851,97 @@
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+    -1,    -1,    65,    -1,    -1,    -1,    -1,    -1,    -1,    -1,
+    73,    74,    75,    -1,    -1,    -1,    -1,    -1,    81,    82,
+    83,    -1,    85,    -1,    -1,    88,    89,    -1,    -1,    92,
+    93,     3,     4,    -1,     6,     7,     8,     9,    -1,    11,
+    12,   104,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,
     -1,    -1,    -1,    -1,    -1,    27,    28,    29,    30,    31,
     -1,    33,    -1,    35,    -1,    37,    38,    -1,    40,    41,
     42,    43,    44,    -1,    46,    47,    48,    49,    50,    51,
@@ -3038,27 +2952,27 @@
     -1,     6,     7,     8,     9,    -1,    11,    12,    -1,    -1,
     -1,    -1,   104,    -1,    -1,    -1,    -1,    -1,    -1,    -1,
     -1,    -1,    27,    28,    29,    30,    31,    -1,    33,    -1,
-    35,    -1,    37,    38,    -1,    40,    41,    42,    43,    -1,
+    35,    -1,    37,    38,    -1,    40,    41,    42,    43,    44,
     -1,    46,    47,    48,    49,    50,    51,    -1,    53,    -1,
     -1,    -1,    -1,    -1,    -1,    -1,    -1,    62,    -1,    -1,
-    65,    -1,    -1,    -1,    -1,    70,    -1,    -1,    73,    74,
+    65,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    73,    74,
     75,    -1,    -1,    -1,    -1,    -1,    81,    82,    83,    -1,
-    -1,    -1,    -1,    88,    -1,     3,     4,    92,     6,     7,
+    85,    -1,    -1,    88,    89,     3,     4,    -1,     6,     7,
      8,     9,    -1,    11,    12,    -1,    -1,    -1,    -1,   104,
     -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    27,
     28,    29,    30,    31,    -1,    33,    -1,    35,    -1,    37,
-    38,    -1,    40,    41,    42,    43,    -1,    -1,    46,    47,
-    48,    49,    50,    51,    -1,    53,    -1,    -1,    56,    -1,
+    38,    -1,    40,    41,    42,    43,    44,    -1,    46,    47,
+    48,    49,    50,    51,    -1,    53,    -1,    -1,    -1,    -1,
     -1,    -1,    -1,    -1,    62,    -1,    -1,    65,    -1,    -1,
     -1,    -1,    -1,    -1,    -1,    73,    74,    75,    -1,    -1,
-    -1,    -1,    -1,    81,    82,    83,    -1,    -1,    -1,    -1,
-    88,    -1,     3,     4,    92,     6,     7,     8,     9,    -1,
+    -1,    -1,    -1,    81,    82,    83,    -1,    85,    -1,    -1,
+    88,    89,     3,     4,    -1,     6,     7,     8,     9,    -1,
     11,    12,    -1,    -1,    -1,    -1,   104,    -1,    -1,    -1,
     -1,    -1,    -1,    -1,    -1,    -1,    27,    28,    29,    30,
     31,    -1,    33,    -1,    35,    -1,    37,    38,    -1,    40,
     41,    42,    43,    -1,    -1,    46,    47,    48,    49,    50,
     51,    -1,    53,    -1,    -1,    -1,    -1,    -1,    -1,    -1,
-    -1,    62,    -1,    -1,    65,    -1,    -1,    -1,    -1,    -1,
+    -1,    62,    -1,    -1,    65,    -1,    -1,    -1,    -1,    70,
     -1,    -1,    73,    74,    75,    -1,    -1,    -1,    -1,    -1,
     81,    82,    83,    -1,    -1,    -1,    -1,    88,    -1,     3,
      4,    92,     6,     7,     8,     9,    -1,    11,    12,    -1,
@@ -3066,24 +2980,7 @@
     -1,    -1,    -1,    27,    28,    29,    30,    31,    -1,    33,
     -1,    35,    -1,    37,    38,    -1,    40,    41,    42,    43,
     -1,    -1,    46,    47,    48,    49,    50,    51,    -1,    53,
-    54,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    62,    -1,
-    -1,    65,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    73,
-    74,    75,    -1,    -1,    -1,    -1,    -1,    81,    82,    83,
-    -1,    -1,     3,     4,    88,     6,     7,     8,     9,    -1,
-    11,    12,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,
-   104,    -1,    -1,    -1,    -1,    -1,    27,    28,    29,    30,
-    31,    -1,    33,    -1,    35,    -1,    37,    38,    -1,    40,
-    41,    42,    43,    -1,    -1,    46,    47,    48,    49,    50,
-    51,    -1,    53,    -1,    -1,    -1,    -1,    -1,    -1,    -1,
-    -1,    62,    -1,    -1,    65,    -1,    -1,    -1,    -1,    -1,
-    -1,    -1,    73,    74,    75,    -1,    -1,    -1,    -1,    -1,
-    81,    82,    83,    -1,    -1,    -1,    -1,    88,    89,     3,
-     4,    -1,     6,     7,     8,     9,    -1,    11,    12,    -1,
-    -1,    -1,    -1,   104,    -1,    -1,    -1,    -1,    -1,    -1,
-    -1,    -1,    -1,    27,    28,    29,    30,    31,    -1,    33,
-    -1,    35,    -1,    37,    38,    -1,    40,    41,    42,    43,
-    -1,    -1,    46,    47,    48,    49,    50,    51,    -1,    53,
-    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    62,    -1,
+    -1,    -1,    56,    -1,    -1,    -1,    -1,    -1,    62,    -1,
     -1,    65,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    73,
     74,    75,    -1,    -1,    -1,    -1,    -1,    81,    82,    83,
     -1,    -1,    -1,    -1,    88,    -1,     3,     4,    92,     6,
@@ -3100,6 +2997,23 @@
     -1,    -1,    -1,    -1,    -1,    -1,    -1,    27,    28,    29,
     30,    31,    -1,    33,    -1,    35,    -1,    37,    38,    -1,
     40,    41,    42,    43,    -1,    -1,    46,    47,    48,    49,
+    50,    51,    -1,    53,    54,    -1,    -1,    -1,    -1,    -1,
+    -1,    -1,    62,    -1,    -1,    65,    -1,    -1,    -1,    -1,
+    -1,    -1,    -1,    73,    74,    75,    -1,    -1,    -1,    -1,
+    -1,    81,    82,    83,    -1,    -1,     3,     4,    88,     6,
+     7,     8,     9,    -1,    11,    12,    -1,    -1,    -1,    -1,
+    -1,    -1,    -1,    -1,   104,    -1,    -1,    -1,    -1,    -1,
+    27,    28,    29,    30,    31,    -1,    33,    -1,    35,    -1,
+    37,    38,    -1,    40,    41,    42,    43,    -1,    -1,    46,
+    47,    48,    49,    50,    51,    -1,    53,    -1,    -1,    -1,
+    -1,    -1,    -1,    -1,    -1,    62,    -1,    -1,    65,    -1,
+    -1,    -1,    -1,    -1,    -1,    -1,    73,    74,    75,    -1,
+    -1,    -1,    -1,    -1,    81,    82,    83,    -1,    -1,    -1,
+    -1,    88,    89,     3,     4,    -1,     6,     7,     8,     9,
+    -1,    11,    12,    -1,    -1,    -1,    -1,   104,    -1,    -1,
+    -1,    -1,    -1,    -1,    -1,    -1,    -1,    27,    28,    29,
+    30,    31,    -1,    33,    -1,    35,    -1,    37,    38,    -1,
+    40,    41,    42,    43,    -1,    -1,    46,    47,    48,    49,
     50,    51,    -1,    53,    -1,    -1,    -1,    -1,    -1,    -1,
     -1,    -1,    62,    -1,    -1,    65,    -1,    -1,    -1,    -1,
     -1,    -1,    -1,    73,    74,    75,    -1,    -1,    -1,    -1,
@@ -3129,10 +3043,44 @@
     49,    50,    51,    -1,    53,    -1,    -1,    -1,    -1,    -1,
     -1,    -1,    -1,    62,    -1,    -1,    65,    -1,    -1,    -1,
     -1,    -1,    -1,    -1,    73,    74,    75,    -1,    -1,    -1,
+    -1,    -1,    81,    82,    83,    -1,    -1,    -1,    -1,    88,
+    -1,     3,     4,    92,     6,     7,     8,     9,    -1,    11,
+    12,    -1,    -1,    -1,    -1,   104,    -1,    -1,    -1,    -1,
+    -1,    -1,    -1,    -1,    -1,    27,    28,    29,    30,    31,
+    -1,    33,    -1,    35,    -1,    37,    38,    -1,    40,    41,
+    42,    43,    -1,    -1,    46,    47,    48,    49,    50,    51,
+    -1,    53,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,
+    62,    -1,    -1,    65,    -1,    -1,    -1,    -1,    -1,    -1,
+    -1,    73,    74,    75,    -1,    -1,    -1,    -1,    -1,    81,
+    82,    83,    -1,    -1,    -1,    -1,    88,    -1,     3,     4,
+    92,     6,     7,     8,     9,    -1,    11,    12,    -1,    -1,
+    -1,    -1,   104,    -1,    -1,    -1,    -1,    -1,    -1,    -1,
+    -1,    -1,    27,    28,    29,    30,    31,    -1,    33,    -1,
+    35,    -1,    37,    38,    -1,    40,    41,    42,    43,    -1,
+    -1,    46,    47,    48,    49,    50,    51,    -1,    53,    -1,
+    -1,    -1,    -1,    -1,    -1,    -1,    -1,    62,    -1,    -1,
+    65,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    73,    74,
+    75,    -1,    -1,    -1,    -1,    -1,    81,    82,    83,    -1,
+    -1,     3,     4,    88,     6,     7,     8,     9,    -1,    11,
+    12,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,   104,
+    -1,    -1,    -1,    -1,    -1,    27,    28,    29,    30,    31,
+    -1,    33,    -1,    35,    -1,    37,    38,    -1,    40,    41,
+    42,    43,    -1,    -1,    46,    47,    48,    49,    50,    51,
+    -1,    53,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,
+    62,    -1,    -1,    65,    -1,    -1,    -1,    -1,    -1,    -1,
+    -1,    73,    74,    75,    -1,    -1,    -1,    -1,    -1,    81,
+    82,    83,    -1,    -1,     3,     4,    88,     6,     7,     8,
+     9,    -1,    11,    12,    -1,    -1,    -1,    -1,    -1,    -1,
+    -1,    -1,   104,    -1,    -1,    -1,    -1,    -1,    27,    28,
+    29,    30,    31,    -1,    33,    -1,    35,    -1,    37,    38,
+    -1,    40,    41,    42,    43,    -1,    -1,    46,    47,    48,
+    49,    50,    51,    -1,    53,    -1,    -1,    -1,    -1,    -1,
+    -1,    -1,    -1,    62,    -1,    -1,    65,    -1,    -1,    -1,
+    -1,    -1,    -1,    -1,    73,    74,    75,    -1,    -1,    -1,
     -1,    -1,    81,    82,    83,    -1,    -1,     3,     4,    88,
      6,     7,     8,     9,    -1,    11,    12,    -1,    -1,    -1,
     -1,    -1,    -1,    -1,    -1,   104,    -1,    -1,    -1,    -1,
-    -1,    27,    28,    29,    30,    31,    -1,    33,    -1,    35,
+    -1,    27,    28,    -1,    -1,    31,    -1,    33,    -1,    35,
     -1,    37,    38,    -1,    40,    41,    42,    43,    -1,    -1,
     46,    47,    48,    49,    50,    51,    -1,    53,    -1,    -1,
     -1,    -1,    -1,    -1,    -1,    -1,    62,    -1,    -1,    65,
@@ -3143,43 +3091,60 @@
     -1,    -1,    -1,    -1,    27,    28,    29,    30,    31,    -1,
     33,    -1,    35,    -1,    37,    38,    -1,    40,    41,    42,
     43,    -1,    -1,    46,    47,    48,    49,    50,    51,    -1,
-    53,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    62,
-    -1,    -1,    65,    -1,    -1,    -1,    -1,    -1,    -1,    -1,
-    73,    74,    75,    -1,    -1,    -1,    -1,    -1,    81,    82,
-    83,    -1,    -1,     3,     4,    88,     6,     7,     8,     9,
-    -1,    11,    12,    -1,    -1,    -1,    -1,    -1,    -1,    -1,
-    -1,   104,    -1,    -1,    -1,    -1,    -1,    27,    28,    -1,
-    -1,    31,    -1,    33,    -1,    35,    -1,    37,    38,    -1,
-    40,    41,    42,    43,    -1,    -1,    46,    47,    48,    49,
-    50,    51,    -1,    53,    -1,    -1,    -1,    -1,    -1,    -1,
-    -1,    -1,    62,    -1,    -1,    65,    -1,    -1,    -1,    -1,
-    -1,    -1,    -1,    73,    74,    75,    -1,    -1,    -1,    -1,
-    -1,    81,    82,    83,    -1,    -1,     3,     4,    88,     6,
-     7,     8,     9,    -1,    11,    12,    -1,    -1,    -1,    -1,
-    -1,    -1,    -1,    -1,   104,    -1,    -1,    -1,    -1,    -1,
-    27,    28,    -1,    -1,    31,    -1,    33,    -1,    35,    -1,
-    37,    38,    -1,    40,    41,    42,    43,    -1,    -1,    46,
-    47,    48,    49,    50,    51,    -1,    53,    -1,    -1,    -1,
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-    73,    74,    75,    76,    77,    78,    79,    57,    58,    59,
-    60,    61,    62,    63,    64,    65,    66,    67,    68,    69,
+    53,    -1,     3,     4,     5,     6,     7,    -1,    -1,    -1,
+    -1,    12,    -1,    -1,    -1,    -1,    -1,     3,     4,     5,
+     6,     7,    -1,    -1,    -1,    -1,    12,    -1,    81,    82,
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+    41,    27,    -1,    44,    -1,    31,    -1,    -1,    -1,    35,
+    51,   104,    53,    -1,    -1,    41,    -1,    -1,    -1,    -1,
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+    56,    -1,    -1,    -1,    75,    -1,    -1,    -1,    -1,    65,
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+     5,     6,     7,    -1,    -1,    27,    -1,    12,    -1,    31,
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+    -1,    53,    -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,
+    57,    58,    59,    65,    61,    62,    63,    64,    65,    66,
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     70,    71,    72,    73,    74,    75,    76,    77,    78,    79,
     57,    58,    59,    60,    61,    62,    63,    64,    65,    66,
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-    61,    62,    63,    64,    65,    66,    67,    68,    69,    -1,
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     71,    72,    73,    74,    75,    76,    77,    78,    79,    59,
     -1,    61,    62,    63,    64,    65,    66,    67,    68,    69,
     70,    71,    72,    73,    74,    75,    76,    77,    78,    79,
-    63,    64,    65,    66,    67,    68,    69,    70,    71,    72,
-    73,    74,    75,    76,    77,    78,    79
+    62,    63,    64,    65,    66,    67,    68,    69,    70,    71,
+    72,    73,    74,    75,    76,    77,    78,    79,    64,    65,
+    66,    67,    68,    69,    70,    71,    72,    73,    74,    75,
+    76,    77,    78,    79,    65,    66,    67,    68,    69,    70,
+    71,    72,    73,    74,    75,    76,    77,    78,    79
 };
 /* -*-C-*-  Note some compilers choke on comments on `#line' lines.  */
 #line 3 "/usr/local/lib/bison.simple"
@@ -3364,23 +3329,8 @@
 #endif
 
 #line 184 "/usr/local/lib/bison.simple"
-
-/* The user can define YYPARSE_PARAM as the name of an argument to be passed
-   into yyparse.  The argument should have type void *.
-   It should actually point to an object.
-   Grammar actions can access the variable by casting it
-   to the proper pointer type.  */
-
-#ifdef YYPARSE_PARAM
-#define YYPARSE_PARAM_DECL void *YYPARSE_PARAM;
-#else
-#define YYPARSE_PARAM
-#define YYPARSE_PARAM_DECL
-#endif
-
 int
-yyparse(YYPARSE_PARAM)
-     YYPARSE_PARAM_DECL
+yyparse()
 {
   register int yystate;
   register int yyn;
@@ -4767,21 +4717,13 @@
 #line 1253 "parse.y"
 { yyval.ttype = build_parse_node (ADDR_EXPR, yyvsp[0].ttype); ;
     break;}
-case 228:
-#line 1255 "parse.y"
-{ yyval.ttype = yyvsp[-1].ttype; ;
-    break;}
-case 231:
-#line 1262 "parse.y"
+case 230:
+#line 1260 "parse.y"
 { push_nested_class (TREE_TYPE (OP0 (yyval.ttype)), 3);
 		  TREE_COMPLEXITY (yyval.ttype) = current_class_depth; ;
     break;}
-case 232:
-#line 1265 "parse.y"
-{ yyval.ttype = finish_decl_parsing (yyvsp[-1].ttype); ;
-    break;}
-case 233:
-#line 1270 "parse.y"
+case 231:
+#line 1266 "parse.y"
 {
 		  if (TREE_CODE (yyval.ttype) == BIT_NOT_EXPR)
 		    yyval.ttype = build_x_unary_op (BIT_NOT_EXPR, TREE_OPERAND (yyval.ttype, 0));
@@ -4801,20 +4743,20 @@
 		    yyval.ttype = do_identifier (yyval.ttype);
 		;
     break;}
-case 236:
-#line 1291 "parse.y"
+case 234:
+#line 1287 "parse.y"
 { yyval.ttype = combine_strings (yyval.ttype); ;
     break;}
-case 237:
-#line 1293 "parse.y"
+case 235:
+#line 1289 "parse.y"
 { yyval.ttype = yyvsp[-1].ttype; ;
     break;}
-case 238:
-#line 1295 "parse.y"
+case 236:
+#line 1291 "parse.y"
 { yyval.ttype = error_mark_node; ;
     break;}
-case 239:
-#line 1297 "parse.y"
+case 237:
+#line 1293 "parse.y"
 { if (current_function_decl == 0)
 		    {
 		      error ("braced-group within expression allowed only inside a function");
@@ -4823,8 +4765,8 @@
 		  keep_next_level ();
 		  yyval.ttype = expand_start_stmt_expr (); ;
     break;}
-case 240:
-#line 1305 "parse.y"
+case 238:
+#line 1301 "parse.y"
 { tree rtl_exp;
 		  if (flag_ansi)
 		    pedwarn ("ANSI C++ forbids braced-groups within expressions");
@@ -4846,16 +4788,16 @@
 		    yyval.ttype = yyvsp[-1].ttype;
 		;
     break;}
-case 241:
-#line 1326 "parse.y"
+case 239:
+#line 1322 "parse.y"
 { /* [eichin:19911016.1902EST] */
                   yyval.ttype = build_x_function_call (yyvsp[-3].ttype, yyvsp[-1].ttype, current_class_decl); 
                   /* here we instantiate_class_template as needed... */
                   do_pending_templates ();
                 ;
     break;}
-case 242:
-#line 1330 "parse.y"
+case 240:
+#line 1326 "parse.y"
 {
                   if (TREE_CODE (yyvsp[-1].ttype) == CALL_EXPR
                       && TREE_TYPE (yyvsp[-1].ttype) != void_type_node)
@@ -4864,8 +4806,8 @@
                     yyval.ttype = yyvsp[-1].ttype;
                 ;
     break;}
-case 243:
-#line 1338 "parse.y"
+case 241:
+#line 1334 "parse.y"
 {
 		  yyval.ttype = build_x_function_call (yyval.ttype, NULL_TREE, current_class_decl);
 		  if (TREE_CODE (yyval.ttype) == CALL_EXPR
@@ -4873,12 +4815,12 @@
 		    yyval.ttype = require_complete_type (yyval.ttype);
                 ;
     break;}
-case 244:
-#line 1345 "parse.y"
+case 242:
+#line 1341 "parse.y"
 { yyval.ttype = grok_array_decl (yyval.ttype, yyvsp[-1].ttype); ;
     break;}
-case 245:
-#line 1347 "parse.y"
+case 243:
+#line 1343 "parse.y"
 { /* If we get an OFFSET_REF, turn it into what it really
 		     means (e.g., a COMPONENT_REF).  This way if we've got,
 		     say, a reference to a static member that's being operated
@@ -4888,14 +4830,14 @@
 		    yyval.ttype = resolve_offset_ref (yyval.ttype);
 		  yyval.ttype = build_x_unary_op (POSTINCREMENT_EXPR, yyval.ttype); ;
     break;}
-case 246:
-#line 1356 "parse.y"
+case 244:
+#line 1352 "parse.y"
 { if (TREE_CODE (yyval.ttype) == OFFSET_REF)
 		    yyval.ttype = resolve_offset_ref (yyval.ttype);
 		  yyval.ttype = build_x_unary_op (POSTDECREMENT_EXPR, yyval.ttype); ;
     break;}
-case 247:
-#line 1361 "parse.y"
+case 245:
+#line 1357 "parse.y"
 { if (current_class_decl)
 		    {
 #ifdef WARNING_ABOUT_CCD
@@ -4919,8 +4861,8 @@
 		    }
 		;
     break;}
-case 248:
-#line 1384 "parse.y"
+case 246:
+#line 1380 "parse.y"
 {
 		  tree type;
 		  tree id = yyval.ttype;
@@ -4965,37 +4907,37 @@
 		    }
 		;
     break;}
-case 250:
-#line 1429 "parse.y"
+case 248:
+#line 1425 "parse.y"
 { tree type = groktypename (yyvsp[-4].ttype);
 		  yyval.ttype = build_dynamic_cast (type, yyvsp[-1].ttype); ;
     break;}
-case 251:
-#line 1432 "parse.y"
+case 249:
+#line 1428 "parse.y"
 { tree type = groktypename (yyvsp[-4].ttype);
 		  yyval.ttype = build_static_cast (type, yyvsp[-1].ttype); ;
     break;}
-case 252:
-#line 1435 "parse.y"
+case 250:
+#line 1431 "parse.y"
 { tree type = groktypename (yyvsp[-4].ttype);
 		  yyval.ttype = build_reinterpret_cast (type, yyvsp[-1].ttype); ;
     break;}
-case 253:
-#line 1438 "parse.y"
+case 251:
+#line 1434 "parse.y"
 { tree type = groktypename (yyvsp[-4].ttype);
 		  yyval.ttype = build_const_cast (type, yyvsp[-1].ttype); ;
     break;}
-case 254:
-#line 1441 "parse.y"
+case 252:
+#line 1437 "parse.y"
 { yyval.ttype = build_typeid (yyvsp[-1].ttype); ;
     break;}
-case 255:
-#line 1443 "parse.y"
+case 253:
+#line 1439 "parse.y"
 { tree type = groktypename (yyvsp[-1].ttype);
 		  yyval.ttype = get_typeid (type); ;
     break;}
-case 256:
-#line 1446 "parse.y"
+case 254:
+#line 1442 "parse.y"
 {
 		do_scoped_id:
 		  yyval.ttype = IDENTIFIER_GLOBAL_VALUE (yyvsp[0].ttype);
@@ -5035,8 +4977,8 @@
 
 		;
     break;}
-case 257:
-#line 1485 "parse.y"
+case 255:
+#line 1481 "parse.y"
 {
 		  got_scope = NULL_TREE;
 		  if (TREE_CODE (yyvsp[0].ttype) == IDENTIFIER_NODE)
@@ -5044,28 +4986,28 @@
 		  yyval.ttype = yyvsp[0].ttype;
 		;
     break;}
+case 256:
+#line 1488 "parse.y"
+{ yyval.ttype = build_offset_ref (OP0 (yyval.ttype), OP1 (yyval.ttype)); ;
+    break;}
+case 257:
+#line 1490 "parse.y"
+{ yyval.ttype = build_member_call (OP0 (yyval.ttype), OP1 (yyval.ttype), yyvsp[-1].ttype); ;
+    break;}
 case 258:
 #line 1492 "parse.y"
-{ yyval.ttype = build_offset_ref (OP0 (yyval.ttype), OP1 (yyval.ttype)); ;
+{ yyval.ttype = build_member_call (OP0 (yyval.ttype), OP1 (yyval.ttype), NULL_TREE); ;
     break;}
 case 259:
 #line 1494 "parse.y"
-{ yyval.ttype = build_member_call (OP0 (yyval.ttype), OP1 (yyval.ttype), yyvsp[-1].ttype); ;
+{ yyval.ttype = build_component_ref (yyval.ttype, yyvsp[0].ttype, NULL_TREE, 1); ;
     break;}
 case 260:
 #line 1496 "parse.y"
-{ yyval.ttype = build_member_call (OP0 (yyval.ttype), OP1 (yyval.ttype), NULL_TREE); ;
+{ yyval.ttype = build_object_ref (yyval.ttype, OP0 (yyvsp[0].ttype), OP1 (yyvsp[0].ttype)); ;
     break;}
 case 261:
 #line 1498 "parse.y"
-{ yyval.ttype = build_component_ref (yyval.ttype, yyvsp[0].ttype, NULL_TREE, 1); ;
-    break;}
-case 262:
-#line 1500 "parse.y"
-{ yyval.ttype = build_object_ref (yyval.ttype, OP0 (yyvsp[0].ttype), OP1 (yyvsp[0].ttype)); ;
-    break;}
-case 263:
-#line 1502 "parse.y"
 {
 #if 0
 		  /* This is a future direction of this code, but because
@@ -5081,8 +5023,8 @@
 #endif
 		;
     break;}
-case 264:
-#line 1517 "parse.y"
+case 262:
+#line 1513 "parse.y"
 {
 #if 0
 		  /* This is a future direction of this code, but because
@@ -5098,8 +5040,8 @@
 #endif
 		;
     break;}
-case 265:
-#line 1532 "parse.y"
+case 263:
+#line 1528 "parse.y"
 {
 		  if (IS_SIGNATURE (IDENTIFIER_TYPE_VALUE (OP0 (yyvsp[-3].ttype))))
 		    {
@@ -5111,8 +5053,8 @@
 		    yyval.ttype = build_scoped_method_call (yyval.ttype, OP0 (yyvsp[-3].ttype), OP1 (yyvsp[-3].ttype), yyvsp[-1].ttype);
 		;
     break;}
-case 266:
-#line 1543 "parse.y"
+case 264:
+#line 1539 "parse.y"
 {
 		  if (IS_SIGNATURE (IDENTIFIER_TYPE_VALUE (OP0 (yyvsp[-1].ttype))))
 		    {
@@ -5124,8 +5066,8 @@
 		    yyval.ttype = build_scoped_method_call (yyval.ttype, OP0 (yyvsp[-1].ttype), OP1 (yyvsp[-1].ttype), NULL_TREE);
 		;
     break;}
-case 267:
-#line 1555 "parse.y"
+case 265:
+#line 1551 "parse.y"
 { 
 		  if (TREE_CODE (TREE_TYPE (yyvsp[-3].ttype)) 
 		      != TREE_CODE (TREE_TYPE (IDENTIFIER_GLOBAL_VALUE (yyvsp[-1].ttype))))
@@ -5133,8 +5075,8 @@
 		  yyval.ttype = convert (void_type_node, yyvsp[-3].ttype);
 		;
     break;}
-case 268:
-#line 1562 "parse.y"
+case 266:
+#line 1558 "parse.y"
 { 
 		  if (yyvsp[-4].ttype != yyvsp[-1].ttype)
 		    cp_error ("destructor specifier `%T::~%T()' must have matching names", yyvsp[-4].ttype, yyvsp[-1].ttype);
@@ -5144,36 +5086,36 @@
 		  yyval.ttype = convert (void_type_node, yyvsp[-5].ttype);
 		;
     break;}
-case 269:
-#line 1611 "parse.y"
+case 267:
+#line 1607 "parse.y"
 { yyval.itype = 0; ;
     break;}
-case 270:
-#line 1613 "parse.y"
+case 268:
+#line 1609 "parse.y"
 { got_scope = NULL_TREE; yyval.itype = 1; ;
     break;}
-case 271:
-#line 1617 "parse.y"
+case 269:
+#line 1613 "parse.y"
 { yyval.itype = 0; ;
     break;}
-case 272:
-#line 1619 "parse.y"
+case 270:
+#line 1615 "parse.y"
 { got_scope = NULL_TREE; yyval.itype = 1; ;
     break;}
-case 273:
-#line 1624 "parse.y"
+case 271:
+#line 1620 "parse.y"
 { yyval.ttype = true_node; ;
     break;}
-case 274:
-#line 1626 "parse.y"
+case 272:
+#line 1622 "parse.y"
 { yyval.ttype = false_node; ;
     break;}
-case 276:
-#line 1633 "parse.y"
+case 274:
+#line 1629 "parse.y"
 { yyval.ttype = chainon (yyval.ttype, yyvsp[0].ttype); ;
     break;}
-case 277:
-#line 1638 "parse.y"
+case 275:
+#line 1634 "parse.y"
 {
 		  if (! current_function_parms_stored)
 		    store_parm_decls ();
@@ -5184,14 +5126,14 @@
 		  keep_next_level ();
 		;
     break;}
-case 279:
-#line 1651 "parse.y"
+case 277:
+#line 1647 "parse.y"
 {
 		  yyval.ttype = build_x_arrow (yyval.ttype);
 		;
     break;}
-case 280:
-#line 1659 "parse.y"
+case 278:
+#line 1655 "parse.y"
 { tree d = get_decl_list (yyvsp[-2].ttype);
 		  int yes = suspend_momentary ();
 		  d = start_decl (yyvsp[-1].ttype, d, 0, NULL_TREE);
@@ -5201,8 +5143,8 @@
 		    note_got_semicolon (yyvsp[-2].ttype);
 		;
     break;}
-case 281:
-#line 1668 "parse.y"
+case 279:
+#line 1664 "parse.y"
 { tree d = yyvsp[-2].ttype;
 		  int yes = suspend_momentary ();
 		  d = start_decl (yyvsp[-1].ttype, d, 0, NULL_TREE);
@@ -5211,164 +5153,164 @@
 		  note_list_got_semicolon (yyvsp[-2].ttype);
 		;
     break;}
-case 282:
-#line 1676 "parse.y"
+case 280:
+#line 1672 "parse.y"
 {
 		  resume_momentary (yyvsp[-1].itype);
 		  if (IS_AGGR_TYPE_CODE (TREE_CODE (yyvsp[-2].ttype)))
 		    note_got_semicolon (yyvsp[-2].ttype);
 		;
     break;}
-case 283:
-#line 1682 "parse.y"
+case 281:
+#line 1678 "parse.y"
 {
 		  resume_momentary (yyvsp[-1].itype);
 		  note_list_got_semicolon (yyvsp[-2].ttype);
 		;
     break;}
-case 284:
-#line 1687 "parse.y"
+case 282:
+#line 1683 "parse.y"
 { resume_momentary (yyvsp[-1].itype); ;
     break;}
-case 285:
-#line 1689 "parse.y"
+case 283:
+#line 1685 "parse.y"
 {
 		  shadow_tag (yyvsp[-1].ttype);
 		  note_list_got_semicolon (yyvsp[-1].ttype);
 		;
     break;}
-case 286:
-#line 1694 "parse.y"
+case 284:
+#line 1690 "parse.y"
 { warning ("empty declaration"); ;
     break;}
-case 289:
-#line 1708 "parse.y"
+case 287:
+#line 1704 "parse.y"
 { yyval.ttype = build_parse_node (CALL_EXPR, NULL_TREE, empty_parms (),
 					 NULL_TREE); ;
     break;}
-case 290:
-#line 1711 "parse.y"
+case 288:
+#line 1707 "parse.y"
 { yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, empty_parms (), 
 					 NULL_TREE); ;
     break;}
+case 289:
+#line 1714 "parse.y"
+{ yyval.ttype = build_decl_list (yyval.ttype, yyvsp[0].ttype); ;
+    break;}
+case 290:
+#line 1716 "parse.y"
+{ yyval.ttype = build_decl_list (yyval.ttype, yyvsp[0].ttype); ;
+    break;}
 case 291:
 #line 1718 "parse.y"
-{ yyval.ttype = build_decl_list (yyval.ttype, yyvsp[0].ttype); ;
+{ yyval.ttype = build_decl_list (get_decl_list (yyval.ttype), yyvsp[0].ttype); ;
     break;}
 case 292:
 #line 1720 "parse.y"
-{ yyval.ttype = build_decl_list (yyval.ttype, yyvsp[0].ttype); ;
+{ yyval.ttype = build_decl_list (yyval.ttype, NULL_TREE); ;
     break;}
 case 293:
 #line 1722 "parse.y"
-{ yyval.ttype = build_decl_list (get_decl_list (yyval.ttype), yyvsp[0].ttype); ;
-    break;}
-case 294:
-#line 1724 "parse.y"
 { yyval.ttype = build_decl_list (yyval.ttype, NULL_TREE); ;
     break;}
-case 295:
-#line 1726 "parse.y"
-{ yyval.ttype = build_decl_list (yyval.ttype, NULL_TREE); ;
+case 296:
+#line 1735 "parse.y"
+{ yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype); ;
+    break;}
+case 297:
+#line 1737 "parse.y"
+{ yyval.ttype = decl_tree_cons (NULL_TREE, yyval.ttype, yyvsp[0].ttype); ;
     break;}
 case 298:
 #line 1739 "parse.y"
-{ yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype); ;
+{ yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[-1].ttype, chainon (yyvsp[0].ttype, yyval.ttype)); ;
     break;}
 case 299:
 #line 1741 "parse.y"
-{ yyval.ttype = decl_tree_cons (NULL_TREE, yyval.ttype, yyvsp[0].ttype); ;
+{ yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[-1].ttype, chainon (yyvsp[0].ttype, yyval.ttype)); ;
     break;}
 case 300:
 #line 1743 "parse.y"
-{ yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[-1].ttype, chainon (yyvsp[0].ttype, yyval.ttype)); ;
-    break;}
-case 301:
-#line 1745 "parse.y"
-{ yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[-1].ttype, chainon (yyvsp[0].ttype, yyval.ttype)); ;
-    break;}
-case 302:
-#line 1747 "parse.y"
 { yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[-2].ttype, 
 				       chainon (yyvsp[-1].ttype, chainon (yyvsp[0].ttype, yyval.ttype))); ;
     break;}
-case 303:
-#line 1753 "parse.y"
+case 301:
+#line 1749 "parse.y"
 { if (extra_warnings)
 		    warning ("`%s' is not at beginning of declaration",
 			     IDENTIFIER_POINTER (yyval.ttype));
 		  yyval.ttype = build_decl_list (NULL_TREE, yyval.ttype); ;
     break;}
-case 304:
-#line 1758 "parse.y"
+case 302:
+#line 1754 "parse.y"
 { yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype); ;
     break;}
-case 305:
-#line 1760 "parse.y"
+case 303:
+#line 1756 "parse.y"
 { if (extra_warnings)
 		    warning ("`%s' is not at beginning of declaration",
 			     IDENTIFIER_POINTER (yyvsp[0].ttype));
 		  yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype); ;
     break;}
-case 306:
-#line 1772 "parse.y"
+case 304:
+#line 1768 "parse.y"
 { TREE_STATIC (yyval.ttype) = 1; ;
     break;}
-case 307:
-#line 1774 "parse.y"
+case 305:
+#line 1770 "parse.y"
 { yyval.ttype = IDENTIFIER_AS_LIST (yyval.ttype); ;
     break;}
-case 308:
-#line 1776 "parse.y"
+case 306:
+#line 1772 "parse.y"
 { yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype);
 		  TREE_STATIC (yyval.ttype) = 1; ;
     break;}
-case 309:
-#line 1779 "parse.y"
+case 307:
+#line 1775 "parse.y"
 { if (extra_warnings && TREE_STATIC (yyval.ttype))
 		    warning ("`%s' is not at beginning of declaration",
 			     IDENTIFIER_POINTER (yyvsp[0].ttype));
 		  yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype);
 		  TREE_STATIC (yyval.ttype) = TREE_STATIC (yyvsp[-1].ttype); ;
     break;}
-case 310:
-#line 1795 "parse.y"
+case 308:
+#line 1791 "parse.y"
 { yyval.ttype = get_decl_list (yyval.ttype); ;
     break;}
-case 311:
-#line 1797 "parse.y"
+case 309:
+#line 1793 "parse.y"
 { yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype); ;
     break;}
-case 312:
-#line 1799 "parse.y"
+case 310:
+#line 1795 "parse.y"
 { yyval.ttype = decl_tree_cons (NULL_TREE, yyval.ttype, yyvsp[0].ttype); ;
     break;}
-case 313:
-#line 1801 "parse.y"
+case 311:
+#line 1797 "parse.y"
 { yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[-1].ttype, chainon (yyvsp[0].ttype, yyval.ttype)); ;
     break;}
-case 314:
-#line 1806 "parse.y"
+case 312:
+#line 1802 "parse.y"
 { yyval.ttype = build_decl_list (NULL_TREE, yyval.ttype); ;
     break;}
-case 315:
-#line 1808 "parse.y"
+case 313:
+#line 1804 "parse.y"
 { yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype); ;
     break;}
-case 319:
-#line 1819 "parse.y"
+case 317:
+#line 1815 "parse.y"
 { yyval.ttype = TREE_TYPE (yyvsp[-1].ttype);
 		  if (flag_ansi)
 		    pedwarn ("ANSI C++ forbids `typeof'"); ;
     break;}
-case 320:
-#line 1823 "parse.y"
+case 318:
+#line 1819 "parse.y"
 { yyval.ttype = groktypename (yyvsp[-1].ttype);
 		  if (flag_ansi)
 		    pedwarn ("ANSI C++ forbids `typeof'"); ;
     break;}
-case 321:
-#line 1827 "parse.y"
+case 319:
+#line 1823 "parse.y"
 { tree type = TREE_TYPE (yyvsp[-1].ttype);
 
 		  if (IS_AGGR_TYPE (type))
@@ -5383,8 +5325,8 @@
 		    }
 		;
     break;}
-case 322:
-#line 1841 "parse.y"
+case 320:
+#line 1837 "parse.y"
 { tree type = groktypename (yyvsp[-1].ttype);
 
 		  if (IS_AGGR_TYPE (type))
@@ -5399,16 +5341,16 @@
 		    }
 		;
     break;}
-case 332:
-#line 1880 "parse.y"
+case 330:
+#line 1876 "parse.y"
 { yyval.ttype = NULL_TREE; ;
     break;}
-case 333:
-#line 1882 "parse.y"
+case 331:
+#line 1878 "parse.y"
 { if (TREE_CHAIN (yyvsp[-1].ttype)) yyvsp[-1].ttype = combine_strings (yyvsp[-1].ttype); yyval.ttype = yyvsp[-1].ttype; ;
     break;}
-case 334:
-#line 1887 "parse.y"
+case 332:
+#line 1883 "parse.y"
 { current_declspecs = yyvsp[-5].ttype;
 		  if (TREE_CODE (current_declspecs) != TREE_LIST)
 		    current_declspecs = get_decl_list (current_declspecs);
@@ -5423,13 +5365,13 @@
 		  yyval.ttype = start_decl (yyvsp[-4].ttype, current_declspecs, 1, yyvsp[-3].ttype);
 		  cplus_decl_attributes (yyval.ttype, yyvsp[-1].ttype); ;
     break;}
-case 335:
-#line 1902 "parse.y"
+case 333:
+#line 1898 "parse.y"
 { finish_decl (yyvsp[-1].ttype, yyvsp[0].ttype, yyvsp[-4].ttype, 0);
 		  yyval.itype = yyvsp[-2].itype; ;
     break;}
-case 336:
-#line 1905 "parse.y"
+case 334:
+#line 1901 "parse.y"
 { tree d;
 		  current_declspecs = yyvsp[-4].ttype;
 		  if (TREE_CODE (current_declspecs) != TREE_LIST)
@@ -5446,35 +5388,35 @@
 		  cplus_decl_attributes (d, yyvsp[0].ttype);
 		  finish_decl (d, NULL_TREE, yyvsp[-1].ttype, 0); ;
     break;}
-case 337:
-#line 1924 "parse.y"
+case 335:
+#line 1920 "parse.y"
 { yyval.ttype = start_decl (yyvsp[-4].ttype, current_declspecs, 1, yyvsp[-3].ttype);
 		  cplus_decl_attributes (yyval.ttype, yyvsp[-1].ttype); ;
     break;}
-case 338:
-#line 1928 "parse.y"
+case 336:
+#line 1924 "parse.y"
 { finish_decl (yyvsp[-1].ttype, yyvsp[0].ttype, yyvsp[-4].ttype, 0); ;
     break;}
-case 339:
-#line 1930 "parse.y"
+case 337:
+#line 1926 "parse.y"
 { yyval.ttype = start_decl (yyvsp[-3].ttype, current_declspecs, 0, yyvsp[-2].ttype);
 		  cplus_decl_attributes (yyval.ttype, yyvsp[0].ttype);
 		  finish_decl (yyval.ttype, NULL_TREE, yyvsp[-1].ttype, 0); ;
     break;}
-case 340:
-#line 1937 "parse.y"
+case 338:
+#line 1933 "parse.y"
 { current_declspecs = yyvsp[-5].ttype;
 		  yyvsp[0].itype = suspend_momentary ();
 		  yyval.ttype = start_decl (yyvsp[-4].ttype, current_declspecs, 1, yyvsp[-3].ttype);
 		  cplus_decl_attributes (yyval.ttype, yyvsp[-1].ttype); ;
     break;}
-case 341:
-#line 1943 "parse.y"
+case 339:
+#line 1939 "parse.y"
 { finish_decl (yyvsp[-1].ttype, yyvsp[0].ttype, yyvsp[-4].ttype, 0);
 		  yyval.itype = yyvsp[-2].itype; ;
     break;}
-case 342:
-#line 1946 "parse.y"
+case 340:
+#line 1942 "parse.y"
 { tree d;
 		  current_declspecs = yyvsp[-4].ttype;
 		  yyval.itype = suspend_momentary ();
@@ -5482,20 +5424,20 @@
 		  cplus_decl_attributes (d, yyvsp[0].ttype);
 		  finish_decl (d, NULL_TREE, yyvsp[-1].ttype, 0); ;
     break;}
-case 343:
-#line 1956 "parse.y"
+case 341:
+#line 1952 "parse.y"
 { current_declspecs = NULL_TREE;
 		  yyvsp[0].itype = suspend_momentary ();
 		  yyval.ttype = start_decl (yyvsp[-4].ttype, current_declspecs, 1, yyvsp[-3].ttype);
 		  cplus_decl_attributes (yyval.ttype, yyvsp[-1].ttype); ;
     break;}
-case 344:
-#line 1962 "parse.y"
+case 342:
+#line 1958 "parse.y"
 { finish_decl (yyvsp[-1].ttype, yyvsp[0].ttype, yyvsp[-4].ttype, 0);
 		  yyval.itype = yyvsp[-2].itype; ;
     break;}
-case 345:
-#line 1965 "parse.y"
+case 343:
+#line 1961 "parse.y"
 { tree d;
 		  current_declspecs = NULL_TREE;
 		  yyval.itype = suspend_momentary ();
@@ -5503,147 +5445,147 @@
 		  cplus_decl_attributes (d, yyvsp[0].ttype);
 		  finish_decl (d, NULL_TREE, yyvsp[-1].ttype, 0); ;
     break;}
-case 346:
-#line 1977 "parse.y"
+case 344:
+#line 1973 "parse.y"
 { yyval.ttype = NULL_TREE; ;
     break;}
-case 347:
-#line 1979 "parse.y"
+case 345:
+#line 1975 "parse.y"
 { yyval.ttype = yyvsp[0].ttype; ;
     break;}
-case 348:
-#line 1984 "parse.y"
+case 346:
+#line 1980 "parse.y"
 { yyval.ttype = yyvsp[0].ttype; ;
     break;}
-case 349:
-#line 1986 "parse.y"
+case 347:
+#line 1982 "parse.y"
 { yyval.ttype = chainon (yyvsp[-1].ttype, yyvsp[0].ttype); ;
     break;}
-case 350:
-#line 1991 "parse.y"
+case 348:
+#line 1987 "parse.y"
 { yyval.ttype = yyvsp[-2].ttype; ;
     break;}
-case 351:
-#line 1996 "parse.y"
+case 349:
+#line 1992 "parse.y"
 { yyval.ttype = build_tree_list (NULL_TREE, yyvsp[0].ttype); ;
     break;}
-case 352:
-#line 1998 "parse.y"
+case 350:
+#line 1994 "parse.y"
 { yyval.ttype = chainon (yyvsp[-2].ttype, build_tree_list (NULL_TREE, yyvsp[0].ttype)); ;
     break;}
-case 353:
-#line 2003 "parse.y"
+case 351:
+#line 1999 "parse.y"
 { yyval.ttype = NULL_TREE; ;
     break;}
-case 354:
-#line 2005 "parse.y"
+case 352:
+#line 2001 "parse.y"
 { yyval.ttype = yyvsp[0].ttype; ;
     break;}
-case 355:
-#line 2007 "parse.y"
+case 353:
+#line 2003 "parse.y"
 { yyval.ttype = tree_cons (yyvsp[-3].ttype, NULL_TREE, build_tree_list (NULL_TREE, yyvsp[-1].ttype)); ;
     break;}
-case 356:
-#line 2009 "parse.y"
+case 354:
+#line 2005 "parse.y"
 { yyval.ttype = tree_cons (yyvsp[-5].ttype, NULL_TREE, tree_cons (NULL_TREE, yyvsp[-3].ttype, yyvsp[-1].ttype)); ;
     break;}
-case 357:
-#line 2011 "parse.y"
+case 355:
+#line 2007 "parse.y"
 { yyval.ttype = tree_cons (yyvsp[-3].ttype, NULL_TREE, yyvsp[-1].ttype); ;
     break;}
-case 362:
-#line 2027 "parse.y"
+case 360:
+#line 2023 "parse.y"
 { yyval.ttype = build_tree_list (NULL_TREE, yyvsp[0].ttype); ;
     break;}
-case 363:
-#line 2029 "parse.y"
+case 361:
+#line 2025 "parse.y"
 { yyval.ttype = chainon (yyvsp[-2].ttype, build_tree_list (NULL_TREE, yyvsp[0].ttype)); ;
     break;}
-case 365:
-#line 2035 "parse.y"
+case 363:
+#line 2031 "parse.y"
 { yyval.ttype = build_nt (CONSTRUCTOR, NULL_TREE, NULL_TREE);
 		  TREE_HAS_CONSTRUCTOR (yyval.ttype) = 1; ;
     break;}
-case 366:
-#line 2038 "parse.y"
+case 364:
+#line 2034 "parse.y"
 { yyval.ttype = build_nt (CONSTRUCTOR, NULL_TREE, nreverse (yyvsp[-1].ttype));
 		  TREE_HAS_CONSTRUCTOR (yyval.ttype) = 1; ;
     break;}
-case 367:
-#line 2041 "parse.y"
+case 365:
+#line 2037 "parse.y"
 { yyval.ttype = build_nt (CONSTRUCTOR, NULL_TREE, nreverse (yyvsp[-2].ttype));
 		  TREE_HAS_CONSTRUCTOR (yyval.ttype) = 1; ;
     break;}
-case 368:
-#line 2044 "parse.y"
+case 366:
+#line 2040 "parse.y"
 { yyval.ttype = NULL_TREE; ;
     break;}
-case 369:
-#line 2051 "parse.y"
+case 367:
+#line 2047 "parse.y"
 { yyval.ttype = build_tree_list (NULL_TREE, yyval.ttype); ;
     break;}
-case 370:
-#line 2053 "parse.y"
+case 368:
+#line 2049 "parse.y"
 { yyval.ttype = tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype); ;
     break;}
-case 371:
-#line 2056 "parse.y"
+case 369:
+#line 2052 "parse.y"
 { yyval.ttype = build_tree_list (yyvsp[-2].ttype, yyvsp[0].ttype); ;
     break;}
-case 372:
-#line 2058 "parse.y"
+case 370:
+#line 2054 "parse.y"
 { yyval.ttype = tree_cons (yyvsp[-2].ttype, yyvsp[0].ttype, yyval.ttype); ;
     break;}
-case 373:
-#line 2060 "parse.y"
+case 371:
+#line 2056 "parse.y"
 { yyval.ttype = build_tree_list (yyval.ttype, yyvsp[0].ttype); ;
     break;}
-case 374:
-#line 2062 "parse.y"
+case 372:
+#line 2058 "parse.y"
 { yyval.ttype = tree_cons (yyvsp[-2].ttype, yyvsp[0].ttype, yyval.ttype); ;
     break;}
-case 375:
-#line 2067 "parse.y"
+case 373:
+#line 2063 "parse.y"
 { yyvsp[0].itype = suspend_momentary ();
 		  yyval.ttype = start_enum (yyvsp[-1].ttype); ;
     break;}
-case 376:
-#line 2070 "parse.y"
+case 374:
+#line 2066 "parse.y"
 { yyval.ttype = finish_enum (yyvsp[-3].ttype, yyvsp[-2].ttype);
 		  resume_momentary ((int) yyvsp[-4].itype);
 		  check_for_missing_semicolon (yyvsp[-3].ttype); ;
     break;}
-case 377:
-#line 2074 "parse.y"
+case 375:
+#line 2070 "parse.y"
 { yyval.ttype = finish_enum (start_enum (yyvsp[-2].ttype), NULL_TREE);
 		  check_for_missing_semicolon (yyval.ttype); ;
     break;}
-case 378:
-#line 2077 "parse.y"
+case 376:
+#line 2073 "parse.y"
 { yyvsp[0].itype = suspend_momentary ();
 		  yyval.ttype = start_enum (make_anon_name ()); ;
     break;}
-case 379:
-#line 2080 "parse.y"
+case 377:
+#line 2076 "parse.y"
 { yyval.ttype = finish_enum (yyvsp[-3].ttype, yyvsp[-2].ttype);
 		  resume_momentary ((int) yyvsp[-5].itype);
 		  check_for_missing_semicolon (yyvsp[-3].ttype); ;
     break;}
-case 380:
-#line 2084 "parse.y"
+case 378:
+#line 2080 "parse.y"
 { yyval.ttype = finish_enum (start_enum (make_anon_name()), NULL_TREE);
 		  check_for_missing_semicolon (yyval.ttype); ;
     break;}
-case 381:
-#line 2087 "parse.y"
+case 379:
+#line 2083 "parse.y"
 { yyval.ttype = xref_tag (enum_type_node, yyvsp[0].ttype, NULL_TREE, 0); ;
     break;}
-case 382:
-#line 2089 "parse.y"
+case 380:
+#line 2085 "parse.y"
 { yyval.ttype = xref_tag (enum_type_node, yyvsp[0].ttype, NULL_TREE, 0); ;
     break;}
-case 383:
-#line 2093 "parse.y"
+case 381:
+#line 2089 "parse.y"
 {
 		  int semi;
 		  tree id;
@@ -5695,8 +5637,8 @@
 		  if (! semi)
 		    check_for_missing_semicolon (yyval.ttype); ;
     break;}
-case 384:
-#line 2144 "parse.y"
+case 382:
+#line 2140 "parse.y"
 {
 #if 0
   /* It's no longer clear what the following error is supposed to
@@ -5710,72 +5652,72 @@
 #endif
 		;
     break;}
-case 388:
-#line 2166 "parse.y"
+case 386:
+#line 2162 "parse.y"
 { if (pedantic) pedwarn ("comma at end of enumerator list"); ;
     break;}
-case 390:
-#line 2171 "parse.y"
+case 388:
+#line 2167 "parse.y"
 { error ("storage class specifier `%s' not allowed after struct or class", IDENTIFIER_POINTER (yyvsp[0].ttype)); ;
     break;}
-case 391:
-#line 2173 "parse.y"
+case 389:
+#line 2169 "parse.y"
 { error ("type specifier `%s' not allowed after struct or class", IDENTIFIER_POINTER (yyvsp[0].ttype)); ;
     break;}
-case 392:
-#line 2175 "parse.y"
+case 390:
+#line 2171 "parse.y"
 { error ("type qualifier `%s' not allowed after struct or class", IDENTIFIER_POINTER (yyvsp[0].ttype)); ;
     break;}
-case 393:
-#line 2177 "parse.y"
+case 391:
+#line 2173 "parse.y"
 { error ("no body nor ';' separates two class, struct or union declarations"); ;
     break;}
-case 394:
-#line 2182 "parse.y"
+case 392:
+#line 2178 "parse.y"
 { 
 		  yyungetc (';', 1); current_aggr = yyval.ttype; yyval.ttype = yyvsp[-1].ttype; 
 		  if (yyvsp[-3].ttype == ridpointers[(int) RID_TEMPLATE])
 		    instantiate_class_template (yyval.ttype, 2);
 		;
     break;}
-case 395:
-#line 2191 "parse.y"
+case 393:
+#line 2187 "parse.y"
 { current_aggr = yyval.ttype; yyval.ttype = yyvsp[0].ttype; ;
     break;}
-case 396:
-#line 2193 "parse.y"
+case 394:
+#line 2189 "parse.y"
 { current_aggr = yyval.ttype; yyval.ttype = yyvsp[0].ttype; ;
     break;}
-case 397:
-#line 2195 "parse.y"
+case 395:
+#line 2191 "parse.y"
 { current_aggr = yyval.ttype; yyval.ttype = yyvsp[0].ttype; ;
     break;}
-case 398:
-#line 2197 "parse.y"
+case 396:
+#line 2193 "parse.y"
 { yyungetc ('{', 1);
 		aggr2:
 		  current_aggr = yyval.ttype;
 		  yyval.ttype = yyvsp[-1].ttype;
 		  overload_template_name (yyval.ttype, 0); ;
     break;}
-case 399:
-#line 2203 "parse.y"
+case 397:
+#line 2199 "parse.y"
 { yyungetc (':', 1); goto aggr2; ;
     break;}
-case 401:
-#line 2209 "parse.y"
+case 399:
+#line 2205 "parse.y"
 { current_aggr = yyval.ttype; yyval.ttype = yyvsp[0].ttype; ;
     break;}
-case 402:
-#line 2213 "parse.y"
+case 400:
+#line 2209 "parse.y"
 { yyval.ttype = xref_tag (current_aggr, yyvsp[0].ttype, NULL_TREE, 1); ;
     break;}
-case 403:
-#line 2216 "parse.y"
+case 401:
+#line 2212 "parse.y"
 { yyval.ttype = xref_defn_tag (current_aggr, yyvsp[0].ttype, NULL_TREE); ;
     break;}
-case 404:
-#line 2221 "parse.y"
+case 402:
+#line 2217 "parse.y"
 {
 		  if (yyvsp[0].ttype)
 		    yyval.ttype = xref_tag (current_aggr, yyvsp[-2].ttype, yyvsp[0].ttype, 1);
@@ -5783,8 +5725,8 @@
 		    yyval.ttype = yyvsp[-1].ttype;
 		;
     break;}
-case 405:
-#line 2230 "parse.y"
+case 403:
+#line 2226 "parse.y"
 {
 		  if (yyvsp[0].ttype)
 		    yyval.ttype = xref_defn_tag (current_aggr, yyvsp[-2].ttype, yyvsp[0].ttype);
@@ -5792,29 +5734,29 @@
 		    yyval.ttype = yyvsp[-1].ttype;
 		;
     break;}
-case 406:
-#line 2239 "parse.y"
+case 404:
+#line 2235 "parse.y"
 { yyval.ttype = xref_tag (yyval.ttype, make_anon_name (), NULL_TREE, 0);
 		  yyungetc ('{', 1); ;
     break;}
-case 409:
-#line 2247 "parse.y"
+case 407:
+#line 2243 "parse.y"
 { yyval.ttype = NULL_TREE; ;
     break;}
-case 410:
-#line 2249 "parse.y"
+case 408:
+#line 2245 "parse.y"
 { yyungetc(':', 1); yyval.ttype = NULL_TREE; ;
     break;}
-case 411:
-#line 2251 "parse.y"
+case 409:
+#line 2247 "parse.y"
 { yyval.ttype = yyvsp[0].ttype; ;
     break;}
-case 413:
-#line 2257 "parse.y"
+case 411:
+#line 2253 "parse.y"
 { yyval.ttype = chainon (yyval.ttype, yyvsp[0].ttype); ;
     break;}
-case 414:
-#line 2262 "parse.y"
+case 412:
+#line 2258 "parse.y"
 {
 		  tree type;
 		 do_base_class1:
@@ -5842,8 +5784,8 @@
 		    yyval.ttype = build_tree_list ((tree)access_default, yyval.ttype);
 		;
     break;}
-case 415:
-#line 2289 "parse.y"
+case 413:
+#line 2285 "parse.y"
 {
 		  tree type;
 		 do_base_class2:
@@ -5873,8 +5815,8 @@
 		    yyval.ttype = build_tree_list ((tree) yyval.ttype, yyvsp[0].ttype);
 		;
     break;}
-case 417:
-#line 2322 "parse.y"
+case 415:
+#line 2318 "parse.y"
 {
 		  if (current_aggr == signature_type_node)
 		    {
@@ -5897,8 +5839,8 @@
 		    }
 		;
     break;}
-case 418:
-#line 2344 "parse.y"
+case 416:
+#line 2340 "parse.y"
 {
 		  if (current_aggr == signature_type_node)
 		    {
@@ -5921,14 +5863,14 @@
 		    }
 		;
     break;}
-case 420:
-#line 2370 "parse.y"
+case 418:
+#line 2366 "parse.y"
 { if (yyval.ttype != ridpointers[(int)RID_VIRTUAL])
 		    sorry ("non-virtual access");
 		  yyval.itype = access_default_virtual; ;
     break;}
-case 421:
-#line 2374 "parse.y"
+case 419:
+#line 2370 "parse.y"
 { int err = 0;
 		  if (yyvsp[0].itype == access_protected)
 		    {
@@ -5955,8 +5897,8 @@
 		    }
 		;
     break;}
-case 422:
-#line 2400 "parse.y"
+case 420:
+#line 2396 "parse.y"
 { if (yyvsp[0].ttype != ridpointers[(int)RID_VIRTUAL])
 		    sorry ("non-virtual access");
 		  if (yyval.itype == access_public)
@@ -5964,8 +5906,8 @@
 		  else if (yyval.itype == access_private)
 		    yyval.itype = access_private_virtual; ;
     break;}
-case 423:
-#line 2409 "parse.y"
+case 421:
+#line 2405 "parse.y"
 { tree t = yyvsp[-1].ttype;
 		  push_obstacks_nochange ();
 		  end_temporary_allocation ();
@@ -6026,12 +5968,12 @@
 #endif
 		;
     break;}
-case 424:
-#line 2472 "parse.y"
+case 422:
+#line 2468 "parse.y"
 { yyval.ttype = NULL_TREE; ;
     break;}
-case 425:
-#line 2474 "parse.y"
+case 423:
+#line 2470 "parse.y"
 {
 		  if (current_aggr == signature_type_node)
 		    yyval.ttype = build_tree_list ((tree) access_public, yyval.ttype);
@@ -6039,8 +5981,8 @@
 		    yyval.ttype = build_tree_list ((tree) access_default, yyval.ttype);
 		;
     break;}
-case 426:
-#line 2481 "parse.y"
+case 424:
+#line 2477 "parse.y"
 {
 		  tree visspec = (tree) yyvsp[-2].itype;
 
@@ -6052,20 +5994,20 @@
 		  yyval.ttype = chainon (yyval.ttype, build_tree_list (visspec, yyvsp[0].ttype));
 		;
     break;}
-case 427:
-#line 2492 "parse.y"
+case 425:
+#line 2488 "parse.y"
 {
 		  if (current_aggr == signature_type_node)
 		    error ("access specifier not allowed in signature");
 		;
     break;}
-case 428:
-#line 2502 "parse.y"
+case 426:
+#line 2498 "parse.y"
 { if (yyval.ttype == void_type_node) yyval.ttype = NULL_TREE; 
 		;
     break;}
-case 429:
-#line 2505 "parse.y"
+case 427:
+#line 2501 "parse.y"
 { /* In pushdecl, we created a reverse list of names
 		     in this binding level.  Make sure that the chain
 		     of what we're trying to add isn't the item itself
@@ -6079,64 +6021,64 @@
 		    }
 		;
     break;}
-case 432:
-#line 2523 "parse.y"
+case 430:
+#line 2519 "parse.y"
 { error ("missing ';' before right brace");
 		  yyungetc ('}', 0); ;
     break;}
-case 433:
-#line 2528 "parse.y"
+case 431:
+#line 2524 "parse.y"
 { yyval.ttype = finish_method (yyval.ttype); ;
     break;}
-case 434:
-#line 2530 "parse.y"
+case 432:
+#line 2526 "parse.y"
 { yyval.ttype = finish_method (yyval.ttype); ;
     break;}
-case 435:
-#line 2538 "parse.y"
+case 433:
+#line 2534 "parse.y"
 {
 		  yyval.ttype = grok_x_components (yyval.ttype, yyvsp[0].ttype);
 		;
     break;}
-case 436:
-#line 2542 "parse.y"
+case 434:
+#line 2538 "parse.y"
 { 
 		  yyval.ttype = grok_x_components (yyval.ttype, yyvsp[0].ttype);
 		;
     break;}
-case 437:
-#line 2546 "parse.y"
+case 435:
+#line 2542 "parse.y"
 { yyval.ttype = grokfield (yyval.ttype, NULL_TREE, yyvsp[-2].ttype, NULL_TREE, yyvsp[-1].ttype);
 		  cplus_decl_attributes (yyval.ttype, yyvsp[0].ttype); ;
     break;}
-case 438:
-#line 2549 "parse.y"
+case 436:
+#line 2545 "parse.y"
 { yyval.ttype = grokbitfield (NULL_TREE, NULL_TREE, yyvsp[0].ttype); ;
     break;}
-case 439:
-#line 2551 "parse.y"
+case 437:
+#line 2547 "parse.y"
 { yyval.ttype = NULL_TREE; ;
     break;}
-case 440:
-#line 2562 "parse.y"
+case 438:
+#line 2558 "parse.y"
 { yyval.ttype = build_parse_node (CALL_EXPR, TREE_VALUE (yyvsp[-4].ttype),
 					 yyvsp[-2].ttype, yyvsp[0].ttype);
 		  yyval.ttype = grokfield (yyval.ttype, TREE_CHAIN (yyvsp[-4].ttype), NULL_TREE, NULL_TREE,
 				  NULL_TREE); ;
     break;}
-case 441:
-#line 2567 "parse.y"
+case 439:
+#line 2563 "parse.y"
 { yyval.ttype = build_parse_node (CALL_EXPR, TREE_VALUE (yyvsp[-2].ttype),
 					 empty_parms (), yyvsp[0].ttype);
 		  yyval.ttype = grokfield (yyval.ttype, TREE_CHAIN (yyvsp[-2].ttype), NULL_TREE, NULL_TREE,
 				  NULL_TREE); ;
     break;}
-case 442:
-#line 2576 "parse.y"
+case 440:
+#line 2572 "parse.y"
 { yyval.ttype = NULL_TREE; ;
     break;}
-case 444:
-#line 2579 "parse.y"
+case 442:
+#line 2575 "parse.y"
 {
 		  /* In this context, void_type_node encodes
 		     friends.  They have been recorded elsewhere.  */
@@ -6146,12 +6088,12 @@
 		    yyval.ttype = chainon (yyval.ttype, yyvsp[0].ttype);
 		;
     break;}
-case 445:
-#line 2591 "parse.y"
+case 443:
+#line 2587 "parse.y"
 { yyval.ttype = NULL_TREE; ;
     break;}
-case 447:
-#line 2594 "parse.y"
+case 445:
+#line 2590 "parse.y"
 {
 		  /* In this context, void_type_node encodes
 		     friends.  They have been recorded elsewhere.  */
@@ -6161,105 +6103,105 @@
 		    yyval.ttype = chainon (yyval.ttype, yyvsp[0].ttype);
 		;
     break;}
-case 452:
-#line 2616 "parse.y"
+case 450:
+#line 2612 "parse.y"
 { current_declspecs = yyvsp[-4].ttype;
 		  yyval.ttype = grokfield (yyval.ttype, current_declspecs, yyvsp[-2].ttype, NULL_TREE, yyvsp[-1].ttype);
 		  cplus_decl_attributes (yyval.ttype, yyvsp[0].ttype); ;
     break;}
-case 453:
-#line 2620 "parse.y"
+case 451:
+#line 2616 "parse.y"
 { current_declspecs = yyvsp[-6].ttype;
 		  yyval.ttype = grokfield (yyval.ttype, current_declspecs, yyvsp[-4].ttype, yyvsp[0].ttype, yyvsp[-3].ttype);
 		  cplus_decl_attributes (yyval.ttype, yyvsp[-2].ttype); ;
     break;}
-case 454:
-#line 2624 "parse.y"
+case 452:
+#line 2620 "parse.y"
 { current_declspecs = yyvsp[-4].ttype;
 		  yyval.ttype = grokbitfield (yyval.ttype, current_declspecs, yyvsp[-1].ttype);
 		  cplus_decl_attributes (yyval.ttype, yyvsp[0].ttype); ;
     break;}
-case 455:
-#line 2631 "parse.y"
+case 453:
+#line 2627 "parse.y"
 { current_declspecs = yyvsp[-4].ttype;
 		  yyval.ttype = grokfield (yyval.ttype, current_declspecs, yyvsp[-2].ttype, NULL_TREE, yyvsp[-1].ttype);
 		  cplus_decl_attributes (yyval.ttype, yyvsp[0].ttype); ;
     break;}
-case 456:
-#line 2635 "parse.y"
+case 454:
+#line 2631 "parse.y"
 { current_declspecs = yyvsp[-6].ttype;
 		  yyval.ttype = grokfield (yyval.ttype, current_declspecs, yyvsp[-4].ttype, yyvsp[0].ttype, yyvsp[-3].ttype);
 		  cplus_decl_attributes (yyval.ttype, yyvsp[-2].ttype); ;
     break;}
-case 457:
-#line 2639 "parse.y"
+case 455:
+#line 2635 "parse.y"
 { current_declspecs = yyvsp[-4].ttype;
 		  yyval.ttype = grokbitfield (yyval.ttype, current_declspecs, yyvsp[-1].ttype);
 		  cplus_decl_attributes (yyval.ttype, yyvsp[0].ttype); ;
     break;}
-case 458:
-#line 2643 "parse.y"
+case 456:
+#line 2639 "parse.y"
 { current_declspecs = yyvsp[-3].ttype;
 		  yyval.ttype = grokbitfield (NULL_TREE, current_declspecs, yyvsp[-1].ttype);
 		  cplus_decl_attributes (yyval.ttype, yyvsp[0].ttype); ;
     break;}
-case 459:
-#line 2650 "parse.y"
+case 457:
+#line 2646 "parse.y"
 { yyval.ttype = grokfield (yyval.ttype, current_declspecs, yyvsp[-2].ttype, NULL_TREE, yyvsp[-1].ttype);
 		  cplus_decl_attributes (yyval.ttype, yyvsp[0].ttype); ;
     break;}
-case 460:
-#line 2653 "parse.y"
+case 458:
+#line 2649 "parse.y"
 { yyval.ttype = grokfield (yyval.ttype, current_declspecs, yyvsp[-4].ttype, yyvsp[0].ttype, yyvsp[-3].ttype);
 		  cplus_decl_attributes (yyval.ttype, yyvsp[-2].ttype); ;
     break;}
-case 461:
-#line 2656 "parse.y"
+case 459:
+#line 2652 "parse.y"
 { yyval.ttype = grokbitfield (yyval.ttype, current_declspecs, yyvsp[-1].ttype);
 		  cplus_decl_attributes (yyval.ttype, yyvsp[0].ttype); ;
     break;}
-case 462:
-#line 2662 "parse.y"
+case 460:
+#line 2658 "parse.y"
 { yyval.ttype = grokfield (yyval.ttype, current_declspecs, yyvsp[-2].ttype, NULL_TREE, yyvsp[-1].ttype);
 		  cplus_decl_attributes (yyval.ttype, yyvsp[0].ttype); ;
     break;}
-case 463:
-#line 2665 "parse.y"
+case 461:
+#line 2661 "parse.y"
 { yyval.ttype = grokfield (yyval.ttype, current_declspecs, yyvsp[-4].ttype, yyvsp[0].ttype, yyvsp[-3].ttype);
 		  cplus_decl_attributes (yyval.ttype, yyvsp[-2].ttype); ;
     break;}
-case 464:
-#line 2668 "parse.y"
+case 462:
+#line 2664 "parse.y"
 { yyval.ttype = grokbitfield (yyval.ttype, current_declspecs, yyvsp[-1].ttype);
 		  cplus_decl_attributes (yyval.ttype, yyvsp[0].ttype); ;
     break;}
-case 465:
-#line 2671 "parse.y"
+case 463:
+#line 2667 "parse.y"
 { yyval.ttype = grokbitfield (NULL_TREE, current_declspecs, yyvsp[-1].ttype);
 		  cplus_decl_attributes (yyval.ttype, yyvsp[0].ttype); ;
     break;}
-case 467:
-#line 2682 "parse.y"
+case 465:
+#line 2678 "parse.y"
 { TREE_CHAIN (yyvsp[0].ttype) = yyval.ttype; yyval.ttype = yyvsp[0].ttype; ;
     break;}
-case 468:
-#line 2687 "parse.y"
+case 466:
+#line 2683 "parse.y"
 { yyval.ttype = build_enumerator (yyval.ttype, NULL_TREE); ;
     break;}
-case 469:
-#line 2689 "parse.y"
+case 467:
+#line 2685 "parse.y"
 { yyval.ttype = build_enumerator (yyval.ttype, yyvsp[0].ttype); ;
     break;}
-case 470:
-#line 2695 "parse.y"
+case 468:
+#line 2691 "parse.y"
 { yyval.ttype = build_decl_list (yyval.ttype, yyvsp[0].ttype); ;
     break;}
-case 471:
-#line 2697 "parse.y"
+case 469:
+#line 2693 "parse.y"
 { yyval.ttype = build_decl_list (yyval.ttype, NULL_TREE); ;
     break;}
-case 472:
-#line 2701 "parse.y"
+case 470:
+#line 2697 "parse.y"
 {
 		  if (flag_ansi)
 		    pedwarn ("ANSI C++ forbids array dimensions with parenthesized type in new");
@@ -6267,54 +6209,54 @@
 		  yyval.ttype = build_decl_list (TREE_PURPOSE (yyvsp[-4].ttype), yyval.ttype);
 		;
     break;}
-case 473:
-#line 2711 "parse.y"
+case 471:
+#line 2707 "parse.y"
 { yyval.ttype = NULL_TREE; ;
     break;}
+case 472:
+#line 2709 "parse.y"
+{ yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype); ;
+    break;}
+case 473:
+#line 2714 "parse.y"
+{ yyval.ttype = IDENTIFIER_AS_LIST (yyval.ttype); ;
+    break;}
 case 474:
-#line 2713 "parse.y"
+#line 2716 "parse.y"
 { yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype); ;
     break;}
 case 475:
-#line 2718 "parse.y"
-{ yyval.ttype = IDENTIFIER_AS_LIST (yyval.ttype); ;
+#line 2724 "parse.y"
+{ yyval.itype = suspend_momentary (); ;
     break;}
 case 476:
-#line 2720 "parse.y"
-{ yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype); ;
+#line 2725 "parse.y"
+{ resume_momentary ((int) yyvsp[-1].itype); yyval.ttype = yyvsp[0].ttype; ;
     break;}
 case 477:
-#line 2728 "parse.y"
-{ yyval.itype = suspend_momentary (); ;
+#line 2732 "parse.y"
+{ yyval.ttype = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ;
     break;}
 case 478:
-#line 2729 "parse.y"
-{ resume_momentary ((int) yyvsp[-1].itype); yyval.ttype = yyvsp[0].ttype; ;
+#line 2734 "parse.y"
+{ yyval.ttype = make_reference_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ;
     break;}
 case 479:
 #line 2736 "parse.y"
-{ yyval.ttype = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ;
+{ yyval.ttype = make_pointer_declarator (NULL_TREE, yyvsp[0].ttype); ;
     break;}
 case 480:
 #line 2738 "parse.y"
-{ yyval.ttype = make_reference_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ;
+{ yyval.ttype = make_reference_declarator (NULL_TREE, yyvsp[0].ttype); ;
     break;}
 case 481:
 #line 2740 "parse.y"
-{ yyval.ttype = make_pointer_declarator (NULL_TREE, yyvsp[0].ttype); ;
-    break;}
-case 482:
-#line 2742 "parse.y"
-{ yyval.ttype = make_reference_declarator (NULL_TREE, yyvsp[0].ttype); ;
-    break;}
-case 483:
-#line 2744 "parse.y"
 { tree arg = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype);
 		  yyval.ttype = build_parse_node (SCOPE_REF, yyvsp[-2].ttype, arg);
 		;
     break;}
-case 485:
-#line 2752 "parse.y"
+case 483:
+#line 2748 "parse.y"
 {
 		  /* Remember that this name has been used in the class
 		     definition, as per [class.scope0] */
@@ -6328,277 +6270,285 @@
 		    }
 		;
     break;}
-case 487:
-#line 2769 "parse.y"
+case 485:
+#line 2765 "parse.y"
 { yyval.ttype = yyvsp[0].ttype; ;
     break;}
+case 486:
+#line 2770 "parse.y"
+{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, yyvsp[-2].ttype, yyvsp[0].ttype); ;
+    break;}
+case 487:
+#line 2772 "parse.y"
+{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, yyvsp[-2].ttype, yyvsp[0].ttype); ;
+    break;}
 case 488:
 #line 2774 "parse.y"
-{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, yyvsp[-2].ttype, yyvsp[0].ttype); ;
+{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, empty_parms (), yyvsp[0].ttype); ;
     break;}
 case 489:
 #line 2776 "parse.y"
-{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, yyvsp[-2].ttype, yyvsp[0].ttype); ;
+{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, NULL_TREE, NULL_TREE); ;
     break;}
 case 490:
 #line 2778 "parse.y"
-{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, empty_parms (), yyvsp[0].ttype); ;
+{ yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, yyvsp[-1].ttype); ;
     break;}
 case 491:
 #line 2780 "parse.y"
-{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, NULL_TREE, NULL_TREE); ;
+{ yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, NULL_TREE); ;
     break;}
 case 492:
 #line 2782 "parse.y"
-{ yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, yyvsp[-1].ttype); ;
+{ yyval.ttype = yyvsp[-1].ttype; ;
     break;}
 case 493:
 #line 2784 "parse.y"
-{ yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, NULL_TREE); ;
-    break;}
-case 494:
-#line 2786 "parse.y"
-{ yyval.ttype = yyvsp[-1].ttype; ;
-    break;}
-case 495:
-#line 2788 "parse.y"
 { push_nested_class (TREE_TYPE (yyval.ttype), 3);
 		  yyval.ttype = build_parse_node (SCOPE_REF, yyval.ttype, yyvsp[0].ttype);
 		  TREE_COMPLEXITY (yyval.ttype) = current_class_depth; ;
     break;}
-case 497:
-#line 2799 "parse.y"
+case 495:
+#line 2795 "parse.y"
 { yyval.ttype = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ;
     break;}
-case 498:
-#line 2801 "parse.y"
+case 496:
+#line 2797 "parse.y"
 { yyval.ttype = make_reference_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ;
     break;}
-case 499:
-#line 2803 "parse.y"
+case 497:
+#line 2799 "parse.y"
 { yyval.ttype = make_pointer_declarator (NULL_TREE, yyvsp[0].ttype); ;
     break;}
-case 500:
-#line 2805 "parse.y"
+case 498:
+#line 2801 "parse.y"
 { yyval.ttype = make_reference_declarator (NULL_TREE, yyvsp[0].ttype); ;
     break;}
-case 501:
-#line 2807 "parse.y"
+case 499:
+#line 2803 "parse.y"
 { tree arg = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype);
 		  yyval.ttype = build_parse_node (SCOPE_REF, yyvsp[-2].ttype, arg);
 		;
     break;}
-case 503:
-#line 2815 "parse.y"
+case 501:
+#line 2811 "parse.y"
 { yyval.ttype = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ;
     break;}
-case 504:
-#line 2817 "parse.y"
+case 502:
+#line 2813 "parse.y"
 { yyval.ttype = make_reference_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ;
     break;}
-case 505:
-#line 2819 "parse.y"
+case 503:
+#line 2815 "parse.y"
 { yyval.ttype = make_pointer_declarator (NULL_TREE, yyvsp[0].ttype); ;
     break;}
-case 506:
-#line 2821 "parse.y"
+case 504:
+#line 2817 "parse.y"
 { yyval.ttype = make_reference_declarator (NULL_TREE, yyvsp[0].ttype); ;
     break;}
-case 507:
-#line 2823 "parse.y"
+case 505:
+#line 2819 "parse.y"
 { tree arg = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype);
 		  yyval.ttype = build_parse_node (SCOPE_REF, yyvsp[-2].ttype, arg);
 		;
     break;}
+case 507:
+#line 2827 "parse.y"
+{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, yyvsp[-2].ttype, yyvsp[0].ttype); ;
+    break;}
+case 508:
+#line 2829 "parse.y"
+{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, yyvsp[-2].ttype, yyvsp[0].ttype); ;
+    break;}
 case 509:
 #line 2831 "parse.y"
-{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, yyvsp[-2].ttype, yyvsp[0].ttype); ;
+{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, empty_parms (), yyvsp[0].ttype); ;
     break;}
 case 510:
 #line 2833 "parse.y"
-{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, yyvsp[-2].ttype, yyvsp[0].ttype); ;
+{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, NULL_TREE, NULL_TREE); ;
     break;}
 case 511:
 #line 2835 "parse.y"
-{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, empty_parms (), yyvsp[0].ttype); ;
+{ yyval.ttype = finish_decl_parsing (yyvsp[-1].ttype); ;
     break;}
 case 512:
 #line 2837 "parse.y"
-{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, NULL_TREE, NULL_TREE); ;
+{ yyval.ttype = yyvsp[-1].ttype; ;
     break;}
 case 513:
 #line 2839 "parse.y"
-{ yyval.ttype = yyvsp[-1].ttype; ;
+{ yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, yyvsp[-1].ttype); ;
     break;}
 case 514:
 #line 2841 "parse.y"
-{ yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, yyvsp[-1].ttype); ;
-    break;}
-case 515:
-#line 2843 "parse.y"
 { yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, NULL_TREE); ;
     break;}
-case 516:
-#line 2848 "parse.y"
+case 515:
+#line 2846 "parse.y"
 { got_scope = NULL_TREE;
 		  yyval.ttype = build_parse_node (SCOPE_REF, yyval.ttype, yyvsp[0].ttype); ;
     break;}
-case 517:
-#line 2854 "parse.y"
+case 516:
+#line 2852 "parse.y"
 { got_scope = NULL_TREE;
 		  yyval.ttype = build_parse_node (SCOPE_REF, yyval.ttype, yyvsp[0].ttype); ;
     break;}
-case 519:
-#line 2861 "parse.y"
+case 518:
+#line 2859 "parse.y"
 { yyval.ttype = yyvsp[0].ttype; ;
     break;}
+case 519:
+#line 2864 "parse.y"
+{ yyval.ttype = build_functional_cast (yyval.ttype, yyvsp[-1].ttype); ;
+    break;}
 case 520:
 #line 2866 "parse.y"
-{ yyval.ttype = build_functional_cast (yyval.ttype, yyvsp[-1].ttype); ;
+{ yyval.ttype = reparse_decl_as_expr (yyval.ttype, yyvsp[-1].ttype); ;
     break;}
 case 521:
 #line 2868 "parse.y"
-{ yyval.ttype = reparse_decl_as_expr (yyval.ttype, yyvsp[-1].ttype); ;
-    break;}
-case 522:
-#line 2870 "parse.y"
 { yyval.ttype = reparse_absdcl_as_expr (yyval.ttype, yyvsp[0].ttype); ;
     break;}
-case 526:
-#line 2881 "parse.y"
+case 525:
+#line 2879 "parse.y"
 { yyval.ttype = yyvsp[0].ttype; ;
     break;}
+case 526:
+#line 2886 "parse.y"
+{ got_scope = TREE_TYPE (yyval.ttype); ;
+    break;}
 case 527:
 #line 2888 "parse.y"
 { got_scope = TREE_TYPE (yyval.ttype); ;
     break;}
-case 528:
-#line 2890 "parse.y"
-{ got_scope = TREE_TYPE (yyval.ttype); ;
+case 529:
+#line 2904 "parse.y"
+{ yyval.ttype = yyvsp[0].ttype; ;
     break;}
-case 530:
-#line 2906 "parse.y"
+case 531:
+#line 2910 "parse.y"
 { yyval.ttype = yyvsp[0].ttype; ;
     break;}
 case 532:
-#line 2912 "parse.y"
-{ yyval.ttype = yyvsp[0].ttype; ;
+#line 2915 "parse.y"
+{ got_scope = NULL_TREE; ;
     break;}
 case 533:
 #line 2917 "parse.y"
-{ got_scope = NULL_TREE; ;
+{ yyval.ttype = yyvsp[-1].ttype; got_scope = NULL_TREE; ;
     break;}
 case 534:
-#line 2919 "parse.y"
-{ yyval.ttype = yyvsp[-1].ttype; got_scope = NULL_TREE; ;
+#line 2924 "parse.y"
+{ got_scope = void_type_node; ;
     break;}
 case 535:
-#line 2926 "parse.y"
-{ got_scope = void_type_node; ;
+#line 2930 "parse.y"
+{ yyval.ttype = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ;
     break;}
 case 536:
 #line 2932 "parse.y"
-{ yyval.ttype = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ;
+{ yyval.ttype = make_pointer_declarator (yyvsp[0].ttype, NULL_TREE); ;
     break;}
 case 537:
 #line 2934 "parse.y"
-{ yyval.ttype = make_pointer_declarator (yyvsp[0].ttype, NULL_TREE); ;
+{ yyval.ttype = make_reference_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ;
     break;}
 case 538:
 #line 2936 "parse.y"
-{ yyval.ttype = make_reference_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ;
+{ yyval.ttype = make_reference_declarator (yyvsp[0].ttype, NULL_TREE); ;
     break;}
 case 539:
 #line 2938 "parse.y"
-{ yyval.ttype = make_reference_declarator (yyvsp[0].ttype, NULL_TREE); ;
-    break;}
-case 540:
-#line 2940 "parse.y"
 { tree arg = make_pointer_declarator (yyvsp[0].ttype, NULL_TREE);
 		  yyval.ttype = build_parse_node (SCOPE_REF, yyvsp[-1].ttype, arg);
 		;
     break;}
-case 541:
-#line 2944 "parse.y"
+case 540:
+#line 2942 "parse.y"
 { tree arg = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype);
 		  yyval.ttype = build_parse_node (SCOPE_REF, yyvsp[-2].ttype, arg);
 		;
     break;}
+case 542:
+#line 2951 "parse.y"
+{ yyval.ttype = build_parse_node (ARRAY_REF, NULL_TREE, yyvsp[-1].ttype); ;
+    break;}
 case 543:
 #line 2953 "parse.y"
-{ yyval.ttype = build_parse_node (ARRAY_REF, NULL_TREE, yyvsp[-1].ttype); ;
+{ yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, yyvsp[-1].ttype); ;
     break;}
 case 544:
-#line 2955 "parse.y"
-{ yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, yyvsp[-1].ttype); ;
+#line 2959 "parse.y"
+{ yyval.ttype = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ;
     break;}
 case 545:
 #line 2961 "parse.y"
-{ yyval.ttype = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ;
+{ yyval.ttype = make_pointer_declarator (NULL_TREE, yyvsp[0].ttype); ;
     break;}
 case 546:
 #line 2963 "parse.y"
-{ yyval.ttype = make_pointer_declarator (NULL_TREE, yyvsp[0].ttype); ;
+{ yyval.ttype = make_pointer_declarator (yyvsp[0].ttype, NULL_TREE); ;
     break;}
 case 547:
 #line 2965 "parse.y"
-{ yyval.ttype = make_pointer_declarator (yyvsp[0].ttype, NULL_TREE); ;
+{ yyval.ttype = make_pointer_declarator (NULL_TREE, NULL_TREE); ;
     break;}
 case 548:
 #line 2967 "parse.y"
-{ yyval.ttype = make_pointer_declarator (NULL_TREE, NULL_TREE); ;
+{ yyval.ttype = make_reference_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ;
     break;}
 case 549:
 #line 2969 "parse.y"
-{ yyval.ttype = make_reference_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ;
+{ yyval.ttype = make_reference_declarator (NULL_TREE, yyvsp[0].ttype); ;
     break;}
 case 550:
 #line 2971 "parse.y"
-{ yyval.ttype = make_reference_declarator (NULL_TREE, yyvsp[0].ttype); ;
+{ yyval.ttype = make_reference_declarator (yyvsp[0].ttype, NULL_TREE); ;
     break;}
 case 551:
 #line 2973 "parse.y"
-{ yyval.ttype = make_reference_declarator (yyvsp[0].ttype, NULL_TREE); ;
+{ yyval.ttype = make_reference_declarator (NULL_TREE, NULL_TREE); ;
     break;}
 case 552:
 #line 2975 "parse.y"
-{ yyval.ttype = make_reference_declarator (NULL_TREE, NULL_TREE); ;
-    break;}
-case 553:
-#line 2977 "parse.y"
 { tree arg = make_pointer_declarator (yyvsp[0].ttype, NULL_TREE);
 		  yyval.ttype = build_parse_node (SCOPE_REF, yyvsp[-1].ttype, arg);
 		;
     break;}
-case 554:
-#line 2981 "parse.y"
+case 553:
+#line 2979 "parse.y"
 { tree arg = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype);
 		  yyval.ttype = build_parse_node (SCOPE_REF, yyvsp[-2].ttype, arg);
 		;
     break;}
-case 556:
-#line 2990 "parse.y"
+case 555:
+#line 2988 "parse.y"
 { yyval.ttype = yyvsp[-1].ttype; ;
     break;}
+case 557:
+#line 2992 "parse.y"
+{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, yyvsp[-2].ttype, yyvsp[0].ttype); ;
+    break;}
 case 558:
 #line 2994 "parse.y"
-{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, yyvsp[-2].ttype, yyvsp[0].ttype); ;
+{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, empty_parms (), yyvsp[0].ttype); ;
     break;}
 case 559:
 #line 2996 "parse.y"
-{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, empty_parms (), yyvsp[0].ttype); ;
+{ yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, yyvsp[-1].ttype); ;
     break;}
 case 560:
 #line 2998 "parse.y"
-{ yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, yyvsp[-1].ttype); ;
+{ yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, NULL_TREE); ;
     break;}
 case 561:
 #line 3000 "parse.y"
-{ yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, NULL_TREE); ;
+{ yyval.ttype = build_parse_node (CALL_EXPR, NULL_TREE, yyvsp[-2].ttype, yyvsp[0].ttype); ;
     break;}
 case 562:
 #line 3002 "parse.y"
-{ yyval.ttype = build_parse_node (CALL_EXPR, NULL_TREE, yyvsp[-2].ttype, yyvsp[0].ttype); ;
+{ TREE_OPERAND (yyval.ttype, 2) = yyvsp[0].ttype; ;
     break;}
 case 563:
 #line 3004 "parse.y"
@@ -6606,31 +6556,27 @@
     break;}
 case 564:
 #line 3006 "parse.y"
-{ TREE_OPERAND (yyval.ttype, 2) = yyvsp[0].ttype; ;
+{ yyval.ttype = build_parse_node (ARRAY_REF, NULL_TREE, yyvsp[-1].ttype); ;
     break;}
 case 565:
 #line 3008 "parse.y"
-{ yyval.ttype = build_parse_node (ARRAY_REF, NULL_TREE, yyvsp[-1].ttype); ;
-    break;}
-case 566:
-#line 3010 "parse.y"
 { yyval.ttype = build_parse_node (ARRAY_REF, NULL_TREE, NULL_TREE); ;
     break;}
-case 572:
-#line 3032 "parse.y"
+case 571:
+#line 3030 "parse.y"
 { emit_line_note (input_filename, lineno);
 		  pushlevel (0);
 		  clear_last_expr ();
 		  push_momentary ();
 		  expand_start_bindings (0); ;
     break;}
-case 574:
-#line 3044 "parse.y"
+case 573:
+#line 3042 "parse.y"
 { if (flag_ansi)
 		    pedwarn ("ANSI C++ forbids label declarations"); ;
     break;}
-case 577:
-#line 3055 "parse.y"
+case 576:
+#line 3053 "parse.y"
 { tree link;
 		  for (link = yyvsp[-1].ttype; link; link = TREE_CHAIN (link))
 		    {
@@ -6640,63 +6586,63 @@
 		    }
 		;
     break;}
-case 578:
-#line 3069 "parse.y"
+case 577:
+#line 3067 "parse.y"
 {;
     break;}
-case 580:
-#line 3074 "parse.y"
+case 579:
+#line 3072 "parse.y"
 { expand_end_bindings (getdecls (), kept_level_p(), 1);
 		  yyval.ttype = poplevel (kept_level_p (), 1, 0);
 		  pop_momentary (); ;
     break;}
-case 581:
-#line 3078 "parse.y"
+case 580:
+#line 3076 "parse.y"
 { expand_end_bindings (getdecls (), kept_level_p(), 1);
 		  yyval.ttype = poplevel (kept_level_p (), 1, 0);
 		  pop_momentary (); ;
     break;}
-case 582:
-#line 3082 "parse.y"
+case 581:
+#line 3080 "parse.y"
 { expand_end_bindings (getdecls (), kept_level_p(), 1);
 		  yyval.ttype = poplevel (kept_level_p (), 0, 0);
 		  pop_momentary (); ;
     break;}
-case 583:
-#line 3086 "parse.y"
+case 582:
+#line 3084 "parse.y"
 { expand_end_bindings (getdecls (), kept_level_p(), 1);
 		  yyval.ttype = poplevel (kept_level_p (), 0, 0);
 		  pop_momentary (); ;
     break;}
-case 584:
-#line 3093 "parse.y"
+case 583:
+#line 3091 "parse.y"
 { cond_stmt_keyword = "if"; ;
     break;}
-case 585:
-#line 3095 "parse.y"
+case 584:
+#line 3093 "parse.y"
 { emit_line_note (input_filename, lineno);
 		  expand_start_cond (yyvsp[0].ttype, 0); ;
     break;}
-case 587:
-#line 3102 "parse.y"
+case 586:
+#line 3100 "parse.y"
 { finish_stmt (); ;
     break;}
-case 588:
-#line 3104 "parse.y"
+case 587:
+#line 3102 "parse.y"
 { expand_end_bindings (getdecls (), kept_level_p (), 1);
 		  yyval.ttype = poplevel (kept_level_p (), 1, 0);
 		  pop_momentary (); ;
     break;}
-case 589:
-#line 3111 "parse.y"
+case 588:
+#line 3109 "parse.y"
+{ finish_stmt (); ;
+    break;}
+case 590:
+#line 3115 "parse.y"
 { finish_stmt (); ;
     break;}
 case 591:
 #line 3117 "parse.y"
-{ finish_stmt (); ;
-    break;}
-case 592:
-#line 3119 "parse.y"
 {
 		  tree expr = yyvsp[-1].ttype;
 		  emit_line_note (input_filename, lineno);
@@ -6710,82 +6656,82 @@
 		  clear_momentary ();
 		  finish_stmt (); ;
     break;}
-case 593:
-#line 3132 "parse.y"
+case 592:
+#line 3130 "parse.y"
 { expand_start_else (); ;
     break;}
-case 594:
-#line 3134 "parse.y"
+case 593:
+#line 3132 "parse.y"
 { expand_end_cond ();
 		  expand_end_bindings (getdecls (), kept_level_p (), 1);
 		  poplevel (kept_level_p (), 1, 0);
 		  pop_momentary ();
 		  finish_stmt (); ;
     break;}
-case 595:
-#line 3140 "parse.y"
+case 594:
+#line 3138 "parse.y"
 { expand_end_cond ();
 		  expand_end_bindings (getdecls (), kept_level_p (), 1);
 		  poplevel (kept_level_p (), 1, 0);
 		  pop_momentary ();
 		  finish_stmt (); ;
     break;}
-case 596:
-#line 3146 "parse.y"
+case 595:
+#line 3144 "parse.y"
 { emit_nop ();
 		  emit_line_note (input_filename, lineno);
 		  expand_start_loop (1);
 		  cond_stmt_keyword = "while"; ;
     break;}
+case 596:
+#line 3149 "parse.y"
+{ expand_exit_loop_if_false (0, yyvsp[0].ttype); ;
+    break;}
 case 597:
 #line 3151 "parse.y"
-{ expand_exit_loop_if_false (0, yyvsp[0].ttype); ;
-    break;}
-case 598:
-#line 3153 "parse.y"
 { expand_end_bindings (getdecls (), kept_level_p (), 1);
 		  poplevel (kept_level_p (), 1, 0);
 		  pop_momentary ();
 		  expand_end_loop ();
 		  finish_stmt (); ;
     break;}
-case 599:
-#line 3159 "parse.y"
+case 598:
+#line 3157 "parse.y"
 { emit_nop ();
 		  emit_line_note (input_filename, lineno);
 		  expand_start_loop_continue_elsewhere (1); ;
     break;}
-case 600:
-#line 3163 "parse.y"
+case 599:
+#line 3161 "parse.y"
 { expand_loop_continue_here ();
 		  cond_stmt_keyword = "do"; ;
     break;}
-case 601:
-#line 3166 "parse.y"
+case 600:
+#line 3164 "parse.y"
 { emit_line_note (input_filename, lineno);
 		  expand_exit_loop_if_false (0, yyvsp[-1].ttype);
 		  expand_end_loop ();
 		  clear_momentary ();
 		  finish_stmt (); ;
     break;}
-case 602:
-#line 3172 "parse.y"
+case 601:
+#line 3170 "parse.y"
 { emit_nop ();
 		  emit_line_note (input_filename, lineno);
 		  if (yyvsp[0].ttype) cplus_expand_expr_stmt (yyvsp[0].ttype);
 		  expand_start_loop_continue_elsewhere (1); ;
     break;}
-case 603:
-#line 3177 "parse.y"
+case 602:
+#line 3175 "parse.y"
 { emit_line_note (input_filename, lineno);
 		  if (yyvsp[-1].ttype) expand_exit_loop_if_false (0, yyvsp[-1].ttype); ;
     break;}
-case 604:
-#line 3182 "parse.y"
+case 603:
+#line 3180 "parse.y"
 { push_momentary (); ;
     break;}
-case 605:
-#line 3184 "parse.y"
+case 604:
+#line 3182 "parse.y"
 { emit_line_note (input_filename, lineno);
 		  expand_end_bindings (getdecls (), kept_level_p (), 1);
 		  poplevel (kept_level_p (), 1, 0);
@@ -6796,24 +6742,24 @@
 		  expand_end_loop ();
 		  finish_stmt (); ;
     break;}
-case 606:
-#line 3194 "parse.y"
+case 605:
+#line 3192 "parse.y"
 { emit_nop ();
 		  emit_line_note (input_filename, lineno);
 		  expand_start_loop_continue_elsewhere (1); ;
     break;}
-case 607:
-#line 3198 "parse.y"
+case 606:
+#line 3196 "parse.y"
 { emit_line_note (input_filename, lineno);
 		  if (yyvsp[-1].ttype) expand_exit_loop_if_false (0, yyvsp[-1].ttype); ;
     break;}
-case 608:
-#line 3203 "parse.y"
+case 607:
+#line 3201 "parse.y"
 { push_momentary ();
 		  yyvsp[0].itype = lineno; ;
     break;}
-case 609:
-#line 3206 "parse.y"
+case 608:
+#line 3204 "parse.y"
 { emit_line_note (input_filename, (int) yyvsp[-2].itype);
 		  expand_end_bindings (getdecls (), kept_level_p (), 1);
 		  poplevel (kept_level_p (), 1, 0);
@@ -6825,16 +6771,16 @@
 		  finish_stmt ();
 		;
     break;}
-case 610:
-#line 3217 "parse.y"
+case 609:
+#line 3215 "parse.y"
 { emit_line_note (input_filename, lineno);
 		  c_expand_start_case (yyvsp[-1].ttype);
 		  /* Don't let the tree nodes for $4 be discarded by
 		     clear_momentary during the parsing of the next stmt.  */
 		  push_momentary (); ;
     break;}
-case 611:
-#line 3223 "parse.y"
+case 610:
+#line 3221 "parse.y"
 { expand_end_case (yyvsp[-3].ttype);
 		  pop_momentary ();
 		  expand_end_bindings (getdecls (), kept_level_p (), 1);
@@ -6842,8 +6788,8 @@
 		  pop_momentary ();
 		  finish_stmt (); ;
     break;}
-case 612:
-#line 3230 "parse.y"
+case 611:
+#line 3228 "parse.y"
 { register tree value = check_cp_case_value (yyvsp[-1].ttype);
 		  register tree label
 		    = build_decl (LABEL_DECL, NULL_TREE, NULL_TREE);
@@ -6868,8 +6814,8 @@
 		  define_case_label (label);
 		;
     break;}
-case 614:
-#line 3255 "parse.y"
+case 613:
+#line 3253 "parse.y"
 { register tree value1 = check_cp_case_value (yyvsp[-3].ttype);
 		  register tree value2 = check_cp_case_value (yyvsp[-1].ttype);
 		  register tree label
@@ -6901,8 +6847,8 @@
 		  define_case_label (label);
 		;
     break;}
-case 616:
-#line 3287 "parse.y"
+case 615:
+#line 3285 "parse.y"
 {
 		  tree duplicate;
 		  register tree label
@@ -6918,40 +6864,40 @@
 		  define_case_label (NULL_TREE);
 		;
     break;}
-case 618:
-#line 3303 "parse.y"
+case 617:
+#line 3301 "parse.y"
 { emit_line_note (input_filename, lineno);
 		  if ( ! expand_exit_something ())
 		    error ("break statement not within loop or switch"); ;
     break;}
-case 619:
-#line 3307 "parse.y"
+case 618:
+#line 3305 "parse.y"
 { emit_line_note (input_filename, lineno);
 		  if (! expand_continue_loop (0))
 		    error ("continue statement not within a loop"); ;
     break;}
-case 620:
-#line 3311 "parse.y"
+case 619:
+#line 3309 "parse.y"
 { emit_line_note (input_filename, lineno);
 		  c_expand_return (NULL_TREE); ;
     break;}
-case 621:
-#line 3314 "parse.y"
+case 620:
+#line 3312 "parse.y"
 { emit_line_note (input_filename, lineno);
 		  c_expand_return (yyvsp[-1].ttype);
 		  finish_stmt ();
 		;
     break;}
-case 622:
-#line 3319 "parse.y"
+case 621:
+#line 3317 "parse.y"
 { if (TREE_CHAIN (yyvsp[-2].ttype)) yyvsp[-2].ttype = combine_strings (yyvsp[-2].ttype);
 		  emit_line_note (input_filename, lineno);
 		  expand_asm (yyvsp[-2].ttype);
 		  finish_stmt ();
 		;
     break;}
-case 623:
-#line 3326 "parse.y"
+case 622:
+#line 3324 "parse.y"
 { if (TREE_CHAIN (yyvsp[-4].ttype)) yyvsp[-4].ttype = combine_strings (yyvsp[-4].ttype);
 		  emit_line_note (input_filename, lineno);
 		  c_expand_asm_operands (yyvsp[-4].ttype, yyvsp[-2].ttype, NULL_TREE, NULL_TREE,
@@ -6960,8 +6906,8 @@
 		  finish_stmt ();
 		;
     break;}
-case 624:
-#line 3335 "parse.y"
+case 623:
+#line 3333 "parse.y"
 { if (TREE_CHAIN (yyvsp[-6].ttype)) yyvsp[-6].ttype = combine_strings (yyvsp[-6].ttype);
 		  emit_line_note (input_filename, lineno);
 		  c_expand_asm_operands (yyvsp[-6].ttype, yyvsp[-4].ttype, yyvsp[-2].ttype, NULL_TREE,
@@ -6970,8 +6916,8 @@
 		  finish_stmt ();
 		;
     break;}
-case 625:
-#line 3345 "parse.y"
+case 624:
+#line 3343 "parse.y"
 { if (TREE_CHAIN (yyvsp[-8].ttype)) yyvsp[-8].ttype = combine_strings (yyvsp[-8].ttype);
 		  emit_line_note (input_filename, lineno);
 		  c_expand_asm_operands (yyvsp[-8].ttype, yyvsp[-6].ttype, yyvsp[-4].ttype, yyvsp[-2].ttype,
@@ -6980,83 +6926,83 @@
 		  finish_stmt ();
 		;
     break;}
-case 626:
-#line 3353 "parse.y"
+case 625:
+#line 3351 "parse.y"
 { emit_line_note (input_filename, lineno);
 		  expand_computed_goto (yyvsp[-1].ttype); ;
     break;}
-case 627:
-#line 3356 "parse.y"
+case 626:
+#line 3354 "parse.y"
 { tree decl;
 		  emit_line_note (input_filename, lineno);
 		  decl = lookup_label (yyvsp[-1].ttype);
 		  TREE_USED (decl) = 1;
 		  expand_goto (decl); ;
     break;}
-case 628:
-#line 3362 "parse.y"
+case 627:
+#line 3360 "parse.y"
 { finish_stmt (); ;
     break;}
-case 629:
-#line 3364 "parse.y"
+case 628:
+#line 3362 "parse.y"
 { error ("label must be followed by statement");
 		  yyungetc ('}', 0);
 		  finish_stmt (); ;
     break;}
-case 630:
-#line 3368 "parse.y"
+case 629:
+#line 3366 "parse.y"
 { finish_stmt (); ;
     break;}
-case 632:
-#line 3374 "parse.y"
+case 631:
+#line 3372 "parse.y"
 { expand_start_try_stmts (); ;
     break;}
-case 633:
-#line 3376 "parse.y"
+case 632:
+#line 3374 "parse.y"
 { expand_end_try_stmts ();
 		  expand_start_all_catch (); ;
     break;}
-case 634:
-#line 3379 "parse.y"
+case 633:
+#line 3377 "parse.y"
 { expand_end_all_catch (); ;
     break;}
-case 635:
-#line 3387 "parse.y"
+case 634:
+#line 3385 "parse.y"
 { expand_end_bindings (0,1,1);
 		  poplevel (2,0,0);
 		;
     break;}
-case 636:
-#line 3391 "parse.y"
+case 635:
+#line 3389 "parse.y"
 { expand_end_bindings (0,1,1);
 		  poplevel (2,0,0);
 		;
     break;}
-case 637:
-#line 3395 "parse.y"
+case 636:
+#line 3393 "parse.y"
 { expand_end_bindings (0,1,1);
 		  poplevel (2,0,0);
 		;
     break;}
-case 639:
-#line 3403 "parse.y"
+case 638:
+#line 3401 "parse.y"
 { emit_line_note (input_filename, lineno); ;
     break;}
-case 640:
-#line 3405 "parse.y"
+case 639:
+#line 3403 "parse.y"
 { expand_end_catch_block (); ;
     break;}
-case 643:
-#line 3415 "parse.y"
+case 642:
+#line 3413 "parse.y"
 { expand_start_catch_block (NULL_TREE, NULL_TREE); ;
     break;}
-case 644:
-#line 3427 "parse.y"
+case 643:
+#line 3425 "parse.y"
 { expand_start_catch_block (TREE_PURPOSE (yyvsp[-1].ttype),
 					    TREE_VALUE (yyvsp[-1].ttype)); ;
     break;}
-case 645:
-#line 3433 "parse.y"
+case 644:
+#line 3431 "parse.y"
 { tree label;
 		do_label:
 		  label = define_label (input_filename, lineno, yyvsp[-1].ttype);
@@ -7064,25 +7010,29 @@
 		    expand_label (label);
 		;
     break;}
+case 645:
+#line 3438 "parse.y"
+{ goto do_label; ;
+    break;}
 case 646:
 #line 3440 "parse.y"
 { goto do_label; ;
     break;}
 case 647:
-#line 3442 "parse.y"
-{ goto do_label; ;
+#line 3445 "parse.y"
+{ yyval.ttype = NULL_TREE; ;
     break;}
 case 648:
 #line 3447 "parse.y"
-{ yyval.ttype = NULL_TREE; ;
+{ yyval.ttype = yyvsp[-1].ttype; ;
     break;}
 case 649:
 #line 3449 "parse.y"
-{ yyval.ttype = yyvsp[-1].ttype; ;
+{ yyval.ttype = NULL_TREE; ;
     break;}
 case 650:
-#line 3451 "parse.y"
-{ yyval.ttype = NULL_TREE; ;
+#line 3454 "parse.y"
+{ yyval.itype = 0; ;
     break;}
 case 651:
 #line 3456 "parse.y"
@@ -7090,55 +7040,51 @@
     break;}
 case 652:
 #line 3458 "parse.y"
-{ yyval.itype = 0; ;
+{ yyval.itype = 1; ;
     break;}
 case 653:
 #line 3460 "parse.y"
-{ yyval.itype = 1; ;
-    break;}
-case 654:
-#line 3462 "parse.y"
 { yyval.itype = -1; ;
     break;}
-case 655:
-#line 3469 "parse.y"
+case 654:
+#line 3467 "parse.y"
 { emit_line_note (input_filename, lineno);
 		  yyval.ttype = NULL_TREE; ;
     break;}
-case 656:
-#line 3472 "parse.y"
+case 655:
+#line 3470 "parse.y"
 { emit_line_note (input_filename, lineno); ;
     break;}
-case 657:
-#line 3477 "parse.y"
+case 656:
+#line 3475 "parse.y"
 { yyval.ttype = NULL_TREE; ;
     break;}
-case 659:
-#line 3480 "parse.y"
+case 658:
+#line 3478 "parse.y"
 { yyval.ttype = NULL_TREE; ;
     break;}
-case 660:
-#line 3486 "parse.y"
+case 659:
+#line 3484 "parse.y"
 { yyval.ttype = NULL_TREE; ;
     break;}
-case 663:
-#line 3493 "parse.y"
+case 662:
+#line 3491 "parse.y"
 { yyval.ttype = chainon (yyval.ttype, yyvsp[0].ttype); ;
     break;}
-case 664:
-#line 3498 "parse.y"
+case 663:
+#line 3496 "parse.y"
 { yyval.ttype = build_tree_list (yyval.ttype, yyvsp[-1].ttype); ;
     break;}
-case 665:
-#line 3503 "parse.y"
+case 664:
+#line 3501 "parse.y"
 { yyval.ttype = tree_cons (NULL_TREE, yyval.ttype, NULL_TREE); ;
     break;}
-case 666:
-#line 3505 "parse.y"
+case 665:
+#line 3503 "parse.y"
 { yyval.ttype = tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype); ;
     break;}
-case 667:
-#line 3515 "parse.y"
+case 666:
+#line 3513 "parse.y"
 {
 		  if (strict_prototype)
 		    yyval.ttype = void_list_node;
@@ -7146,39 +7092,39 @@
 		    yyval.ttype = NULL_TREE;
 		;
     break;}
-case 669:
-#line 3523 "parse.y"
+case 668:
+#line 3521 "parse.y"
 { yyval.ttype = tree_cons (NULL_TREE, yyval.ttype, void_list_node);
 		  TREE_PARMLIST (yyval.ttype) = 1; ;
     break;}
-case 670:
-#line 3531 "parse.y"
+case 669:
+#line 3529 "parse.y"
 {
 		  yyval.ttype = chainon (yyval.ttype, void_list_node);
 		  TREE_PARMLIST (yyval.ttype) = 1;
 		;
     break;}
-case 671:
-#line 3536 "parse.y"
+case 670:
+#line 3534 "parse.y"
 {
 		  TREE_PARMLIST (yyval.ttype) = 1;
 		;
     break;}
-case 672:
-#line 3541 "parse.y"
+case 671:
+#line 3539 "parse.y"
 {
 		  TREE_PARMLIST (yyval.ttype) = 1;
 		;
     break;}
-case 673:
-#line 3545 "parse.y"
+case 672:
+#line 3543 "parse.y"
 {
 		  yyval.ttype = build_tree_list (NULL_TREE, yyval.ttype); 
 		  TREE_PARMLIST (yyval.ttype) = 1;
 		;
     break;}
-case 674:
-#line 3550 "parse.y"
+case 673:
+#line 3548 "parse.y"
 {
 		  /* ARM $8.2.5 has this as a boxed-off comment.  */
 		  if (pedantic)
@@ -7186,27 +7132,27 @@
 		  yyval.ttype = NULL_TREE;
 		;
     break;}
-case 675:
-#line 3557 "parse.y"
+case 674:
+#line 3555 "parse.y"
 {
 		  TREE_PARMLIST (yyval.ttype) = 1;
 		;
     break;}
-case 676:
-#line 3561 "parse.y"
+case 675:
+#line 3559 "parse.y"
 {
 		  TREE_PARMLIST (yyval.ttype) = 1;
 		;
     break;}
-case 677:
-#line 3565 "parse.y"
+case 676:
+#line 3563 "parse.y"
 {
 		  yyval.ttype = build_tree_list (NULL_TREE, yyval.ttype);
 		  TREE_PARMLIST (yyval.ttype) = 1;
 		;
     break;}
-case 678:
-#line 3570 "parse.y"
+case 677:
+#line 3568 "parse.y"
 {
 		  /* This helps us recover from really nasty
 		     parse errors, for example, a missing right
@@ -7218,8 +7164,8 @@
 		  yychar = ')';
 		;
     break;}
-case 679:
-#line 3581 "parse.y"
+case 678:
+#line 3579 "parse.y"
 {
 		  /* This helps us recover from really nasty
 		     parse errors, for example, a missing right
@@ -7231,184 +7177,188 @@
 		  yychar = ')';
 		;
     break;}
+case 679:
+#line 3594 "parse.y"
+{ yyval.ttype = build_tree_list (NULL_TREE, yyval.ttype); ;
+    break;}
 case 680:
 #line 3596 "parse.y"
-{ yyval.ttype = build_tree_list (NULL_TREE, yyval.ttype); ;
+{ yyval.ttype = build_tree_list (yyvsp[0].ttype, yyval.ttype); ;
     break;}
 case 681:
 #line 3598 "parse.y"
-{ yyval.ttype = build_tree_list (yyvsp[0].ttype, yyval.ttype); ;
+{ yyval.ttype = chainon (yyval.ttype, yyvsp[0].ttype); ;
     break;}
 case 682:
 #line 3600 "parse.y"
-{ yyval.ttype = chainon (yyval.ttype, yyvsp[0].ttype); ;
+{ yyval.ttype = chainon (yyval.ttype, build_tree_list (NULL_TREE, yyvsp[0].ttype)); ;
     break;}
 case 683:
 #line 3602 "parse.y"
-{ yyval.ttype = chainon (yyval.ttype, build_tree_list (NULL_TREE, yyvsp[0].ttype)); ;
-    break;}
-case 684:
-#line 3604 "parse.y"
 { yyval.ttype = chainon (yyval.ttype, build_tree_list (yyvsp[0].ttype, yyvsp[-2].ttype)); ;
     break;}
-case 686:
-#line 3610 "parse.y"
+case 685:
+#line 3608 "parse.y"
 { yyval.ttype = build_tree_list (NULL_TREE, yyval.ttype); ;
     break;}
+case 686:
+#line 3631 "parse.y"
+{ yyval.ttype = build_tree_list (yyval.ttype, yyvsp[0].ttype); ;
+    break;}
 case 687:
 #line 3633 "parse.y"
 { yyval.ttype = build_tree_list (yyval.ttype, yyvsp[0].ttype); ;
     break;}
 case 688:
 #line 3635 "parse.y"
-{ yyval.ttype = build_tree_list (yyval.ttype, yyvsp[0].ttype); ;
+{ yyval.ttype = build_tree_list (get_decl_list (yyval.ttype), yyvsp[0].ttype); ;
     break;}
 case 689:
 #line 3637 "parse.y"
-{ yyval.ttype = build_tree_list (get_decl_list (yyval.ttype), yyvsp[0].ttype); ;
+{ yyval.ttype = build_tree_list (yyval.ttype, yyvsp[0].ttype); ;
     break;}
 case 690:
 #line 3639 "parse.y"
-{ yyval.ttype = build_tree_list (yyval.ttype, yyvsp[0].ttype); ;
+{ yyval.ttype = build_tree_list (yyval.ttype, NULL_TREE); ;
     break;}
 case 691:
 #line 3641 "parse.y"
-{ yyval.ttype = build_tree_list (yyval.ttype, NULL_TREE); ;
+{ yyval.ttype = build_tree_list (yyval.ttype, yyvsp[0].ttype); ;
     break;}
 case 692:
-#line 3643 "parse.y"
-{ yyval.ttype = build_tree_list (yyval.ttype, yyvsp[0].ttype); ;
+#line 3646 "parse.y"
+{ yyval.ttype = build_tree_list (NULL_TREE, yyval.ttype); ;
     break;}
 case 693:
 #line 3648 "parse.y"
-{ yyval.ttype = build_tree_list (NULL_TREE, yyval.ttype); ;
-    break;}
-case 694:
-#line 3650 "parse.y"
 { yyval.ttype = build_tree_list (yyvsp[0].ttype, yyval.ttype); ;
     break;}
-case 697:
-#line 3659 "parse.y"
+case 696:
+#line 3657 "parse.y"
 { see_typename (); ;
     break;}
-case 698:
-#line 3682 "parse.y"
+case 697:
+#line 3680 "parse.y"
 {
 		  warning ("type specifier omitted for parameter");
 		  yyval.ttype = build_tree_list (TREE_PURPOSE (TREE_VALUE (yyvsp[-1].ttype)), NULL_TREE);
 		;
     break;}
-case 699:
-#line 3687 "parse.y"
+case 698:
+#line 3685 "parse.y"
 {
 		  warning ("type specifier omitted for parameter");
 		  yyval.ttype = build_tree_list (TREE_PURPOSE (TREE_VALUE (yyvsp[-2].ttype)), yyval.ttype);
 		;
     break;}
-case 700:
-#line 3695 "parse.y"
+case 699:
+#line 3693 "parse.y"
 { yyval.ttype = NULL_TREE; ;
     break;}
-case 701:
-#line 3697 "parse.y"
+case 700:
+#line 3695 "parse.y"
 { yyval.ttype = yyvsp[-1].ttype; ;
     break;}
-case 702:
-#line 3702 "parse.y"
+case 701:
+#line 3700 "parse.y"
 { yyval.ttype = build_decl_list (NULL_TREE, yyval.ttype); ;
     break;}
-case 704:
-#line 3708 "parse.y"
+case 703:
+#line 3706 "parse.y"
 {
 		  TREE_CHAIN (yyvsp[0].ttype) = yyval.ttype;
 		  yyval.ttype = yyvsp[0].ttype;
 		;
     break;}
+case 704:
+#line 3714 "parse.y"
+{ yyval.ttype = NULL_TREE; ;
+    break;}
 case 705:
 #line 3716 "parse.y"
-{ yyval.ttype = NULL_TREE; ;
+{ yyval.ttype = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ;
     break;}
 case 706:
 #line 3718 "parse.y"
-{ yyval.ttype = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ;
+{ yyval.ttype = make_reference_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ;
     break;}
 case 707:
 #line 3720 "parse.y"
-{ yyval.ttype = make_reference_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ;
-    break;}
-case 708:
-#line 3722 "parse.y"
 { tree arg = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype);
 		  yyval.ttype = build_parse_node (SCOPE_REF, yyvsp[-2].ttype, arg);
 		;
     break;}
-case 709:
-#line 3728 "parse.y"
+case 708:
+#line 3726 "parse.y"
 { got_scope = NULL_TREE; ;
     break;}
+case 709:
+#line 3731 "parse.y"
+{ yyval.ttype = ansi_opname[MULT_EXPR]; ;
+    break;}
 case 710:
 #line 3733 "parse.y"
-{ yyval.ttype = ansi_opname[MULT_EXPR]; ;
+{ yyval.ttype = ansi_opname[TRUNC_DIV_EXPR]; ;
     break;}
 case 711:
 #line 3735 "parse.y"
-{ yyval.ttype = ansi_opname[TRUNC_DIV_EXPR]; ;
+{ yyval.ttype = ansi_opname[TRUNC_MOD_EXPR]; ;
     break;}
 case 712:
 #line 3737 "parse.y"
-{ yyval.ttype = ansi_opname[TRUNC_MOD_EXPR]; ;
+{ yyval.ttype = ansi_opname[PLUS_EXPR]; ;
     break;}
 case 713:
 #line 3739 "parse.y"
-{ yyval.ttype = ansi_opname[PLUS_EXPR]; ;
+{ yyval.ttype = ansi_opname[MINUS_EXPR]; ;
     break;}
 case 714:
 #line 3741 "parse.y"
-{ yyval.ttype = ansi_opname[MINUS_EXPR]; ;
+{ yyval.ttype = ansi_opname[BIT_AND_EXPR]; ;
     break;}
 case 715:
 #line 3743 "parse.y"
-{ yyval.ttype = ansi_opname[BIT_AND_EXPR]; ;
+{ yyval.ttype = ansi_opname[BIT_IOR_EXPR]; ;
     break;}
 case 716:
 #line 3745 "parse.y"
-{ yyval.ttype = ansi_opname[BIT_IOR_EXPR]; ;
+{ yyval.ttype = ansi_opname[BIT_XOR_EXPR]; ;
     break;}
 case 717:
 #line 3747 "parse.y"
-{ yyval.ttype = ansi_opname[BIT_XOR_EXPR]; ;
+{ yyval.ttype = ansi_opname[BIT_NOT_EXPR]; ;
     break;}
 case 718:
 #line 3749 "parse.y"
-{ yyval.ttype = ansi_opname[BIT_NOT_EXPR]; ;
+{ yyval.ttype = ansi_opname[COMPOUND_EXPR]; ;
     break;}
 case 719:
 #line 3751 "parse.y"
-{ yyval.ttype = ansi_opname[COMPOUND_EXPR]; ;
+{ yyval.ttype = ansi_opname[yyvsp[0].code]; ;
     break;}
 case 720:
 #line 3753 "parse.y"
-{ yyval.ttype = ansi_opname[yyvsp[0].code]; ;
+{ yyval.ttype = ansi_opname[LT_EXPR]; ;
     break;}
 case 721:
 #line 3755 "parse.y"
-{ yyval.ttype = ansi_opname[LT_EXPR]; ;
+{ yyval.ttype = ansi_opname[GT_EXPR]; ;
     break;}
 case 722:
 #line 3757 "parse.y"
-{ yyval.ttype = ansi_opname[GT_EXPR]; ;
+{ yyval.ttype = ansi_opname[yyvsp[0].code]; ;
     break;}
 case 723:
 #line 3759 "parse.y"
-{ yyval.ttype = ansi_opname[yyvsp[0].code]; ;
+{ yyval.ttype = ansi_assopname[yyvsp[0].code]; ;
     break;}
 case 724:
 #line 3761 "parse.y"
-{ yyval.ttype = ansi_assopname[yyvsp[0].code]; ;
+{ yyval.ttype = ansi_opname [MODIFY_EXPR]; ;
     break;}
 case 725:
 #line 3763 "parse.y"
-{ yyval.ttype = ansi_opname [MODIFY_EXPR]; ;
+{ yyval.ttype = ansi_opname[yyvsp[0].code]; ;
     break;}
 case 726:
 #line 3765 "parse.y"
@@ -7416,79 +7366,75 @@
     break;}
 case 727:
 #line 3767 "parse.y"
-{ yyval.ttype = ansi_opname[yyvsp[0].code]; ;
+{ yyval.ttype = ansi_opname[POSTINCREMENT_EXPR]; ;
     break;}
 case 728:
 #line 3769 "parse.y"
-{ yyval.ttype = ansi_opname[POSTINCREMENT_EXPR]; ;
+{ yyval.ttype = ansi_opname[PREDECREMENT_EXPR]; ;
     break;}
 case 729:
 #line 3771 "parse.y"
-{ yyval.ttype = ansi_opname[PREDECREMENT_EXPR]; ;
+{ yyval.ttype = ansi_opname[TRUTH_ANDIF_EXPR]; ;
     break;}
 case 730:
 #line 3773 "parse.y"
-{ yyval.ttype = ansi_opname[TRUTH_ANDIF_EXPR]; ;
+{ yyval.ttype = ansi_opname[TRUTH_ORIF_EXPR]; ;
     break;}
 case 731:
 #line 3775 "parse.y"
-{ yyval.ttype = ansi_opname[TRUTH_ORIF_EXPR]; ;
+{ yyval.ttype = ansi_opname[TRUTH_NOT_EXPR]; ;
     break;}
 case 732:
 #line 3777 "parse.y"
-{ yyval.ttype = ansi_opname[TRUTH_NOT_EXPR]; ;
+{ yyval.ttype = ansi_opname[COND_EXPR]; ;
     break;}
 case 733:
 #line 3779 "parse.y"
-{ yyval.ttype = ansi_opname[COND_EXPR]; ;
+{ yyval.ttype = ansi_opname[yyvsp[0].code]; ;
     break;}
 case 734:
 #line 3781 "parse.y"
-{ yyval.ttype = ansi_opname[yyvsp[0].code]; ;
+{ yyval.ttype = ansi_opname[COMPONENT_REF]; ;
     break;}
 case 735:
 #line 3783 "parse.y"
-{ yyval.ttype = ansi_opname[COMPONENT_REF]; ;
+{ yyval.ttype = ansi_opname[MEMBER_REF]; ;
     break;}
 case 736:
 #line 3785 "parse.y"
-{ yyval.ttype = ansi_opname[MEMBER_REF]; ;
+{ yyval.ttype = ansi_opname[CALL_EXPR]; ;
     break;}
 case 737:
 #line 3787 "parse.y"
-{ yyval.ttype = ansi_opname[CALL_EXPR]; ;
+{ yyval.ttype = ansi_opname[ARRAY_REF]; ;
     break;}
 case 738:
 #line 3789 "parse.y"
-{ yyval.ttype = ansi_opname[ARRAY_REF]; ;
+{ yyval.ttype = ansi_opname[NEW_EXPR]; ;
     break;}
 case 739:
 #line 3791 "parse.y"
-{ yyval.ttype = ansi_opname[NEW_EXPR]; ;
+{ yyval.ttype = ansi_opname[DELETE_EXPR]; ;
     break;}
 case 740:
 #line 3793 "parse.y"
-{ yyval.ttype = ansi_opname[DELETE_EXPR]; ;
+{ yyval.ttype = ansi_opname[VEC_NEW_EXPR]; ;
     break;}
 case 741:
 #line 3795 "parse.y"
-{ yyval.ttype = ansi_opname[VEC_NEW_EXPR]; ;
+{ yyval.ttype = ansi_opname[VEC_DELETE_EXPR]; ;
     break;}
 case 742:
-#line 3797 "parse.y"
-{ yyval.ttype = ansi_opname[VEC_DELETE_EXPR]; ;
+#line 3798 "parse.y"
+{ yyval.ttype = grokoptypename (yyvsp[-1].ttype, yyvsp[0].ttype); ;
     break;}
 case 743:
 #line 3800 "parse.y"
-{ yyval.ttype = grokoptypename (yyvsp[-1].ttype, yyvsp[0].ttype); ;
-    break;}
-case 744:
-#line 3802 "parse.y"
 { yyval.ttype = ansi_opname[ERROR_MARK]; ;
     break;}
 }
    /* the action file gets copied in in place of this dollarsign */
-#line 480 "/usr/local/lib/bison.simple"
+#line 465 "/usr/local/lib/bison.simple"
 
   yyvsp -= yylen;
   yyssp -= yylen;
@@ -7684,7 +7630,7 @@
   yystate = yyn;
   goto yynewstate;
 }
-#line 3805 "parse.y"
+#line 3803 "parse.y"
 
 
 #ifdef SPEW_DEBUG
diff -r -u -H -N gcc-2.6.3/cse.c gcc-i2.6.3/cse.c
--- gcc-2.6.3/cse.c	Tue Nov  1 18:38:40 1994
+++ gcc-i2.6.3/cse.c	Thu Feb 16 11:58:55 1995
@@ -6007,6 +6007,29 @@
       sets = (struct set *) alloca (sizeof (struct set));
       sets[0].rtl = x;
 
+/* intel1 */
+#ifdef STACK_REGS
+#ifdef IS_STACK_MODE
+      if (IS_STACK_MODE (DFmode) && GET_CODE (SET_SRC (x)) == CONST_DOUBLE 
+         && GET_CODE (SET_DEST (x)) == REG)
+        {
+           /* not worthwhile to hold on stack */
+	  rtx tem = find_reg_note (insn, REG_EQUAL, 0);
+	  
+	  /* Record the actual constant value in a REG_EQUAL note, making
+	     a new one if one does not already exist.  */
+	  if (tem)
+	    XEXP (tem, 0) = SET_SRC(x);
+	  else
+	    REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL,
+				        SET_SRC(x), REG_NOTES (insn));
+
+	  invalidate (SET_DEST (x), GET_MODE(x) );
+        }
+      else
+      
+#endif
+#endif
       /* Ignore SETs that are unconditional jumps.
 	 They never need cse processing, so this does not hurt.
 	 The reason is not efficiency but rather
@@ -6625,6 +6648,32 @@
       if (dest == pc_rtx && src_const && GET_CODE (src_const) == LABEL_REF)
 	src_folded = src_const, src_folded_cost = -1;
 	  
+#ifdef SAVE_ON_REGS
+      /* intel1 If src is of form  (reg1 OP const) and src_folded
+         is of form (reg2 OP const) and the costs are the same
+         and reg1 != reg2,
+         then bump up the cost of src_folded so that src will be
+         preferred.  The reason for this is that if reg2 is used
+         here it's life may be extended thereby increasing register
+         pressure and causing superfulous movs.  */
+      {
+        char * fmt;
+        if (src)
+          fmt = GET_RTX_FORMAT (GET_CODE (src));
+        if (src && src_folded && src_cost == src_folded_cost
+            && GET_CODE (src) == GET_CODE (src_folded) 
+            && GET_RTX_LENGTH (GET_CODE (src)) == 2
+            && fmt[0] == 'e' && fmt[1] == 'e'
+            && GET_CODE (XEXP (src, 0)) == REG
+            && GET_CODE (XEXP (src, 1)) == CONST_INT 
+            && GET_CODE (XEXP (src_folded, 0)) == REG
+            && GET_CODE (XEXP (src_folded, 1)) == CONST_INT 
+            && !rtx_equal_p (XEXP (src, 0), XEXP (src_folded, 0)))
+          {
+            src_folded_cost++;
+          }          
+      }
+#endif
       /* Terminate loop when replacement made.  This must terminate since
          the current contents will be tested and will always be valid.  */
       while (1)
@@ -7068,6 +7117,16 @@
 	    if (sets[i].src_elt == 0)
 	      {
 		register struct table_elt *elt;
+		/* intel1 */
+		int do_rehash=0;
+
+                /* intel1 */
+		if(GET_CODE(src)==REG && 
+		   !REGNO_QTY_VALID_P (REGNO(src)))
+		    { /* we will want to rehash all expressions based of src since
+		         reg_qty[REGNO(src)] is about to change */
+		      do_rehash = 1;
+		    }
 
 		/* Note that these insert_regs calls cannot remove
 		   any of the src_elt's, because they would have failed to
diff -r -u -H -N gcc-2.6.3/expr.c gcc-i2.6.3/expr.c
--- gcc-2.6.3/expr.c	Wed Nov 30 19:08:49 1994
+++ gcc-i2.6.3/expr.c	Wed Feb 15 23:19:22 1995
@@ -23,6 +23,8 @@
 #include "rtl.h"
 #include "tree.h"
 #include "obstack.h"
+/* intel1 */
+#include "c-tree.h"
 #include "flags.h"
 #include "regs.h"
 #include "function.h"
@@ -8596,6 +8598,12 @@
 	  && (i = floor_log2 (TREE_INT_CST_LOW (TREE_OPERAND (exp, 1)))) >= 0
 	  && (mode = mode_for_size (i + 1, MODE_INT, 0)) != BLKmode
 	  && (type = type_for_mode (mode, 1)) != 0
+      /* intel1 */
+      && !(SLOW_SHORT_ACCESS
+         && (type == short_unsigned_type_node
+             || type == short_integer_type_node
+             || type == intHI_type_node
+             || type == unsigned_intHI_type_node))
 	  && TYPE_PRECISION (type) < TYPE_PRECISION (TREE_TYPE (exp))
 	  && (cmp_optab->handlers[(int) TYPE_MODE (type)].insn_code
 	      != CODE_FOR_nothing))
@@ -8751,6 +8759,12 @@
 	type = type_for_size (bitsize, unsignedp);
 	if (! SLOW_BYTE_ACCESS
 	    && type != 0 && bitsize >= 0
+	    /* intel1 */
+	    && !(SLOW_SHORT_ACCESS 
+	         && (type == short_unsigned_type_node 
+	             || type == short_integer_type_node
+	             || type == intHI_type_node 
+	             || type == unsigned_intHI_type_node))
 	    && TYPE_PRECISION (type) < TYPE_PRECISION (TREE_TYPE (exp))
 	    && (cmp_optab->handlers[(int) TYPE_MODE (type)].insn_code
 		!= CODE_FOR_nothing))
diff -r -u -H -N gcc-2.6.3/flags.h gcc-i2.6.3/flags.h
--- gcc-2.6.3/flags.h	Thu May 12 20:04:27 1994
+++ gcc-i2.6.3/flags.h	Wed Feb 15 22:47:02 1995
@@ -357,3 +357,149 @@
    function.  */
 
 extern int current_function_has_nonlocal_goto;
+
+/* intel1 our optimization controllers */
+
+/* Optimize usage of registers for memory addresses */
+
+extern int flag_opt_reg_use;
+
+/* Do reduce all the mem address givs */
+
+extern int flag_all_mem_givs;
+
+/* Try to treat index terms of addresses as reducible mem givs */
+
+extern int flag_reduce_index_givs;
+
+/* After reload try to replace spill slots with equivalent registers */
+
+extern int flag_peep_spills;
+
+/* After reload try to optimize usage of spill slots in loops */
+
+extern int flag_loop_after_global;
+
+/* In optimization of loops treats jumps backwards as not nullifying
+   optimization opportunities.  */
+   
+extern int flag_jump_back;
+
+/* Do loop copy propogation */
+
+extern int flag_copy_prop;
+
+/* Do compare elimination */
+
+extern int flag_compare_elim;
+
+/* Do a mini software pipelining on stack registers */
+
+extern int flag_sftwr_pipe;
+
+/* Try aggressive changing of jumps taken to jumps not taken */
+
+extern int flag_opt_jumps_out;
+
+/* Try to replace memory operands with equivalent registers in first
+   pass of loop optimize */
+   
+extern int flag_replace_mem;
+
+/* Try to replace memory operands with equivalent stack registers in first
+   pass of loop optimize */
+   
+extern int flag_replace_stack_mem;
+
+/* After reload if a register is marked dead at a copy into another
+   register - see if the other register can be used in the first place.
+   Thereby eleiminating the copy.  */
+   
+extern int flag_reg_reg_copy_opt;
+
+/* Move stack registers that will be compared for equality off, the
+   stack before the comparison.  */
+   
+extern int flag_do_offload;
+
+/* Optimize usage of stack registers from the stack */
+
+extern int flag_opt_reg_stack;
+
+/* cse is sometimes detrimental - see flow.c */
+
+extern int flag_correct_cse_mistakes;
+
+/* Try to push loads back into loops if the loaded register has been spilled */
+
+extern int flag_push_load_into_loop;
+
+/* After reload use available registers to load memory operands into
+  them and use the register instead of the memory operand.  */
+  
+extern int flag_risc;
+
+/* After reload use available registers to load CONST_INTs into
+  them and then store the register instead of the CONST_INT.  */
+  
+extern int flag_risc_const;
+
+/* Allow scheduler to try to swap two instructions when the
+   first increments a register by a constant and the second
+   uses that register as a base
+*/
+
+extern int flag_swap_for_agi;
+
+/* A destination that was riscified should stay that way.  */
+
+extern int flag_risc_mem_dest;
+
+/* Try to use available registers so that a memory operand that is
+   reloaded will be reloaded into the same register.  This helps
+   loop_after_global.  */
+   
+extern int flag_replace_reload_regs;
+
+/* If the riscified instruction has not changed it's place in
+  scheduling then recombine it into a cisc instruction.  */
+  
+extern int flag_recombine;
+
+/* These negative flags needed to override optimization
+   levels which turn them on by default */
+   
+extern int flag_no_omit_frame_pointer;
+extern int flag_no_risc;
+extern int flag_no_risc_const;
+extern int flag_no_risc_mem_dest;
+extern int flag_no_recombine;
+/* Use the first pass of the scheduler to rearrange between
+   insns that reference stack registers.  */
+   
+extern int flag_schedule_stack_reg_insns;
+
+/* Use the first pass of the scheduler to rearrange between
+   insns that reference stack registers and those that don't
+   but not amongst themselves  */
+   
+extern int flag_interleave_stack_non_stack;
+
+/* These negative flags needed to override optimization
+   levels which turn them on by default */
+   
+extern int flag_no_schedule_stack_reg_insns;
+extern int flag_no_interleave_stack_non_stack;
+
+extern int flag_sign_extension_elim;
+
+/* Try to lift memory disambiguated memory operands that are stored
+   to in a loop into a register for the duration of the loop.  */
+   
+extern int flag_lift_stores;
+
+/* As above but do the disambiguation at runtime. i.e. there
+   will be two copies of the loop, one disambiguated one not,
+   And the decision of which one to run will be made at runtime.  */
+   
+extern int flag_runtime_lift_stores;
diff -r -u -H -N gcc-2.6.3/flow.c gcc-i2.6.3/flow.c
--- gcc-2.6.3/flow.c	Thu Nov 17 12:46:04 1994
+++ gcc-i2.6.3/flow.c	Thu Feb 16 12:14:28 1995
@@ -285,14 +285,14 @@
 static HARD_REG_SET elim_reg_set;
 
 /* Forward declarations */
-static void find_basic_blocks		PROTO((rtx, rtx));
+static void find_basic_blocks		PROTO((rtx, rtx, int));
 static int uses_reg_or_mem		PROTO((rtx));
 static void mark_label_ref		PROTO((rtx, rtx, int));
-static void life_analysis		PROTO((rtx, int));
+static void life_analysis		PROTO((rtx, int, int));
 void allocate_for_life_analysis		PROTO((void));
-static void init_regset_vector		PROTO((regset *, regset, int, int));
+/* intel2 static */ void init_regset_vector		PROTO((regset *, regset, int, int));
 static void propagate_block		PROTO((regset, rtx, rtx, int, 
-					       regset, int));
+					       regset, int, int));
 static int insn_dead_p			PROTO((rtx, regset, int));
 static int libcall_dead_p		PROTO((rtx, regset, rtx, rtx));
 static void mark_set_regs		PROTO((regset, regset, rtx,
@@ -305,16 +305,27 @@
 static int try_pre_increment		PROTO((rtx, rtx, HOST_WIDE_INT));
 static rtx find_use_as_address		PROTO((rtx, rtx, HOST_WIDE_INT));
 void dump_flow_info			PROTO((FILE *));
+/* intel1 */
+static void correct_cse_mistakes ();
+static void count_reg_uses ();
+static void do_correction ();
 
 /* Find basic blocks of the current function and perform data flow analysis.
    F is the first insn of the function and NREGS the number of register numbers
    in use.  */
 
 void
+/*
 flow_analysis (f, nregs, file)
+*/
+/* intel2 - added the change_f flag to disable changes to the insns, when called
+ * by memory_simplify. Don't apply any change to an insn if this flag == 0
+ */
+flow_analysis (f, nregs, file, change_f)
      rtx f;
      int nregs;
      FILE *file;
+	 int change_f; /* intel2 */
 {
   register rtx insn;
   register int i;
@@ -324,6 +335,14 @@
   static struct {int from, to; } eliminables[] = ELIMINABLE_REGS;
 #endif
 
+  /* intel1 */
+#ifdef SPARE_REGS
+  if (change_f && flag_opt_reg_stack)
+    {
+      nregs += SPARE_REGS;
+    }
+#endif
+
   /* Record which registers will be eliminated.  We use this in
      mark_used_regs. */
 
@@ -370,9 +389,13 @@
   /* Allocate some tables that last till end of compiling this function
      and some needed only in find_basic_blocks and life_analysis.  */
 
-  n_basic_blocks = i;
-  basic_block_head = (rtx *) oballoc (n_basic_blocks * sizeof (rtx));
-  basic_block_end = (rtx *) oballoc (n_basic_blocks * sizeof (rtx));
+  if (change_f || (n_basic_blocks!=i)) 
+  /* intel2 if change_f is 0 we may have already allocated basic blocks */
+    {
+      n_basic_blocks = i;
+      basic_block_head = (rtx *) oballoc (n_basic_blocks * sizeof (rtx));
+      basic_block_end = (rtx *) oballoc (n_basic_blocks * sizeof (rtx));
+    }
   basic_block_drops_in = (char *) alloca (n_basic_blocks);
   basic_block_loop_depth = (short *) alloca (n_basic_blocks * sizeof (short));
   uid_block_number
@@ -380,11 +403,16 @@
   uid_volatile = (char *) alloca (max_uid_for_flow + 1);
   bzero (uid_volatile, max_uid_for_flow + 1);
 
-  find_basic_blocks (f, nonlocal_label_list);
-  life_analysis (f, nregs);
+  find_basic_blocks (f, nonlocal_label_list /* intel2: */, change_f);
+  life_analysis (f, nregs /* intel2: */, change_f);
   if (file)
     dump_flow_info (file);
 
+  /* intel1 */
+  if (flag_correct_cse_mistakes && change_f)
+    {
+      correct_cse_mistakes (f, nregs, file);
+    }
   basic_block_drops_in = 0;
   uid_block_number = 0;
   basic_block_loop_depth = 0;
@@ -398,8 +426,9 @@
    NONLOCAL_LABEL_LIST is the same local variable from flow_analysis.  */
 
 static void
-find_basic_blocks (f, nonlocal_label_list)
+find_basic_blocks (f, nonlocal_label_list /* intel2: */, change_f)
      rtx f, nonlocal_label_list;
+     int change_f;/* intel2 */
 {
   register rtx insn;
   register int i;
@@ -627,7 +656,7 @@
 	 unreachable loops as unreachable.  */
 
       for (i = 0; i < n_basic_blocks; i++)
-	if (!block_live[i])
+	if (!block_live[i] /* intel2: */ && change_f)
 	  {
 	    insn = basic_block_head[i];
 	    while (1)
@@ -790,9 +819,10 @@
    regset_size and regset_bytes are also set here.  */
 
 static void
-life_analysis (f, nregs)
+life_analysis (f, nregs /* intel2: */, change_f)
      rtx f;
      int nregs;
+     int change_f;	/* intel2 */
 {
   register regset tem;
   int first_pass;
@@ -820,8 +850,14 @@
 
   max_regno = nregs;
 
-  bzero (regs_ever_live, sizeof regs_ever_live);
 
+  /* intel2 - begin */
+  /* Dont reset the regs_ever_live array if called from memory_simplify */
+  if (change_f)
+    {
+      /* intel2 - end */
+      bzero (regs_ever_live, sizeof regs_ever_live);
+    }
   /* Allocate and zero out many data structures
      that will record the data from lifetime analysis.  */
 
@@ -866,10 +902,32 @@
   for (insn = f; insn; insn = NEXT_INSN (insn))
     {
       enum rtx_code code1 = GET_CODE (insn);
-      if (code1 == CALL_INSN)
+      if (code1 == CALL_INSN /* intel2: */ && change_f)
 	INSN_VOLATILE (insn) = 1;
       else if (code1 == INSN || code1 == JUMP_INSN)
 	{
+		/* intel2 - begin */
+		/* if change_f is reset, i.e. we are called from memory_simplify, and
+		 * therefore we would like to update the insn's REG_DEAD notes.
+		 * If we find a REG_DEAD note, we remove it here.
+		 */
+		if (!change_f)
+		{
+			register rtx note;
+			
+
+			for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
+				if (REG_NOTE_KIND (note) == REG_DEAD
+				    || REG_NOTE_KIND (note) == REG_UNUSED)
+					remove_note(insn, note);
+		} 
+		/* intel2 - end */
+
+
+/* intel2 - begin */
+		if (change_f)
+		{
+/* intel2 - end */
 	  /* Delete (in effect) any obvious no-op moves.  */
 	  if (GET_CODE (PATTERN (insn)) == SET
 	      && GET_CODE (SET_DEST (PATTERN (insn))) == REG
@@ -930,6 +988,9 @@
 #endif
 		   && XEXP (SET_SRC (PATTERN (insn)), 0) == stack_pointer_rtx)
 	    INSN_VOLATILE (insn) = 1;
+		/* intel2 - begin */
+		} /* if (change_f) */
+		/* intel2 - end */
 	}
     }
 
@@ -1070,7 +1131,7 @@
 			       basic_block_head[i], basic_block_end[i], 0,
 			       first_pass ? basic_block_significant[i]
 			       : (regset) 0,
-			       i);
+			       i/* intel2: */, change_f);
 	    }
 
 	  {
@@ -1135,7 +1196,7 @@
     {
       propagate_block (basic_block_live_at_end[i],
 		       basic_block_head[i], basic_block_end[i], 1,
-		       (regset) 0, i);
+		       (regset) 0, i/* intel2: */, change_f);
 #ifdef USE_C_ALLOCA
       alloca (0);
 #endif
@@ -1232,7 +1293,7 @@
    SPACE is of type regset, but it is really as long as NELTS regsets.
    BYTES_PER_ELT is the number of bytes in one regset.  */
 
-static void
+/* intel2 static */ void
 init_regset_vector (vector, space, nelts, bytes_per_elt)
      regset *vector;
      regset space;
@@ -1269,13 +1330,13 @@
    BNUM is the number of the basic block.  */
 
 static void
-propagate_block (old, first, last, final, significant, bnum)
+propagate_block (old, first, last, final, significant, bnum /* intel2: */, change_f)
      register regset old;
      rtx first;
      rtx last;
      int final;
      regset significant;
-     int bnum;
+     int bnum /* intel2: */, change_f;
 {
   register rtx insn;
   rtx prev;
@@ -1319,7 +1380,7 @@
 	loop_depth--;
     }
 
-  if (final)
+  if (final /* intel2: */ && change_f)
     {
       register int i, offset;
       REGSET_ELT_TYPE bit;
@@ -1402,7 +1463,7 @@
 	     "delete" it by turning it into a NOTE of type NOTE_INSN_DELETED.
 	     We could really delete it with delete_insn, but that
 	     can cause trouble for first or last insn in a basic block.  */
-	  if (final && insn_is_dead)
+	  if (final /* intel2: */ && change_f && insn_is_dead)
 	    {
 	      PUT_CODE (insn, NOTE);
 	      NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
@@ -1444,7 +1505,7 @@
 	  {
 	    register rtx x = PATTERN (insn);
 	    /* Does this instruction increment or decrement a register?  */
-	    if (final && GET_CODE (x) == SET
+	    if (final /* intel2: */ && change_f && GET_CODE (x) == SET
 		&& GET_CODE (SET_DEST (x)) == REG
 		&& (GET_CODE (SET_SRC (x)) == PLUS
 		    || GET_CODE (SET_SRC (x)) == MINUS)
@@ -1488,7 +1549,7 @@
 		 live.  */
 
 	      mark_set_regs (old, dead, PATTERN (insn),
-			     final ? insn : NULL_RTX, significant);
+			     (final /* intel2: */ && change_f) ? insn : NULL_RTX, significant);
 
 	      /* If an insn doesn't use CC0, it becomes dead since we 
 		 assume that every insn clobbers it.  So show it dead here;
@@ -1552,7 +1613,7 @@
 		  old[i] |= live[i];
 		}
 
-	      if (GET_CODE (insn) == CALL_INSN && final)
+	      if (GET_CODE (insn) == CALL_INSN && final /* intel2: */ && change_f)
 		{
 		  /* Any regs live at the time of a call instruction
 		     must not go in a register clobbered by calls.
@@ -1570,7 +1631,7 @@
 	     into MAXLIVE and REGS_SOMETIMES_LIVE.
 	     Also update counts of how many insns each reg is live at.  */
 
-	  if (final)
+	  if (final /* intel2: */ && change_f)
 	    {
 	      for (i = 0; i < regset_size; i++)
 		{
@@ -2776,6 +2837,11 @@
 {
   register int i;
   static char *reg_class_names[] = REG_CLASS_NAMES;
+  /* intel1 */
+#ifdef SPARE_REGS
+  int max_regno;
+  max_regno = max_reg_num();
+#endif
 
   fprintf (file, "%d registers.\n", max_regno);
 
@@ -2852,3 +2918,594 @@
     }
   fprintf (file, "\n");
 }
+
+/* intel1 */
+/* Information about registers */
+struct regopt_info
+{
+  rtx insn_set;			/* If non NULL then the insn that loads the register
+                          with it's current value */
+  int num_uses_copied;		/* To count if the reg setter has been copied to
+                          each of the uses */
+  char copied_for_src;          /* Set per insn if the insn_set has been copied
+                          as a result of analysis on the src */
+};
+static struct regopt_info *rinfo;
+
+/* Count the number of new sets of the register */
+static int *my_reg_n_sets;
+
+/* Count the number of times a register is used in an insn */
+static int *regs_in_body;
+
+/* Count the number of times a register is used in a function */
+static int *reg_n_uses;
+
+/* Copied from sched.c
+   Return the INSN_LIST containing INSN in LIST, or NULL
+   if LIST does not contain INSN.  */
+#ifndef __GNUC__
+#define __inline
+#endif
+
+__inline static rtx
+find_insn_list (insn, list)
+     rtx insn;
+     rtx list;
+{
+  while (list)
+    {
+      if (XEXP (list, 0) == insn)
+	return list;
+      list = XEXP (list, 1);
+    }
+  return 0;
+}
+
+/*
+  Sometimes cse is done where it is detremental. Consider register 23
+  in the following insn stream:
+
+(insn 18 65 82 (set (reg/v:SI 23)
+        (plus:SI (reg/v:SI 22)
+            (const_int -4501))) 32 {movsi+1} (nil)
+    (nil))
+
+(insn 82 18 83 (set (cc0)
+        (compare:CC (reg/v:SI 22)
+            (const_int 4500))) 6 {cmpsi_cc} (nil)
+    (nil))
+
+(jump_insn 83 82 90 (set (pc)
+        (if_then_else (gt (cc0)
+                (const_int 0))
+            (label_ref 63)
+            (pc))) 185 {bgt+1} (nil)
+    (nil))
+
+(note 90 83 91 "" NOTE_INSN_DELETED)
+
+(insn 91 90 93 (set (reg:SI 32)
+        (ashift:SI (reg/v:SI 23)
+            (const_int 2))) 136 {ashlsi3} (nil)
+    (expr_list:REG_DEAD (reg/v:SI 23)
+        (nil)))
+
+  reg 23 appears in insn 91 as a result of cse, before cse insn 90
+  and 91 were:
+
+(insn 90 83 91 (set (reg:SI 33)
+        (plus:SI (reg/v:SI 22)
+            (const_int -4501))) -1 (nil)
+    (nil))
+
+(insn 91 90 93 (set (reg:SI 34)
+        (ashift:SI (reg:SI 33)
+            (const_int 2))) -1 (nil)
+    (nil))
+
+  since reg 23 does not appear anywhere else in the rtl and it is dead
+  at insn 91 it would be better to move insn 18 to after insn 90, thus
+  allowing the combiner to combine insn 18 into 91.
+
+*/
+static void
+correct_cse_mistakes (f, cur_max_reg, dump_file)
+     rtx f;
+     int cur_max_reg;
+     FILE *dump_file;
+{
+  rtx insn, src, dest, insn_set, note;
+  struct regs_mentioned *header, *a_reg_used;
+  int num_regs, recog_ok, i, regno;
+  char *storage1, *storage2;
+
+  rinfo =
+    (struct regopt_info *) alloca ((cur_max_reg) * sizeof (struct regopt_info));
+  bzero (rinfo, (cur_max_reg) * sizeof (struct regopt_info));
+  reg_n_uses = (int *) alloca ((cur_max_reg) * sizeof (int));
+  bzero (reg_n_uses, (cur_max_reg) * sizeof (int));
+  regs_in_body = (int *) alloca ((cur_max_reg) * sizeof (int));
+  bzero (regs_in_body, (cur_max_reg) * sizeof (int));
+  my_reg_n_sets = (int *) alloca ((cur_max_reg) * sizeof (int));
+  bzero (my_reg_n_sets, (cur_max_reg) * sizeof (int));
+
+  if (dump_file)
+    fprintf (dump_file, "\ndoing correct_cse_mistakes:\n\n");
+  insn = f;
+  while (insn)
+    {
+      if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
+	  || GET_CODE (insn) == CALL_INSN)
+	{
+	  count_reg_uses (PATTERN (insn), reg_n_uses);
+	}
+      insn = NEXT_INSN (insn);
+    }
+  insn = f;
+  while (insn)
+    {
+      switch (GET_CODE (insn))
+	{
+
+	case CALL_INSN:
+	  /* Don't want to change reg_n_calls_crosses */
+	  bzero (rinfo, cur_max_reg * sizeof (struct regopt_info));
+	  break;
+
+	case CODE_LABEL:
+	case BARRIER:
+	  /* forget everything */
+	  bzero (rinfo, cur_max_reg * sizeof (struct regopt_info));
+	  break;
+
+	case INSN:
+          if (GET_CODE (PATTERN (insn)) == CLOBBER)
+            {
+	      if (GET_CODE (SET_DEST (PATTERN (insn))) == REG)
+		{
+		  rinfo[ REGNO (SET_DEST (PATTERN (insn)))].insn_set = NULL;
+		  for (i = 0; i < cur_max_reg; i++)
+		    {
+		      if (rinfo[i].insn_set
+			  && reg_overlap_mentioned_p (SET_DEST (PATTERN (insn)), 
+			        SET_SRC (PATTERN (rinfo[i].insn_set)))
+			)
+			{	/* current value of reg dest overwritten */
+			  rinfo[i].insn_set = NULL;
+			}
+		    }
+		}
+            }
+	  else if (GET_CODE (PATTERN (insn)) == PARALLEL)
+	    {
+	      for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
+		{
+		  rtx cur_rtx;
+		  cur_rtx = XVECEXP (PATTERN (insn), 0, i);
+		  if ((GET_CODE (cur_rtx) == SET  
+		       || GET_CODE (cur_rtx) == CLOBBER)
+		      && GET_CODE (SET_DEST (cur_rtx)) == REG)
+		    {
+		      rinfo[ REGNO (SET_DEST (cur_rtx))].insn_set = NULL;
+		      for (i = 0; i < cur_max_reg; i++)
+		        {
+		          if (rinfo[i].insn_set
+			      && reg_overlap_mentioned_p (SET_DEST (cur_rtx), 
+			             SET_SRC (PATTERN (rinfo[i].insn_set)))
+			    )
+			    {	/* current value of reg dest overwritten */
+			      rinfo[i].insn_set = NULL;
+			    }
+		        }
+		    }
+		  if (!(GET_CODE (cur_rtx) == SET  
+		       || GET_CODE (cur_rtx) == CLOBBER
+		       || GET_CODE (cur_rtx) == USE))
+	            bzero (rinfo, cur_max_reg * sizeof (struct regopt_info));
+		}
+	    }
+	  else if (GET_CODE (PATTERN (insn)) == SET)
+	    {
+	      dest = SET_DEST (PATTERN (insn));
+	      src = SET_SRC (PATTERN (insn));
+	      if (GET_CODE (src) == REG)
+		{
+		  i = REGNO (src);
+                  if (rinfo[i].insn_set
+                      && BLOCK_NUM (insn) == BLOCK_NUM (rinfo[i].insn_set))
+                    { /* Since insn_set cannot be deleted stop optimization */
+                      rinfo[i].insn_set = NULL;
+                    }
+                }
+	      else /* (GET_CODE (src) != REG) */
+		{
+	          count_reg_uses (src, regs_in_body);
+		  for (i = 0; i < cur_max_reg; i++)
+		    {
+                      if (rinfo[i].insn_set
+                          && regs_in_body[i]
+                          && BLOCK_NUM (insn) == BLOCK_NUM (rinfo[i].insn_set))
+                        { /* Since insn_set cannot be deleted stop optimization */
+                          rinfo[i].insn_set = NULL;
+                        }
+		      if (reg_n_sets[i] == 1
+		          && regs_in_body[i]
+			  && rinfo[i].insn_set
+			  && GET_CODE (rinfo[i].insn_set) == INSN)
+			{	
+			  if (find_regno_note (insn, REG_DEAD, i))
+			    {
+			      /* copy insn_set just prior to insn */
+			      do_correction (i, insn, dump_file);
+			    }
+			  else
+			    { /* A use that is not dead - stop.  */
+                              rinfo[i].insn_set = NULL;
+			    }
+			}
+		    }
+		  bzero (regs_in_body, cur_max_reg * sizeof (int));
+		}
+	      if (GET_CODE (dest) != REG)
+		{
+		  count_reg_uses (dest, regs_in_body);
+		  for (i = 0; i < cur_max_reg; i++)
+		    {
+                      if (rinfo[i].insn_set
+                          && regs_in_body[i]
+                          && BLOCK_NUM (insn) == BLOCK_NUM (rinfo[i].insn_set))
+                        { /* Since insn_set cannot be deleted stop optimization */
+                          rinfo[i].insn_set = NULL;
+                        }
+		      if (reg_n_sets[i] == 1
+		          && !rinfo[i].copied_for_src
+		          && regs_in_body[i]
+			  && rinfo[i].insn_set
+			  && GET_CODE (rinfo[i].insn_set) == INSN)
+			{
+			  if (find_regno_note (insn, REG_DEAD, i))
+			    {
+			      /* copy insn_set just prior to insn */
+			      do_correction (i, insn, dump_file);
+			    }
+			  else
+			    { /* A use that is not dead - stop.  */
+                              rinfo[i].insn_set = NULL;
+			    }
+
+			}
+		    }
+		  bzero (regs_in_body, cur_max_reg * sizeof (int));
+		}
+	      for (i = 0; i < cur_max_reg; i++)
+		{
+		  rinfo[i].copied_for_src = 0;
+		}
+	      if (GET_CODE (dest) == REG)
+		{
+		  for (i = 0; i < cur_max_reg; i++)
+		    {
+		      if (rinfo[i].insn_set
+			  && reg_overlap_mentioned_p (dest, SET_SRC (PATTERN (rinfo[i].insn_set)))
+			)
+			{	/* current value of reg dest overwritten */
+			  rinfo[i].insn_set = NULL;
+			}
+		    }
+		  if (reg_overlap_mentioned_p (dest, SET_SRC (PATTERN (insn))))
+		    {
+		      rinfo[REGNO (dest)].insn_set = NULL;
+		    }
+		  else
+		    {
+		      if ((GET_CODE (SET_SRC (PATTERN (insn))) == ASHIFT
+		           && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == REG
+			   && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == CONST_INT)
+			  || (GET_CODE (SET_SRC (PATTERN (insn))) == PLUS
+		              && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == REG
+			      && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == SYMBOL_REF)
+			  || (GET_CODE (SET_SRC (PATTERN (insn))) == PLUS
+			      && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == MULT
+			      && GET_CODE (XEXP (XEXP (SET_SRC (PATTERN (insn)), 0), 0)) == REG
+			      && GET_CODE (XEXP (XEXP (SET_SRC (PATTERN (insn)), 0), 1)) == CONST_INT
+			      && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == CONST_INT)
+			  || (GET_CODE (SET_SRC (PATTERN (insn))) == PLUS
+		              && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == REG
+			      && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == CONST_INT)
+			)
+			{	/* these may be combinable */
+			  if (REG_NOTES (insn) == NULL)
+			    { /* Don't want to mess around with
+			         the REG_NOTES.  */
+			      rinfo[REGNO (dest)].insn_set = insn;
+			    }
+			}
+		      else
+			{
+			  rinfo[REGNO (dest)].insn_set = NULL;
+			}
+		    }
+		}
+	    }
+	  else if (GET_CODE (PATTERN (insn)) == USE)
+	    ; /* nothing */
+	  else 
+	    {
+	      bzero (rinfo, cur_max_reg * sizeof (struct regopt_info));
+	    }
+	  /* A register that dies cannot be used further in a substitution.  */
+          for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
+	    if (REG_NOTE_KIND (note) == REG_DEAD
+		&& GET_CODE (XEXP (note, 0)) == REG)
+	      {
+		for (i = 0; i < cur_max_reg; i++)
+		  {
+		    if (rinfo[i].insn_set
+			&& reg_overlap_mentioned_p (XEXP (note, 0), 
+			      SET_SRC (PATTERN (rinfo[i].insn_set)))
+		       )
+		      {	
+			  rinfo[i].insn_set = NULL;
+	              }
+		  }    
+	      }
+
+	  break;
+
+	case JUMP_INSN:
+	case NOTE:
+	  break;
+
+	default:
+	  bzero (rinfo, cur_max_reg * sizeof (struct regopt_info));
+	  break;
+	}
+      insn = NEXT_INSN (insn);
+    }
+  for (i = 0; i < cur_max_reg; i++)
+    reg_n_sets[i] += my_reg_n_sets[i];
+}
+
+/*
+  Increment the reg_n_uses element for each register mentioned in body
+  and for each time it is mentioned
+*/
+static void
+count_reg_uses (body, where_to_count)
+     rtx body;
+     int *where_to_count;
+{
+  int i, j, ret_val = 0;
+  char *fmt;
+  register RTX_CODE code = GET_CODE (body);
+
+  if (code == CLOBBER)
+    return;
+  else if (code == REG)
+    where_to_count[REGNO (body)]++;
+  else if (code == SET)
+    {
+      if (GET_CODE (SET_DEST (body)) != REG)
+	{
+	  count_reg_uses (SET_DEST (body), where_to_count);
+	}
+      count_reg_uses (SET_SRC (body), where_to_count);
+    }
+  else
+    {
+      fmt = GET_RTX_FORMAT (code);
+      for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+	if (fmt[i] == 'e')
+	  count_reg_uses (XEXP (body, i), where_to_count);
+	else if (fmt[i] == 'E' || fmt[i] == 'V')
+	  {
+	    for (j = 0; j < XVECLEN (body, i); j++)
+	      count_reg_uses (XVECEXP (body, i, j), where_to_count);
+	  }
+    }
+}
+
+/*
+   Copy the insn that sets regnum to just before insn.
+   If that insn has been copied to in front of each of
+   it's uses then delete it
+*/
+static void
+do_correction (regnum, insn, dump_file)
+     int regnum;
+     rtx insn;
+     FILE * dump_file;
+{
+  rtx insn_set;
+  int i;
+  
+  insn_set
+    = rinfo[regnum].insn_set;
+  if (BLOCK_NUM (insn) == BLOCK_NUM (insn_set))
+    { /* Since insn_set cannot be deleted stop optimization */
+      rinfo[regnum].insn_set = NULL;
+      return;
+    }
+  emit_insn_before (
+		     copy_rtx (PATTERN (insn_set)),
+		     insn);
+   
+  if (REG_NOTES (insn_set))
+    {
+      REG_NOTES (PREV_INSN (insn))
+	= copy_rtx (REG_NOTES (insn_set));
+    }
+  LOG_LINKS (insn)
+    = gen_rtx (INSN_LIST, VOIDmode, PREV_INSN (insn),
+	       LOG_LINKS (insn));
+  if (find_insn_list (insn_set,
+		      LOG_LINKS (insn)))
+    remove_dependence (insn, insn_set);
+  rinfo[regnum].num_uses_copied += regs_in_body[regnum];
+  my_reg_n_sets[regnum]++;
+  if (dump_file)
+    {
+      fprintf (dump_file,
+	       " copy insn %d to before insn %d\n",
+	       INSN_UID (insn_set), INSN_UID (insn));
+    }
+  if (rinfo[regnum].num_uses_copied == reg_n_uses[regnum])
+    {	/* insn_set is no longer relevant - delete it */
+      rinfo[regnum].insn_set = NULL;
+      PUT_CODE (insn_set, NOTE);
+      NOTE_LINE_NUMBER (insn_set) = NOTE_INSN_DELETED;
+      NOTE_SOURCE_FILE (insn_set) = 0;
+      if (dump_file)
+	{
+	  fprintf (dump_file,
+		   " delete insn %d \n",
+		   INSN_UID (insn_set));
+	}
+      reg_n_sets[regnum]--;
+    }
+  /* If insn was a basic block head then now the copy is
+     the basic block head.  */
+  for (i = 0; i < n_basic_blocks; i++)
+    {
+      if (basic_block_head[i] == insn)
+        {
+          basic_block_head[i] = PREV_INSN (insn);
+          break;
+        }
+    }
+  
+}
+
+/* intel2 */
+/* Call flow_analysis without changing insns, and if save_pseudo is set, saves
+   the basic_block_live_at_start information, concerning the pseudo registers,
+   and restores it after flow_analysis. */
+
+void
+hard_reg_flow_analysis (f, file, save_pseudo)
+     rtx f;
+     FILE *file;
+     int save_pseudo;
+{
+  int limit;
+  register int block, regno;
+
+  /* Element N is a regset describing the registers live
+     at the start of basic block N, as was saved before the call to
+     flow_analysis. We use it to restore the contents of the pseudo registers,
+     needed by other phases. */
+    
+  regset *basic_block_live_at_start_saved;
+    
+#if 0
+  register int j;
+#endif
+
+  if (save_pseudo)
+    {
+      int regset_size = ((max_regno + REGSET_ELT_BITS - 1) / REGSET_ELT_BITS);
+      int regset_bytes = regset_size * sizeof (*(regset)0);
+      basic_block_live_at_start_saved =
+  			   (regset *) alloca (n_basic_blocks * sizeof (regset));
+      /* copy basic_block_live_at_start to basic_block_live_at_start_saved */
+      for (block = 0; block < n_basic_blocks; block++)
+        {
+          basic_block_live_at_start_saved[block] = (regset) alloca (regset_bytes);
+          bcopy (basic_block_live_at_start[block],
+    	         basic_block_live_at_start_saved[block],
+    	         regset_bytes);
+        }
+
+#if 0
+      /* Check if copy is o.k. */
+      if (file)
+        {
+          fprintf (file, "Pseudo registers live at start:\n");
+
+          for (block = 0; block < n_basic_blocks; block++)
+	    {
+	      fprintf (file, "\nBlock no. %d original:", block);
+
+	      for (regno = FIRST_PSEUDO_REGISTER; regno < max_regno; regno++)
+	        {
+	          register int offset = regno / REGSET_ELT_BITS;
+	          register REGSET_ELT_TYPE bit
+	      		     = (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS);
+	          if ((basic_block_live_at_start_saved[block][offset] & bit)
+	              ^ (basic_block_live_at_start[block][offset] & bit))
+	            {
+		      fprintf (file, "\nERROR: differnt values in regsets!\n");
+		      fprintf (file,
+			       "original: %d, saved: %d\n",
+			       basic_block_live_at_start[block][offset],
+			       basic_block_live_at_start_saved[block][offset]);
+	              abort ();
+	            }
+	          if (basic_block_live_at_start[block][offset] & bit)
+	            fprintf (file, " %d", regno);
+	        }
+	      fprintf (file, "\nSaved:");
+	      for (regno = FIRST_PSEUDO_REGISTER; regno < max_regno; regno++)
+	        {
+	          register int offset = regno / REGSET_ELT_BITS;
+	          register REGSET_ELT_TYPE bit
+	      		     = (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS);
+
+	          if (basic_block_live_at_start_saved[block][offset] & bit)
+	            fprintf (file, " %d", regno);
+	        }
+	      fprintf (file, "\n");
+            }  /* for (block = 0; block < n_basic_blocks; block++) */
+        }  /* if (file) */
+#endif
+    }  /* if (save_pseudo) */
+
+  limit = max_reg_num ();
+
+  /* Do control and data flow analysis, and write the results to the dump
+   * file, if dump wanted.
+   */
+  flow_analysis (f, limit, file, 0 /* do not allow a change to the insns */ );
+
+  if (save_pseudo)
+    {
+      /* restore the contents of pseudo registers if basic_block_live_at_start */
+      for (block = 0; block < n_basic_blocks; block++)
+        {
+          for (regno = FIRST_PSEUDO_REGISTER; regno < max_regno; regno++)
+            {
+              register int offset = regno / REGSET_ELT_BITS;
+              register REGSET_ELT_TYPE bit
+	      		     = (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS);
+
+	      if (basic_block_live_at_start_saved[block][offset] & bit)
+	        basic_block_live_at_start[block][offset] |= bit;
+	      else
+	        basic_block_live_at_start[block][offset] &= ~bit;
+            }
+        }
+
+#if 0
+      /* Check if copy is o.k. */
+      if (file)
+        {
+          fprintf (file, "Pseudo registers live at start - restored :\n");
+
+          for (block = 0; block < n_basic_blocks; block++)
+	    {
+	      fprintf (file, "Block no. %d:", block);
+	      for (regno = FIRST_PSEUDO_REGISTER; regno < max_regno; regno++)
+	        {
+	          register int offset = regno / REGSET_ELT_BITS;
+	          register REGSET_ELT_TYPE bit
+	      		     = (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS);
+	          if (basic_block_live_at_start[block][offset] & bit)
+	            fprintf (file, " %d", regno);
+	        }
+	      fprintf (file, "\n");
+            }
+        }
+#endif
+    }  /* if (save_pseudo) */
+}  /* hard_reg_flow_analysis (f, file, save_pseudo) */
diff -r -u -H -N gcc-2.6.3/fold-const.c gcc-i2.6.3/fold-const.c
--- gcc-2.6.3/fold-const.c	Wed Nov 30 19:03:17 1994
+++ gcc-i2.6.3/fold-const.c	Wed Feb 15 23:25:35 1995
@@ -3547,7 +3547,12 @@
 	return fold (build (MINUS_EXPR, type, arg0, TREE_OPERAND (arg1, 0)));
       else if (! FLOAT_TYPE_P (type))
 	{
-	  if (integer_zerop (arg1))
+	  if (integer_zerop (arg1)
+	      /* intel1 if it is pointer_type then removing the + 0 here
+	         will cause references to array[0] not to be marked
+	         as MEM_IN_STRUCT_P.  So just leave the + 0 here - it
+	         will be removed when the tree is made into rtl anyway.  */
+	      && TREE_CODE (TREE_TYPE (arg0)) != POINTER_TYPE)
 	    return non_lvalue (convert (type, arg0));
 
 	  /* If we are adding two BIT_AND_EXPR's, both of which are and'ing
@@ -3914,6 +3919,31 @@
     case FLOOR_DIV_EXPR:
     case CEIL_DIV_EXPR:
     case EXACT_DIV_EXPR:
+   /* intel1 - implemet x/C where c is floating point and a power of two
+              as x*(1/C)
+   */
+#ifndef REAL_IS_NOT_DOUBLE
+      if (HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
+         && TREE_CODE (t) == RDIV_EXPR
+         && TREE_CODE (TREE_TYPE (t)) == REAL_TYPE
+         && TYPE_NAME (TREE_TYPE (t))
+         && TREE_CODE (TYPE_NAME TREE_TYPE (t)) == TYPE_DECL
+         && TREE_CODE (TREE_OPERAND (t,  1)) == REAL_CST
+         && TREE_CODE (TREE_TYPE (TREE_OPERAND (t, 1))) == REAL_TYPE
+         && TYPE_NAME (TREE_TYPE (TREE_OPERAND (t, 1)))
+         && TREE_CODE (TYPE_NAME (TREE_TYPE (TREE_OPERAND(t, 1))))== TYPE_DE CL
+         && TREE_REAL_CST (TREE_OPERAND (t, 1)) >= 2.0
+         && TREE_REAL_CST (TREE_OPERAND (t, 1))
+          ==(double)(REAL_VALUE_UNSIGNED_FIX(TREE_REAL_CST(TREE_OPERAND(t, 1))))
+          &&exact_log2(REAL_VALUE_UNSIGNED_FIX(TREE_REAL_CST(TREE_OPERAND(t,1)))) != -1
+         )
+        {
+          TREE_SET_CODE (t, MULT_EXPR);
+          code = TREE_CODE (t);
+          TREE_REAL_CST (TREE_OPERAND (t, 1))
+            = 1.0 / TREE_REAL_CST (TREE_OPERAND (t, 1));
+        }
+#endif
       if (integer_onep (arg1))
 	return non_lvalue (convert (type, arg0));
       if (integer_zerop (arg1))
diff -r -u -H -N gcc-2.6.3/gcc.aux gcc-i2.6.3/gcc.aux
--- gcc-2.6.3/gcc.aux	Fri Nov 11 18:51:12 1994
+++ gcc-i2.6.3/gcc.aux	Thu Jul 14 22:14:35 1994
@@ -4,678 +4,672 @@
 'xrdef {Contributors-title}{Contributors to GNU CC}
 'xrdef {Contributors-pg}{9}
 'xrdef {Contributors-snt}{}
-'xrdef {Funding-title}{Funding Free Software}
-'xrdef {Funding-pg}{11}
-'xrdef {Funding-snt}{Chapter'tie1}
 'xrdef {Look and Feel-title}{Protect Your Freedom---Fight ``Look And Feel''}
-'xrdef {Look and Feel-pg}{13}
-'xrdef {Look and Feel-snt}{Chapter'tie2}
+'xrdef {Look and Feel-pg}{11}
+'xrdef {Look and Feel-snt}{Chapter'tie1}
 'xrdef {G++ and GCC-title}{Compile C, C++, or Objective C}
-'xrdef {G++ and GCC-pg}{17}
-'xrdef {G++ and GCC-snt}{Chapter'tie3}
+'xrdef {G++ and GCC-pg}{15}
+'xrdef {G++ and GCC-snt}{Chapter'tie2}
 'xrdef {Invoking GCC-title}{GNU CC Command Options}
-'xrdef {Invoking GCC-pg}{19}
-'xrdef {Invoking GCC-snt}{Chapter'tie4}
+'xrdef {Invoking GCC-pg}{17}
+'xrdef {Invoking GCC-snt}{Chapter'tie3}
 'xrdef {Option Summary-title}{Option Summary}
-'xrdef {Option Summary-pg}{19}
-'xrdef {Option Summary-snt}{Section'tie4.1}
+'xrdef {Option Summary-pg}{17}
+'xrdef {Option Summary-snt}{Section'tie3.1}
 'xrdef {Overall Options-title}{Options Controlling the Kind of Output}
-'xrdef {Overall Options-pg}{24}
-'xrdef {Overall Options-snt}{Section'tie4.2}
+'xrdef {Overall Options-pg}{22}
+'xrdef {Overall Options-snt}{Section'tie3.2}
 'xrdef {Invoking G++-title}{Compiling C++ Programs}
-'xrdef {Invoking G++-pg}{26}
-'xrdef {Invoking G++-snt}{Section'tie4.3}
+'xrdef {Invoking G++-pg}{24}
+'xrdef {Invoking G++-snt}{Section'tie3.3}
 'xrdef {C Dialect Options-title}{Options Controlling C Dialect}
-'xrdef {C Dialect Options-pg}{27}
-'xrdef {C Dialect Options-snt}{Section'tie4.4}
+'xrdef {C Dialect Options-pg}{25}
+'xrdef {C Dialect Options-snt}{Section'tie3.4}
 'xrdef {C++ Dialect Options-title}{Options Controlling C++ Dialect}
-'xrdef {C++ Dialect Options-pg}{30}
-'xrdef {C++ Dialect Options-snt}{Section'tie4.5}
+'xrdef {C++ Dialect Options-pg}{28}
+'xrdef {C++ Dialect Options-snt}{Section'tie3.5}
 'xrdef {Warning Options-title}{Options to Request or Suppress Warnings}
-'xrdef {Warning Options-pg}{34}
-'xrdef {Warning Options-snt}{Section'tie4.6}
+'xrdef {Warning Options-pg}{32}
+'xrdef {Warning Options-snt}{Section'tie3.6}
 'xrdef {Debugging Options-title}{Options for Debugging Your Program or GNU CC}
-'xrdef {Debugging Options-pg}{41}
-'xrdef {Debugging Options-snt}{Section'tie4.7}
+'xrdef {Debugging Options-pg}{37}
+'xrdef {Debugging Options-snt}{Section'tie3.7}
 'xrdef {Optimize Options-title}{Options That Control Optimization}
-'xrdef {Optimize Options-pg}{44}
-'xrdef {Optimize Options-snt}{Section'tie4.8}
+'xrdef {Optimize Options-pg}{41}
+'xrdef {Optimize Options-snt}{Section'tie3.8}
 'xrdef {Preprocessor Options-title}{Options Controlling the Preprocessor}
-'xrdef {Preprocessor Options-pg}{48}
-'xrdef {Preprocessor Options-snt}{Section'tie4.9}
+'xrdef {Preprocessor Options-pg}{45}
+'xrdef {Preprocessor Options-snt}{Section'tie3.9}
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-'xrdef {Assembler Options-pg}{51}
-'xrdef {Assembler Options-snt}{Section'tie4.10}
+'xrdef {Assembler Options-pg}{48}
+'xrdef {Assembler Options-snt}{Section'tie3.10}
 'xrdef {Link Options-title}{Options for Linking}
-'xrdef {Link Options-pg}{51}
-'xrdef {Link Options-snt}{Section'tie4.11}
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+'xrdef {Link Options-snt}{Section'tie3.11}
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-'xrdef {Directory Options-pg}{53}
-'xrdef {Directory Options-snt}{Section'tie4.12}
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+'xrdef {Directory Options-snt}{Section'tie3.12}
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-'xrdef {Target Options-pg}{54}
-'xrdef {Target Options-snt}{Section'tie4.13}
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+'xrdef {Target Options-snt}{Section'tie3.13}
 'xrdef {Submodel Options-title}{Hardware Models and Configurations}
-'xrdef {Submodel Options-pg}{56}
-'xrdef {Submodel Options-snt}{Section'tie4.14}
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+'xrdef {Submodel Options-snt}{Section'tie3.14}
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-'xrdef {M680x0 Options-pg}{56}
-'xrdef {M680x0 Options-snt}{Section'tie4.14.1}
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+'xrdef {M680x0 Options-snt}{Section'tie3.14.1}
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-'xrdef {VAX Options-pg}{57}
-'xrdef {VAX Options-snt}{Section'tie4.14.2}
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+'xrdef {VAX Options-snt}{Section'tie3.14.2}
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-'xrdef {SPARC Options-pg}{58}
-'xrdef {SPARC Options-snt}{Section'tie4.14.3}
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-'xrdef {Convex Options-pg}{60}
-'xrdef {Convex Options-snt}{Section'tie4.14.4}
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-'xrdef {AMD29K Options-pg}{61}
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-'xrdef {ARM Options-pg}{63}
-'xrdef {ARM Options-snt}{Section'tie4.14.6}
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+'xrdef {ARM Options-snt}{Section'tie3.14.6}
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-'xrdef {M88K Options-pg}{63}
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-'xrdef {RT Options-snt}{Section'tie4.14.9}
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-'xrdef {MIPS Options-pg}{70}
-'xrdef {MIPS Options-snt}{Section'tie4.14.10}
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-'xrdef {i386 Options-pg}{73}
-'xrdef {i386 Options-snt}{Section'tie4.14.11}
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-'xrdef {HPPA Options-pg}{74}
-'xrdef {HPPA Options-snt}{Section'tie4.14.12}
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-'xrdef {Intel 960 Options-pg}{75}
-'xrdef {Intel 960 Options-snt}{Section'tie4.14.13}
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-'xrdef {DEC Alpha Options-snt}{Section'tie4.14.14}
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+'xrdef {DEC Alpha Options-snt}{Section'tie3.14.14}
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-'xrdef {Clipper Options-pg}{77}
-'xrdef {Clipper Options-snt}{Section'tie4.14.15}
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-'xrdef {H8/300 Options-pg}{77}
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-'xrdef {System V Options-snt}{Section'tie4.14.17}
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-'xrdef {Code Gen Options-pg}{78}
-'xrdef {Code Gen Options-snt}{Section'tie4.15}
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+'xrdef {Code Gen Options-snt}{Section'tie3.15}
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-'xrdef {Environment Variables-pg}{81}
-'xrdef {Environment Variables-snt}{Section'tie4.16}
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-'xrdef {Installation-snt}{Chapter'tie5}
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-'xrdef {Configurations-pg}{93}
-'xrdef {Configurations-snt}{Section'tie5.1}
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-'xrdef {Other Dir-pg}{106}
-'xrdef {Other Dir-snt}{Section'tie5.2}
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-'xrdef {Cross-Compiler-pg}{106}
-'xrdef {Cross-Compiler-snt}{Section'tie5.3}
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-'xrdef {Sun Install-pg}{112}
-'xrdef {Sun Install-snt}{Section'tie5.4}
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-'xrdef {VMS Install-pg}{113}
-'xrdef {VMS Install-snt}{Section'tie5.5}
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-'xrdef {Complex-pg}{129}
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-'xrdef {Min and Max-snt}{Section'tie7.2}
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-'xrdef {Destructors and Goto-snt}{Section'tie7.3}
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-'xrdef {Template Instantiation-pg}{164}
-'xrdef {Template Instantiation-snt}{Section'tie7.5}
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-'xrdef {Trouble-snt}{Chapter'tie8}
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-'xrdef {Installation Problems-snt}{Section'tie8.2}
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-'xrdef {Cross-Compiler Problems-snt}{Section'tie8.3}
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+'xrdef {Cross-Compiler Problems-snt}{Section'tie7.3}
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-'xrdef {Interoperation-pg}{175}
-'xrdef {Interoperation-snt}{Section'tie8.4}
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+'xrdef {Interoperation-snt}{Section'tie7.4}
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-'xrdef {External Bugs-pg}{179}
-'xrdef {External Bugs-snt}{Section'tie8.5}
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+'xrdef {External Bugs-snt}{Section'tie7.5}
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-'xrdef {Incompatibilities-pg}{180}
-'xrdef {Incompatibilities-snt}{Section'tie8.6}
+'xrdef {Incompatibilities-pg}{174}
+'xrdef {Incompatibilities-snt}{Section'tie7.6}
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-'xrdef {Fixed Headers-snt}{Section'tie8.7}
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-'xrdef {Disappointments-snt}{Section'tie8.8}
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-'xrdef {C++ Misunderstandings-pg}{185}
-'xrdef {C++ Misunderstandings-snt}{Section'tie8.9}
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-'xrdef {Static Definitions-snt}{Section'tie8.9.1}
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-'xrdef {Protoize Caveats-snt}{Section'tie8.10}
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-'xrdef {Non-bugs-snt}{Section'tie8.11}
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-'xrdef {Bugs-snt}{Chapter'tie9}
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-'xrdef {Bug Criteria-snt}{Section'tie9.1}
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-'xrdef {Bug Lists-snt}{Section'tie9.2}
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-'xrdef {Bug Reporting-snt}{Section'tie9.3}
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-'xrdef {Sending Patches-pg}{199}
-'xrdef {Sending Patches-snt}{Section'tie9.4}
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-'xrdef {Service-pg}{203}
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-'xrdef {VMS-pg}{205}
-'xrdef {VMS-snt}{Chapter'tie11}
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-'xrdef {Include Files and VMS-snt}{Section'tie11.1}
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-'xrdef {VMS Misc-pg}{209}
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-'xrdef {Portability-pg}{211}
-'xrdef {Portability-snt}{Chapter'tie12}
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-'xrdef {Interface-snt}{Chapter'tie13}
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-'xrdef {Passes-snt}{Chapter'tie14}
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-'xrdef {RTL-snt}{Chapter'tie15}
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-'xrdef {Accessors-snt}{Section'tie15.2}
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-'xrdef {Flags-snt}{Section'tie15.3}
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-'xrdef {Machine Modes-snt}{Section'tie15.4}
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-'xrdef {Constants-snt}{Section'tie15.5}
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-'xrdef {Regs and Memory-pg}{234}
-'xrdef {Regs and Memory-snt}{Section'tie15.6}
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-'xrdef {Arithmetic-pg}{238}
-'xrdef {Arithmetic-snt}{Section'tie15.7}
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-'xrdef {Comparisons-pg}{241}
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-'xrdef {Bit Fields-snt}{Section'tie15.9}
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-'xrdef {Conversions-pg}{243}
-'xrdef {Conversions-snt}{Section'tie15.10}
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-'xrdef {RTL Declarations-snt}{Section'tie15.11}
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-'xrdef {Side Effects-pg}{245}
-'xrdef {Side Effects-snt}{Section'tie15.12}
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-'xrdef {Incdec-pg}{249}
-'xrdef {Incdec-snt}{Section'tie15.13}
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-'xrdef {Assembler-pg}{250}
-'xrdef {Assembler-snt}{Section'tie15.14}
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+'xrdef {Assembler-snt}{Section'tie14.14}
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-'xrdef {Insns-pg}{251}
-'xrdef {Insns-snt}{Section'tie15.15}
+'xrdef {Insns-pg}{245}
+'xrdef {Insns-snt}{Section'tie14.15}
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-'xrdef {Calls-pg}{259}
-'xrdef {Calls-snt}{Section'tie15.16}
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-'xrdef {Sharing-pg}{261}
-'xrdef {Sharing-snt}{Section'tie15.17}
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-'xrdef {Reading RTL-snt}{Section'tie15.18}
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-'xrdef {Patterns-snt}{Section'tie16.1}
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-'xrdef {Example-pg}{264}
-'xrdef {Example-snt}{Section'tie16.2}
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-'xrdef {RTL Template-snt}{Section'tie16.3}
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-'xrdef {Output Template-pg}{269}
-'xrdef {Output Template-snt}{Section'tie16.4}
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-'xrdef {Output Statement-pg}{271}
-'xrdef {Output Statement-snt}{Section'tie16.5}
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-'xrdef {Constraints-pg}{273}
-'xrdef {Constraints-snt}{Section'tie16.6}
+'xrdef {Constraints-pg}{267}
+'xrdef {Constraints-snt}{Section'tie15.6}
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-'xrdef {Simple Constraints-pg}{273}
-'xrdef {Simple Constraints-snt}{Section'tie16.6.1}
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-'xrdef {Class Preferences-snt}{Section'tie16.6.3}
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-'xrdef {Modifiers-pg}{279}
-'xrdef {Modifiers-snt}{Section'tie16.6.4}
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+'xrdef {Modifiers-snt}{Section'tie15.6.4}
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-'xrdef {Machine Constraints-pg}{280}
-'xrdef {Machine Constraints-snt}{Section'tie16.6.5}
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+'xrdef {No Constraints-pg}{279}
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-'xrdef {Standard Names-pg}{286}
-'xrdef {Standard Names-snt}{Section'tie16.7}
+'xrdef {Standard Names-pg}{280}
+'xrdef {Standard Names-snt}{Section'tie15.7}
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-'xrdef {Pattern Ordering-snt}{Section'tie16.8}
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+'xrdef {Pattern Ordering-snt}{Section'tie15.8}
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-'xrdef {Dependent Patterns-pg}{296}
-'xrdef {Dependent Patterns-snt}{Section'tie16.9}
+'xrdef {Dependent Patterns-pg}{290}
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-'xrdef {Jump Patterns-snt}{Section'tie16.10}
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-'xrdef {Insn Canonicalizations-snt}{Section'tie16.11}
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-'xrdef {Peephole Definitions-snt}{Section'tie16.12}
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-'xrdef {Expander Definitions-snt}{Section'tie16.13}
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-'xrdef {Insn Splitting-snt}{Section'tie16.14}
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-'xrdef {Insn Attributes-snt}{Section'tie16.15}
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-'xrdef {Expressions-snt}{Section'tie16.15.2}
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-'xrdef {Tagging Insns-snt}{Section'tie16.15.3}
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-'xrdef {Attr Example-snt}{Section'tie16.15.4}
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-'xrdef {Constant Attributes-snt}{Section'tie16.15.6}
+'xrdef {Constant Attributes-pg}{314}
+'xrdef {Constant Attributes-snt}{Section'tie15.15.6}
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-'xrdef {Delay Slots-pg}{320}
-'xrdef {Delay Slots-snt}{Section'tie16.15.7}
+'xrdef {Delay Slots-pg}{314}
+'xrdef {Delay Slots-snt}{Section'tie15.15.7}
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-'xrdef {Function Units-pg}{322}
-'xrdef {Function Units-snt}{Section'tie16.15.8}
+'xrdef {Function Units-pg}{316}
+'xrdef {Function Units-snt}{Section'tie15.15.8}
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-'xrdef {Target Macros-pg}{325}
-'xrdef {Target Macros-snt}{Chapter'tie17}
+'xrdef {Target Macros-pg}{319}
+'xrdef {Target Macros-snt}{Chapter'tie16}
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-'xrdef {Driver-pg}{325}
-'xrdef {Driver-snt}{Section'tie17.1}
+'xrdef {Driver-pg}{319}
+'xrdef {Driver-snt}{Section'tie16.1}
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-'xrdef {Run-time Target-pg}{329}
-'xrdef {Run-time Target-snt}{Section'tie17.2}
+'xrdef {Run-time Target-pg}{323}
+'xrdef {Run-time Target-snt}{Section'tie16.2}
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-'xrdef {Storage Layout-pg}{332}
-'xrdef {Storage Layout-snt}{Section'tie17.3}
+'xrdef {Storage Layout-pg}{326}
+'xrdef {Storage Layout-snt}{Section'tie16.3}
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-'xrdef {Type Layout-pg}{337}
-'xrdef {Type Layout-snt}{Section'tie17.4}
+'xrdef {Type Layout-pg}{331}
+'xrdef {Type Layout-snt}{Section'tie16.4}
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-'xrdef {Registers-pg}{340}
-'xrdef {Registers-snt}{Section'tie17.5}
+'xrdef {Registers-pg}{334}
+'xrdef {Registers-snt}{Section'tie16.5}
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-'xrdef {Register Basics-pg}{340}
-'xrdef {Register Basics-snt}{Section'tie17.5.1}
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+'xrdef {Register Basics-snt}{Section'tie16.5.1}
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-'xrdef {Allocation Order-pg}{342}
-'xrdef {Allocation Order-snt}{Section'tie17.5.2}
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+'xrdef {Allocation Order-snt}{Section'tie16.5.2}
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-'xrdef {Values in Registers-snt}{Section'tie17.5.3}
+'xrdef {Values in Registers-pg}{336}
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-'xrdef {Leaf Functions-pg}{344}
-'xrdef {Leaf Functions-snt}{Section'tie17.5.4}
+'xrdef {Leaf Functions-pg}{338}
+'xrdef {Leaf Functions-snt}{Section'tie16.5.4}
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-'xrdef {Stack Registers-pg}{345}
-'xrdef {Stack Registers-snt}{Section'tie17.5.5}
+'xrdef {Stack Registers-pg}{339}
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-'xrdef {Obsolete Register Macros-pg}{346}
-'xrdef {Obsolete Register Macros-snt}{Section'tie17.5.6}
+'xrdef {Obsolete Register Macros-pg}{339}
+'xrdef {Obsolete Register Macros-snt}{Section'tie16.5.6}
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-'xrdef {Register Classes-pg}{347}
-'xrdef {Register Classes-snt}{Section'tie17.6}
+'xrdef {Register Classes-pg}{340}
+'xrdef {Register Classes-snt}{Section'tie16.6}
 'xrdef {Stack and Calling-title}{Stack Layout and Calling Conventions}
-'xrdef {Stack and Calling-pg}{353}
-'xrdef {Stack and Calling-snt}{Section'tie17.7}
+'xrdef {Stack and Calling-pg}{347}
+'xrdef {Stack and Calling-snt}{Section'tie16.7}
 'xrdef {Frame Layout-title}{Basic Stack Layout}
-'xrdef {Frame Layout-pg}{353}
-'xrdef {Frame Layout-snt}{Section'tie17.7.1}
+'xrdef {Frame Layout-pg}{347}
+'xrdef {Frame Layout-snt}{Section'tie16.7.1}
 'xrdef {Frame Registers-title}{Registers That Address the Stack Frame}
-'xrdef {Frame Registers-pg}{355}
-'xrdef {Frame Registers-snt}{Section'tie17.7.2}
+'xrdef {Frame Registers-pg}{349}
+'xrdef {Frame Registers-snt}{Section'tie16.7.2}
 'xrdef {Elimination-title}{Eliminating Frame Pointer and Arg Pointer}
-'xrdef {Elimination-pg}{357}
-'xrdef {Elimination-snt}{Section'tie17.7.3}
+'xrdef {Elimination-pg}{350}
+'xrdef {Elimination-snt}{Section'tie16.7.3}
 'xrdef {Stack Arguments-title}{Passing Function Arguments on the Stack}
-'xrdef {Stack Arguments-pg}{358}
-'xrdef {Stack Arguments-snt}{Section'tie17.7.4}
+'xrdef {Stack Arguments-pg}{352}
+'xrdef {Stack Arguments-snt}{Section'tie16.7.4}
 'xrdef {Register Arguments-title}{Passing Arguments in Registers}
-'xrdef {Register Arguments-pg}{360}
-'xrdef {Register Arguments-snt}{Section'tie17.7.5}
+'xrdef {Register Arguments-pg}{354}
+'xrdef {Register Arguments-snt}{Section'tie16.7.5}
 'xrdef {Scalar Return-title}{How Scalar Function Values Are Returned}
-'xrdef {Scalar Return-pg}{363}
-'xrdef {Scalar Return-snt}{Section'tie17.7.6}
+'xrdef {Scalar Return-pg}{357}
+'xrdef {Scalar Return-snt}{Section'tie16.7.6}
 'xrdef {Aggregate Return-title}{How Large Values Are Returned}
-'xrdef {Aggregate Return-pg}{365}
-'xrdef {Aggregate Return-snt}{Section'tie17.7.7}
+'xrdef {Aggregate Return-pg}{359}
+'xrdef {Aggregate Return-snt}{Section'tie16.7.7}
 'xrdef {Caller Saves-title}{Caller-Saves Register Allocation}
-'xrdef {Caller Saves-pg}{366}
-'xrdef {Caller Saves-snt}{Section'tie17.7.8}
+'xrdef {Caller Saves-pg}{360}
+'xrdef {Caller Saves-snt}{Section'tie16.7.8}
 'xrdef {Function Entry-title}{Function Entry and Exit}
-'xrdef {Function Entry-pg}{367}
-'xrdef {Function Entry-snt}{Section'tie17.7.9}
+'xrdef {Function Entry-pg}{361}
+'xrdef {Function Entry-snt}{Section'tie16.7.9}
 'xrdef {Profiling-title}{Generating Code for Profiling}
-'xrdef {Profiling-pg}{370}
-'xrdef {Profiling-snt}{Section'tie17.7.10}
+'xrdef {Profiling-pg}{364}
+'xrdef {Profiling-snt}{Section'tie16.7.10}
 'xrdef {Varargs-title}{Implementing the Varargs Macros}
-'xrdef {Varargs-pg}{371}
-'xrdef {Varargs-snt}{Section'tie17.8}
+'xrdef {Varargs-pg}{365}
+'xrdef {Varargs-snt}{Section'tie16.8}
 'xrdef {Trampolines-title}{Trampolines for Nested Functions}
-'xrdef {Trampolines-pg}{373}
-'xrdef {Trampolines-snt}{Section'tie17.9}
+'xrdef {Trampolines-pg}{367}
+'xrdef {Trampolines-snt}{Section'tie16.9}
 'xrdef {Library Calls-title}{Implicit Calls to Library Routines}
-'xrdef {Library Calls-pg}{376}
-'xrdef {Library Calls-snt}{Section'tie17.10}
+'xrdef {Library Calls-pg}{370}
+'xrdef {Library Calls-snt}{Section'tie16.10}
 'xrdef {Addressing Modes-title}{Addressing Modes}
-'xrdef {Addressing Modes-pg}{379}
-'xrdef {Addressing Modes-snt}{Section'tie17.11}
+'xrdef {Addressing Modes-pg}{373}
+'xrdef {Addressing Modes-snt}{Section'tie16.11}
 'xrdef {Condition Code-title}{Condition Code Status}
-'xrdef {Condition Code-pg}{382}
-'xrdef {Condition Code-snt}{Section'tie17.12}
+'xrdef {Condition Code-pg}{376}
+'xrdef {Condition Code-snt}{Section'tie16.12}
 'xrdef {Costs-title}{Describing Relative Costs of Operations}
-'xrdef {Costs-pg}{385}
-'xrdef {Costs-snt}{Section'tie17.13}
+'xrdef {Costs-pg}{378}
+'xrdef {Costs-snt}{Section'tie16.13}
 'xrdef {Sections-title}{Dividing the Output into Sections (Texts, Data, \dots{})}
-'xrdef {Sections-pg}{388}
-'xrdef {Sections-snt}{Section'tie17.14}
+'xrdef {Sections-pg}{382}
+'xrdef {Sections-snt}{Section'tie16.14}
 'xrdef {PIC-title}{Position Independent Code}
-'xrdef {PIC-pg}{390}
-'xrdef {PIC-snt}{Section'tie17.15}
+'xrdef {PIC-pg}{383}
+'xrdef {PIC-snt}{Section'tie16.15}
 'xrdef {Assembler Format-title}{Defining the Output Assembler Language}
-'xrdef {Assembler Format-pg}{391}
-'xrdef {Assembler Format-snt}{Section'tie17.16}
+'xrdef {Assembler Format-pg}{384}
+'xrdef {Assembler Format-snt}{Section'tie16.16}
 'xrdef {File Framework-title}{The Overall Framework of an Assembler File}
-'xrdef {File Framework-pg}{391}
-'xrdef {File Framework-snt}{Section'tie17.16.1}
+'xrdef {File Framework-pg}{385}
+'xrdef {File Framework-snt}{Section'tie16.16.1}
 'xrdef {Data Output-title}{Output of Data}
-'xrdef {Data Output-pg}{393}
-'xrdef {Data Output-snt}{Section'tie17.16.2}
+'xrdef {Data Output-pg}{386}
+'xrdef {Data Output-snt}{Section'tie16.16.2}
 'xrdef {Uninitialized Data-title}{Output of Uninitialized Variables}
-'xrdef {Uninitialized Data-pg}{395}
-'xrdef {Uninitialized Data-snt}{Section'tie17.16.3}
+'xrdef {Uninitialized Data-pg}{389}
+'xrdef {Uninitialized Data-snt}{Section'tie16.16.3}
 'xrdef {Label Output-title}{Output and Generation of Labels}
-'xrdef {Label Output-pg}{396}
-'xrdef {Label Output-snt}{Section'tie17.16.4}
+'xrdef {Label Output-pg}{390}
+'xrdef {Label Output-snt}{Section'tie16.16.4}
 'xrdef {Initialization-title}{How Initialization Functions Are Handled}
-'xrdef {Initialization-pg}{399}
-'xrdef {Initialization-snt}{Section'tie17.16.5}
+'xrdef {Initialization-pg}{393}
+'xrdef {Initialization-snt}{Section'tie16.16.5}
 'xrdef {Macros for Initialization-title}{Macros Controlling Initialization Routines}
-'xrdef {Macros for Initialization-pg}{402}
-'xrdef {Macros for Initialization-snt}{Section'tie17.16.6}
+'xrdef {Macros for Initialization-pg}{395}
+'xrdef {Macros for Initialization-snt}{Section'tie16.16.6}
 'xrdef {Instruction Output-title}{Output of Assembler Instructions}
-'xrdef {Instruction Output-pg}{403}
-'xrdef {Instruction Output-snt}{Section'tie17.16.7}
+'xrdef {Instruction Output-pg}{397}
+'xrdef {Instruction Output-snt}{Section'tie16.16.7}
 'xrdef {Dispatch Tables-title}{Output of Dispatch Tables}
-'xrdef {Dispatch Tables-pg}{406}
-'xrdef {Dispatch Tables-snt}{Section'tie17.16.8}
+'xrdef {Dispatch Tables-pg}{400}
+'xrdef {Dispatch Tables-snt}{Section'tie16.16.8}
 'xrdef {Alignment Output-title}{Assembler Commands for Alignment}
-'xrdef {Alignment Output-pg}{407}
-'xrdef {Alignment Output-snt}{Section'tie17.16.9}
+'xrdef {Alignment Output-pg}{401}
+'xrdef {Alignment Output-snt}{Section'tie16.16.9}
 'xrdef {Debugging Info-title}{Controlling Debugging Information Format}
-'xrdef {Debugging Info-pg}{408}
-'xrdef {Debugging Info-snt}{Section'tie17.17}
+'xrdef {Debugging Info-pg}{402}
+'xrdef {Debugging Info-snt}{Section'tie16.17}
 'xrdef {All Debuggers-title}{Macros Affecting All Debugging Formats}
-'xrdef {All Debuggers-pg}{408}
-'xrdef {All Debuggers-snt}{Section'tie17.17.1}
+'xrdef {All Debuggers-pg}{402}
+'xrdef {All Debuggers-snt}{Section'tie16.17.1}
 'xrdef {DBX Options-title}{Specific Options for DBX Output}
-'xrdef {DBX Options-pg}{409}
-'xrdef {DBX Options-snt}{Section'tie17.17.2}
+'xrdef {DBX Options-pg}{403}
+'xrdef {DBX Options-snt}{Section'tie16.17.2}
 'xrdef {DBX Hooks-title}{Open-Ended Hooks for DBX Format}
-'xrdef {DBX Hooks-pg}{411}
-'xrdef {DBX Hooks-snt}{Section'tie17.17.3}
+'xrdef {DBX Hooks-pg}{404}
+'xrdef {DBX Hooks-snt}{Section'tie16.17.3}
 'xrdef {File Names and DBX-title}{File Names in DBX Format}
-'xrdef {File Names and DBX-pg}{413}
-'xrdef {File Names and DBX-snt}{Section'tie17.17.4}
+'xrdef {File Names and DBX-pg}{406}
+'xrdef {File Names and DBX-snt}{Section'tie16.17.4}
 'xrdef {SDB and DWARF-title}{Macros for SDB and DWARF Output}
-'xrdef {SDB and DWARF-pg}{414}
-'xrdef {SDB and DWARF-snt}{Section'tie17.17.5}
+'xrdef {SDB and DWARF-pg}{407}
+'xrdef {SDB and DWARF-snt}{Section'tie16.17.5}
 'xrdef {Cross-compilation-title}{Cross Compilation and Floating Point}
-'xrdef {Cross-compilation-pg}{415}
-'xrdef {Cross-compilation-snt}{Section'tie17.18}
+'xrdef {Cross-compilation-pg}{408}
+'xrdef {Cross-compilation-snt}{Section'tie16.18}
 'xrdef {Misc-title}{Miscellaneous Parameters}
-'xrdef {Misc-pg}{417}
-'xrdef {Misc-snt}{Section'tie17.19}
+'xrdef {Misc-pg}{410}
+'xrdef {Misc-snt}{Section'tie16.19}
 'xrdef {Config-title}{The Configuration File}
-'xrdef {Config-pg}{425}
-'xrdef {Config-snt}{Chapter'tie18}
+'xrdef {Config-pg}{417}
+'xrdef {Config-snt}{Chapter'tie17}
 'xrdef {Index-title}{Index}
-'xrdef {Index-pg}{429}
+'xrdef {Index-pg}{421}
 'xrdef {Index-snt}{}
diff -r -u -H -N gcc-2.6.3/gcc.cps gcc-i2.6.3/gcc.cps
--- gcc-2.6.3/gcc.cps	Fri Nov 11 18:44:28 1994
+++ gcc-i2.6.3/gcc.cps	Thu Jul 14 22:07:29 1994
@@ -1,1866 +1,1856 @@
 \initial {!}
-\entry {\samp {!} in constraint}{278}
+\entry {\samp {!} in constraint}{272}
 \initial {#}
-\entry {\samp {#} in constraint}{279}
-\entry {\code {#} in template}{270}
-\entry {\code {#pragma}}{422}
-\entry {\code {#pragma implementation}, implied}{163}
-\entry {\code {#pragma}, reason for not using}{141}
+\entry {\samp {#} in constraint}{273}
+\entry {\code {#} in template}{264}
+\entry {\code {#pragma}}{414}
+\entry {\code {#pragma implementation}, implied}{159}
+\entry {\code {#pragma}, reason for not using}{136}
 \initial {$}
-\entry {$}{142}
+\entry {$}{138}
 \initial {%}
-\entry {\samp {%} in constraint}{279}
-\entry {\samp {%} in template}{269}
+\entry {\samp {%} in constraint}{273}
+\entry {\samp {%} in template}{263}
 \initial {&}
-\entry {\samp {&} in constraint}{279}
+\entry {\samp {&} in constraint}{273}
 \initial {'}
-\entry {'}{182}
+\entry {'}{176}
 \initial {(}
-\entry {(nil)}{222}
+\entry {(nil)}{216}
 \initial {*}
-\entry {\samp {*} in constraint}{279}
-\entry {\code {*} in template}{271}
+\entry {\samp {*} in constraint}{273}
+\entry {\code {*} in template}{265}
 \initial {-}
-\entry {\code {-lgcc}, use with \code {-nostdlib}}{52}
-\entry {\code {-nostdlib} and unresolved references}{52}
+\entry {\code {-lgcc}, use with \code {-nostdlib}}{49}
+\entry {\code {-nostdlib} and unresolved references}{49}
 \initial {/}
-\entry {\samp {/i} in RTL dump}{225}
-\entry {\samp {/s} in RTL dump}{225, 226}
-\entry {\samp {/u} in RTL dump}{225}
-\entry {\samp {/v} in RTL dump}{225}
+\entry {\samp {/i} in RTL dump}{219}
+\entry {\samp {/s} in RTL dump}{219, 220}
+\entry {\samp {/u} in RTL dump}{219}
+\entry {\samp {/v} in RTL dump}{219}
 \initial {=}
-\entry {\samp {=} in constraint}{279}
+\entry {\samp {=} in constraint}{273}
 \initial {?}
-\entry {\samp {?} in constraint}{278}
-\entry {\code {?:} extensions}{127, 128}
-\entry {?: side effect}{129}
+\entry {\samp {?} in constraint}{272}
+\entry {\code {?:} extensions}{123, 124}
+\entry {?: side effect}{125}
 \initial {{\_}}
-\entry {\samp {{\_}} in variables in macros}{126}
-\entry {\code {{\_}{\_}bb{\_}init{\_}func}}{370}
-\entry {\code {{\_}{\_}builtin{\_}apply}}{125}
-\entry {\code {{\_}{\_}builtin{\_}apply{\_}args}}{125}
-\entry {\code {{\_}{\_}builtin{\_}args{\_}info}}{372}
-\entry {\code {{\_}{\_}builtin{\_}classify{\_}type}}{372}
-\entry {\code {{\_}{\_}builtin{\_}next{\_}arg}}{372}
-\entry {\code {{\_}{\_}builtin{\_}return}}{125}
-\entry {\code {{\_}{\_}builtin{\_}saveregs}}{371}
-\entry {\code {{\_}{\_}CTOR{\_}LIST{\_}{\_}}}{400}
-\entry {\code {{\_}{\_}DTOR{\_}LIST{\_}{\_}}}{400}
-\entry {\code {{\_}{\_}main}}{117}
+\entry {\samp {{\_}} in variables in macros}{122}
+\entry {\code {{\_}{\_}bb{\_}init{\_}func}}{364}
+\entry {\code {{\_}{\_}builtin{\_}apply}}{121}
+\entry {\code {{\_}{\_}builtin{\_}apply{\_}args}}{121}
+\entry {\code {{\_}{\_}builtin{\_}args{\_}info}}{366}
+\entry {\code {{\_}{\_}builtin{\_}classify{\_}type}}{366}
+\entry {\code {{\_}{\_}builtin{\_}next{\_}arg}}{366}
+\entry {\code {{\_}{\_}builtin{\_}return}}{121}
+\entry {\code {{\_}{\_}builtin{\_}saveregs}}{365}
+\entry {\code {{\_}{\_}CTOR{\_}LIST{\_}{\_}}}{393}
+\entry {\code {{\_}{\_}DTOR{\_}LIST{\_}{\_}}}{393}
+\entry {\code {{\_}{\_}main}}{112}
 \initial {{\tt\char43}}
-\entry {\samp {{\tt\char43}} in constraint}{279}
+\entry {\samp {{\tt\char43}} in constraint}{273}
 \initial {{\tt\gtr}}
-\entry {\samp {{\tt\gtr}} in constraint}{273}
-\entry {\code {{\tt\gtr}?}}{161}
+\entry {\samp {{\tt\gtr}} in constraint}{267}
+\entry {\code {{\tt\gtr}?}}{157}
 \initial {{\tt\indexbackslash }}
-\entry {{\tt\indexbackslash }}{270}
+\entry {{\tt\indexbackslash }}{264}
 \initial {{\tt\less}}
-\entry {\samp {{\tt\less}} in constraint}{273}
-\entry {\code {{\tt\less}?}}{161}
+\entry {\samp {{\tt\less}} in constraint}{267}
+\entry {\code {{\tt\less}?}}{157}
 \initial {0}
-\entry {\samp {0} in constraint}{274}
+\entry {\samp {0} in constraint}{268}
 \initial {A}
-\entry {\code {abort}}{27, 211}
-\entry {\code {abs}}{27, 240}
-\entry {\code {abs} and attributes}{313}
-\entry {\code {abs\var {m}2} instruction pattern}{289}
-\entry {absolute value}{240}
-\entry {access to operands}{222}
-\entry {accessors}{222}
-\entry {\code {ACCUMULATE{\_}OUTGOING{\_}ARGS}}{359}
-\entry {\code {ACCUMULATE{\_}OUTGOING{\_}ARGS} and stack frames}{368}
-\entry {\code {ADDITIONAL{\_}REGISTER{\_}NAMES}}{403}
-\entry {\code {add\var {m}3} instruction pattern}{288}
-\entry {\code {addr{\_}diff{\_}vec}}{249}
-\entry {\code {addr{\_}diff{\_}vec}, length of}{319}
-\entry {\code {addr{\_}vec}}{249}
-\entry {\code {addr{\_}vec}, length of}{319}
-\entry {\code {address}}{269}
-\entry {address constraints}{275}
-\entry {address of a label}{121}
-\entry {\code {ADDRESS{\_}COST}}{385}
-\entry {\code {address{\_}operand}}{275}
-\entry {addressing modes}{379}
-\entry {\code {ADJUST{\_}COST}}{387}
-\entry {\code {ADJUST{\_}INSN{\_}LENGTH}}{319}
-\entry {aggregates as return values}{365}
-\entry {\code {aligned} attribute}{143}
-\entry {alignment}{143}
-\entry {\code {ALL{\_}REGS}}{347}
-\entry {Alliant}{178}
-\entry {\code {alloca}}{27}
-\entry {\code {alloca} and SunOs}{93}
-\entry {\code {alloca} vs variable-length arrays}{131}
-\entry {\code {alloca}, for SunOs}{113}
-\entry {\code {alloca}, for Unos}{101}
-\entry {\code {allocate{\_}stack} instruction pattern}{295}
-\entry {\code {ALLOCATE{\_}TRAMPOLINE}}{374}
-\entry {alternate keywords}{155}
-\entry {AMD29K options}{61}
-\entry {analysis, data flow}{217}
-\entry {\code {and}}{240}
-\entry {\code {and} and attributes}{313}
-\entry {\code {and}, canonicalization of}{300}
-\entry {\code {and\var {m}3} instruction pattern}{288}
-\entry {ANSI support}{27}
-\entry {apostrophes}{182}
-\entry {\code {APPLY{\_}RESULT{\_}SIZE}}{365}
-\entry {\code {ARG{\_}POINTER{\_}REGNUM}}{356}
-\entry {\code {ARG{\_}POINTER{\_}REGNUM} and virtual registers}{235}
-\entry {\code {arg{\_}pointer{\_}rtx}}{356}
-\entry {\code {ARGS{\_}GROW{\_}DOWNWARD}}{354}
-\entry {argument passing}{213}
-\entry {arguments in frame (88k)}{64}
-\entry {arguments in registers}{360}
-\entry {arguments on stack}{358}
-\entry {arithmetic libraries}{214}
-\entry {arithmetic shift}{240}
-\entry {arithmetic simplifications}{215}
-\entry {arithmetic, in RTL}{238}
-\entry {ARM options}{63}
-\entry {arrays of length zero}{130}
-\entry {arrays of variable length}{131}
-\entry {arrays, non-lvalue}{133}
-\entry {\code {ashift}}{240}
-\entry {\code {ashift} and attributes}{313}
-\entry {\code {ashiftrt}}{240}
-\entry {\code {ashiftrt} and attributes}{313}
-\entry {\code {ashl\var {m}3} instruction pattern}{288}
-\entry {\code {ashr\var {m}3} instruction pattern}{289}
-\entry {\code {asm} expressions}{147}
-\entry {\code {ASM{\_}APP{\_}OFF}}{392}
-\entry {\code {ASM{\_}APP{\_}ON}}{392}
-\entry {\code {ASM{\_}BYTE{\_}OP}}{393}
-\entry {\code {ASM{\_}CLOSE{\_}PAREN}}{394}
-\entry {\code {ASM{\_}COMMENT{\_}START}}{392}
-\entry {\code {ASM{\_}DECLARE{\_}FUNCTION{\_}NAME}}{396}
-\entry {\code {ASM{\_}DECLARE{\_}FUNCTION{\_}SIZE}}{397}
-\entry {\code {ASM{\_}DECLARE{\_}OBJECT{\_}NAME}}{397}
-\entry {\code {ASM{\_}FILE{\_}END}}{391}
-\entry {\code {ASM{\_}FILE{\_}START}}{391}
-\entry {\code {ASM{\_}FINAL{\_}SPEC}}{326}
-\entry {\code {ASM{\_}FINISH{\_}DECLARE{\_}OBJECT}}{397}
-\entry {\code {ASM{\_}FORMAT{\_}PRIVATE{\_}NAME}}{398}
-\entry {\code {asm{\_}fprintf}}{405}
-\entry {\code {ASM{\_}GENERATE{\_}INTERNAL{\_}LABEL}}{398}
-\entry {\code {ASM{\_}GLOBALIZE{\_}LABEL}}{397}
-\entry {\code {ASM{\_}IDENTIFY{\_}GCC}}{391}
-\entry {\code {asm{\_}input}}{249}
-\entry {\code {ASM{\_}NO{\_}SKIP{\_}IN{\_}TEXT}}{408}
-\entry {\code {asm{\_}noperands}}{255}
-\entry {\code {ASM{\_}OPEN{\_}PAREN}}{394}
-\entry {\code {asm{\_}operands}, RTL sharing}{261}
-\entry {\code {asm{\_}operands}, usage}{250}
-\entry {\code {ASM{\_}OUTPUT{\_}ADDR{\_}DIFF{\_}ELT}}{406}
-\entry {\code {ASM{\_}OUTPUT{\_}ADDR{\_}VEC{\_}ELT}}{407}
-\entry {\code {ASM{\_}OUTPUT{\_}ALIGN}}{408}
-\entry {\code {ASM{\_}OUTPUT{\_}ALIGN{\_}CODE}}{407}
-\entry {\code {ASM{\_}OUTPUT{\_}ALIGNED{\_}COMMON}}{395}
-\entry {\code {ASM{\_}OUTPUT{\_}ALIGNED{\_}LOCAL}}{396}
-\entry {\code {ASM{\_}OUTPUT{\_}ASCII}}{393}
-\entry {\code {ASM{\_}OUTPUT{\_}BYTE}}{393}
-\entry {\code {ASM{\_}OUTPUT{\_}CASE{\_}END}}{407}
-\entry {\code {ASM{\_}OUTPUT{\_}CASE{\_}LABEL}}{407}
-\entry {\code {ASM{\_}OUTPUT{\_}CHAR}}{393}
-\entry {\code {ASM{\_}OUTPUT{\_}COMMON}}{395}
-\entry {\code {ASM{\_}OUTPUT{\_}CONSTRUCTOR}}{402}
-\entry {\code {ASM{\_}OUTPUT{\_}DEF}}{399}
-\entry {\code {ASM{\_}OUTPUT{\_}DESTRUCTOR}}{403}
-\entry {\code {ASM{\_}OUTPUT{\_}DOUBLE}}{393}
-\entry {\code {ASM{\_}OUTPUT{\_}DOUBLE{\_}INT}}{393}
-\entry {\code {ASM{\_}OUTPUT{\_}EXTERNAL}}{397}
-\entry {\code {ASM{\_}OUTPUT{\_}EXTERNAL{\_}LIBCALL}}{397}
-\entry {\code {ASM{\_}OUTPUT{\_}FLOAT}}{393}
-\entry {\code {ASM{\_}OUTPUT{\_}IDENT}}{392}
-\entry {\code {ASM{\_}OUTPUT{\_}INT}}{393}
-\entry {\code {ASM{\_}OUTPUT{\_}INTERNAL{\_}LABEL}}{398}
-\entry {\code {ASM{\_}OUTPUT{\_}LABEL}}{396}
-\entry {\code {ASM{\_}OUTPUT{\_}LABELREF}}{398}
-\entry {\code {ASM{\_}OUTPUT{\_}LOCAL}}{396}
-\entry {\code {ASM{\_}OUTPUT{\_}LONG{\_}DOUBLE}}{393}
-\entry {\code {ASM{\_}OUTPUT{\_}LOOP{\_}ALIGN}}{407}
-\entry {\code {ASM{\_}OUTPUT{\_}OPCODE}}{404}
-\entry {\code {ASM{\_}OUTPUT{\_}POOL{\_}PROLOGUE}}{394}
-\entry {\code {ASM{\_}OUTPUT{\_}QUADRUPLE{\_}INT}}{393}
-\entry {\code {ASM{\_}OUTPUT{\_}REG{\_}POP}}{406}
-\entry {\code {ASM{\_}OUTPUT{\_}REG{\_}PUSH}}{406}
-\entry {\code {ASM{\_}OUTPUT{\_}SECTION{\_}NAME}}{392}
-\entry {\code {ASM{\_}OUTPUT{\_}SHARED{\_}COMMON}}{396}
-\entry {\code {ASM{\_}OUTPUT{\_}SHARED{\_}LOCAL}}{396}
-\entry {\code {ASM{\_}OUTPUT{\_}SHORT}}{393}
-\entry {\code {ASM{\_}OUTPUT{\_}SKIP}}{408}
-\entry {\code {ASM{\_}OUTPUT{\_}SOURCE{\_}FILENAME}}{392}
-\entry {\code {ASM{\_}OUTPUT{\_}SOURCE{\_}LINE}}{392}
-\entry {\code {ASM{\_}OUTPUT{\_}SPECIAL{\_}POOL{\_}ENTRY}}{394}
-\entry {\code {ASM{\_}SPEC}}{326}
-\entry {\code {ASM{\_}STABD{\_}OP}}{410}
-\entry {\code {ASM{\_}STABN{\_}OP}}{410}
-\entry {\code {ASM{\_}STABS{\_}OP}}{410}
-\entry {\code {assemble{\_}name}}{396}
-\entry {assembler format}{391}
-\entry {assembler instructions}{147}
-\entry {assembler instructions in RTL}{250}
-\entry {assembler names for identifiers}{151}
-\entry {assembler syntax, 88k}{65}
-\entry {\code {ASSEMBLER{\_}DIALECT}}{406}
-\entry {assembly code, invalid}{193}
-\entry {assigning attribute values to insns}{315}
-\entry {asterisk in template}{271}
-\entry {\code {atof}}{415}
-\entry {\code {attr}}{316}
-\entry {\code {attr{\_}flag}}{314}
-\entry {attribute expressions}{312}
-\entry {attribute of variables}{143}
-\entry {attribute specifications}{317}
-\entry {attribute specifications example}{317}
-\entry {attributes, defining}{311}
-\entry {autoincrement addressing, availability}{211}
-\entry {autoincrement/decrement addressing}{273}
-\entry {autoincrement/decrement analysis}{217}
-\entry {automatic \code {inline} for C{\tt\char43}{\tt\char43} member fns}{146}
+\entry {\code {abort}}{25, 205}
+\entry {\code {abs}}{25, 234}
+\entry {\code {abs} and attributes}{307}
+\entry {\code {abs\var {m}2} instruction pattern}{283}
+\entry {absolute value}{234}
+\entry {access to operands}{216}
+\entry {accessors}{216}
+\entry {\code {ACCUMULATE{\_}OUTGOING{\_}ARGS}}{352}
+\entry {\code {ACCUMULATE{\_}OUTGOING{\_}ARGS} and stack frames}{362}
+\entry {\code {ADDITIONAL{\_}REGISTER{\_}NAMES}}{397}
+\entry {\code {add\var {m}3} instruction pattern}{282}
+\entry {\code {addr{\_}diff{\_}vec}}{243}
+\entry {\code {addr{\_}diff{\_}vec}, length of}{313}
+\entry {\code {addr{\_}vec}}{243}
+\entry {\code {addr{\_}vec}, length of}{313}
+\entry {\code {address}}{263}
+\entry {address constraints}{269}
+\entry {address of a label}{117}
+\entry {\code {ADDRESS{\_}COST}}{379}
+\entry {\code {address{\_}operand}}{269}
+\entry {addressing modes}{373}
+\entry {\code {ADJUST{\_}COST}}{381}
+\entry {\code {ADJUST{\_}INSN{\_}LENGTH}}{313}
+\entry {aggregates as return values}{359}
+\entry {\code {aligned} attribute}{139}
+\entry {alignment}{139}
+\entry {\code {ALL{\_}REGS}}{341}
+\entry {Alliant}{172}
+\entry {\code {alloca}}{25}
+\entry {\code {alloca} and SunOs}{89}
+\entry {\code {alloca} vs variable-length arrays}{127}
+\entry {\code {alloca}, for SunOs}{108}
+\entry {\code {alloca}, for Unos}{96}
+\entry {\code {allocate{\_}stack} instruction pattern}{289}
+\entry {\code {ALLOCATE{\_}TRAMPOLINE}}{368}
+\entry {alternate keywords}{151}
+\entry {AMD29K options}{58}
+\entry {analysis, data flow}{211}
+\entry {\code {and}}{234}
+\entry {\code {and} and attributes}{307}
+\entry {\code {and}, canonicalization of}{294}
+\entry {\code {and\var {m}3} instruction pattern}{282}
+\entry {ANSI support}{25}
+\entry {apostrophes}{176}
+\entry {\code {APPLY{\_}RESULT{\_}SIZE}}{358}
+\entry {\code {ARG{\_}POINTER{\_}REGNUM}}{349}
+\entry {\code {ARG{\_}POINTER{\_}REGNUM} and virtual registers}{229}
+\entry {\code {arg{\_}pointer{\_}rtx}}{350}
+\entry {\code {ARGS{\_}GROW{\_}DOWNWARD}}{347}
+\entry {argument passing}{207}
+\entry {arguments in frame (88k)}{61}
+\entry {arguments in registers}{354}
+\entry {arguments on stack}{352}
+\entry {arithmetic libraries}{208}
+\entry {arithmetic shift}{234}
+\entry {arithmetic simplifications}{209}
+\entry {arithmetic, in RTL}{232}
+\entry {ARM options}{60}
+\entry {arrays of length zero}{126}
+\entry {arrays of variable length}{127}
+\entry {arrays, non-lvalue}{129}
+\entry {\code {ashift}}{234}
+\entry {\code {ashift} and attributes}{307}
+\entry {\code {ashiftrt}}{234}
+\entry {\code {ashiftrt} and attributes}{307}
+\entry {\code {ashl\var {m}3} instruction pattern}{282}
+\entry {\code {ashr\var {m}3} instruction pattern}{283}
+\entry {\code {asm} expressions}{143}
+\entry {\code {ASM{\_}APP{\_}OFF}}{385}
+\entry {\code {ASM{\_}APP{\_}ON}}{385}
+\entry {\code {ASM{\_}BYTE{\_}OP}}{387}
+\entry {\code {ASM{\_}CLOSE{\_}PAREN}}{388}
+\entry {\code {ASM{\_}COMMENT{\_}START}}{385}
+\entry {\code {ASM{\_}DECLARE{\_}FUNCTION{\_}NAME}}{390}
+\entry {\code {ASM{\_}DECLARE{\_}FUNCTION{\_}SIZE}}{390}
+\entry {\code {ASM{\_}DECLARE{\_}OBJECT{\_}NAME}}{390}
+\entry {\code {ASM{\_}FILE{\_}END}}{385}
+\entry {\code {ASM{\_}FILE{\_}START}}{385}
+\entry {\code {ASM{\_}FINAL{\_}SPEC}}{320}
+\entry {\code {ASM{\_}FINISH{\_}DECLARE{\_}OBJECT}}{391}
+\entry {\code {ASM{\_}FORMAT{\_}PRIVATE{\_}NAME}}{392}
+\entry {\code {asm{\_}fprintf}}{399}
+\entry {\code {ASM{\_}GENERATE{\_}INTERNAL{\_}LABEL}}{392}
+\entry {\code {ASM{\_}GLOBALIZE{\_}LABEL}}{391}
+\entry {\code {ASM{\_}IDENTIFY{\_}GCC}}{385}
+\entry {\code {asm{\_}input}}{243}
+\entry {\code {ASM{\_}NO{\_}SKIP{\_}IN{\_}TEXT}}{401}
+\entry {\code {asm{\_}noperands}}{249}
+\entry {\code {ASM{\_}OPEN{\_}PAREN}}{388}
+\entry {\code {asm{\_}operands}, RTL sharing}{255}
+\entry {\code {asm{\_}operands}, usage}{244}
+\entry {\code {ASM{\_}OUTPUT{\_}ADDR{\_}DIFF{\_}ELT}}{400}
+\entry {\code {ASM{\_}OUTPUT{\_}ADDR{\_}VEC{\_}ELT}}{400}
+\entry {\code {ASM{\_}OUTPUT{\_}ALIGN}}{401}
+\entry {\code {ASM{\_}OUTPUT{\_}ALIGN{\_}CODE}}{401}
+\entry {\code {ASM{\_}OUTPUT{\_}ALIGNED{\_}COMMON}}{389}
+\entry {\code {ASM{\_}OUTPUT{\_}ALIGNED{\_}LOCAL}}{390}
+\entry {\code {ASM{\_}OUTPUT{\_}ASCII}}{387}
+\entry {\code {ASM{\_}OUTPUT{\_}BYTE}}{387}
+\entry {\code {ASM{\_}OUTPUT{\_}CASE{\_}END}}{400}
+\entry {\code {ASM{\_}OUTPUT{\_}CASE{\_}LABEL}}{400}
+\entry {\code {ASM{\_}OUTPUT{\_}CHAR}}{387}
+\entry {\code {ASM{\_}OUTPUT{\_}COMMON}}{389}
+\entry {\code {ASM{\_}OUTPUT{\_}CONSTRUCTOR}}{396}
+\entry {\code {ASM{\_}OUTPUT{\_}DEF}}{392}
+\entry {\code {ASM{\_}OUTPUT{\_}DESTRUCTOR}}{396}
+\entry {\code {ASM{\_}OUTPUT{\_}DOUBLE}}{386}
+\entry {\code {ASM{\_}OUTPUT{\_}DOUBLE{\_}INT}}{387}
+\entry {\code {ASM{\_}OUTPUT{\_}EXTERNAL}}{391}
+\entry {\code {ASM{\_}OUTPUT{\_}EXTERNAL{\_}LIBCALL}}{391}
+\entry {\code {ASM{\_}OUTPUT{\_}FLOAT}}{386}
+\entry {\code {ASM{\_}OUTPUT{\_}IDENT}}{386}
+\entry {\code {ASM{\_}OUTPUT{\_}INT}}{387}
+\entry {\code {ASM{\_}OUTPUT{\_}INTERNAL{\_}LABEL}}{391}
+\entry {\code {ASM{\_}OUTPUT{\_}LABEL}}{390}
+\entry {\code {ASM{\_}OUTPUT{\_}LABELREF}}{391}
+\entry {\code {ASM{\_}OUTPUT{\_}LOCAL}}{389}
+\entry {\code {ASM{\_}OUTPUT{\_}LONG{\_}DOUBLE}}{386}
+\entry {\code {ASM{\_}OUTPUT{\_}LOOP{\_}ALIGN}}{401}
+\entry {\code {ASM{\_}OUTPUT{\_}OPCODE}}{397}
+\entry {\code {ASM{\_}OUTPUT{\_}POOL{\_}PROLOGUE}}{387}
+\entry {\code {ASM{\_}OUTPUT{\_}QUADRUPLE{\_}INT}}{387}
+\entry {\code {ASM{\_}OUTPUT{\_}REG{\_}POP}}{399}
+\entry {\code {ASM{\_}OUTPUT{\_}REG{\_}PUSH}}{399}
+\entry {\code {ASM{\_}OUTPUT{\_}SECTION{\_}NAME}}{386}
+\entry {\code {ASM{\_}OUTPUT{\_}SHARED{\_}COMMON}}{389}
+\entry {\code {ASM{\_}OUTPUT{\_}SHARED{\_}LOCAL}}{390}
+\entry {\code {ASM{\_}OUTPUT{\_}SHORT}}{387}
+\entry {\code {ASM{\_}OUTPUT{\_}SKIP}}{401}
+\entry {\code {ASM{\_}OUTPUT{\_}SOURCE{\_}FILENAME}}{385}
+\entry {\code {ASM{\_}OUTPUT{\_}SOURCE{\_}LINE}}{386}
+\entry {\code {ASM{\_}OUTPUT{\_}SPECIAL{\_}POOL{\_}ENTRY}}{387}
+\entry {\code {ASM{\_}SPEC}}{320}
+\entry {\code {ASM{\_}STABD{\_}OP}}{403}
+\entry {\code {ASM{\_}STABN{\_}OP}}{403}
+\entry {\code {ASM{\_}STABS{\_}OP}}{403}
+\entry {\code {assemble{\_}name}}{390}
+\entry {assembler format}{385}
+\entry {assembler instructions}{143}
+\entry {assembler instructions in RTL}{244}
+\entry {assembler names for identifiers}{147}
+\entry {assembler syntax, 88k}{62}
+\entry {\code {ASSEMBLER{\_}DIALECT}}{399}
+\entry {assembly code, invalid}{187}
+\entry {assigning attribute values to insns}{309}
+\entry {asterisk in template}{265}
+\entry {\code {atof}}{408}
+\entry {\code {attr}}{310}
+\entry {\code {attr{\_}flag}}{308}
+\entry {attribute expressions}{306}
+\entry {attribute of variables}{139}
+\entry {attribute specifications}{311}
+\entry {attribute specifications example}{311}
+\entry {attributes, defining}{305}
+\entry {autoincrement addressing, availability}{205}
+\entry {autoincrement/decrement addressing}{267}
+\entry {autoincrement/decrement analysis}{211}
+\entry {automatic \code {inline} for C{\tt\char43}{\tt\char43} member fns}{142}
 \initial {B}
-\entry {backslash}{270}
-\entry {backtrace for bug reports}{197}
-\entry {\code {barrier}}{253}
-\entry {\code {BASE{\_}REG{\_}CLASS}}{348}
-\entry {basic blocks}{217}
-\entry {\code {bcmp}}{427}
-\entry {\code {b\var {cond}} instruction pattern}{292}
-\entry {\code {bcopy}, implicit usage}{378}
-\entry {\code {BIGGEST{\_}ALIGNMENT}}{334}
-\entry {\code {BIGGEST{\_}FIELD{\_}ALIGNMENT}}{334}
-\entry {Bison parser generator}{90}
-\entry {bit fields}{243}
-\entry {bit shift overflow (88k)}{66}
-\entry {\code {BITFIELD{\_}NBYTES{\_}LIMITED}}{336}
-\entry {\code {BITS{\_}BIG{\_}ENDIAN}}{332}
-\entry {\code {BITS{\_}BIG{\_}ENDIAN}, effect on \code {sign{\_}extract}}{243}
-\entry {\code {BITS{\_}PER{\_}UNIT}}{332}
-\entry {\code {BITS{\_}PER{\_}WORD}}{333}
-\entry {bitwise complement}{240}
-\entry {bitwise exclusive-or}{240}
-\entry {bitwise inclusive-or}{240}
-\entry {bitwise logical-and}{240}
-\entry {\code {BLKmode}}{229}
-\entry {\code {BLKmode}, and function return values}{260}
-\entry {\code {BLOCK{\_}PROFILER}}{371}
-\entry {\code {BLOCK{\_}PROFILER{\_}CODE}}{371}
-\entry {\code {BRANCH{\_}COST}}{386}
-\entry {\code {break{\_}out{\_}memory{\_}refs}}{382}
-\entry {bug criteria}{193}
-\entry {bug report mailing lists}{194}
-\entry {bugs}{193}
-\entry {bugs, known}{169}
-\entry {builtin functions}{27}
-\entry {byte writes (29k)}{62}
-\entry {\code {byte{\_}mode}}{232}
-\entry {\code {BYTES{\_}BIG{\_}ENDIAN}}{332}
-\entry {\code {bzero}}{427}
-\entry {\code {bzero}, implicit usage}{378}
+\entry {backslash}{264}
+\entry {backtrace for bug reports}{191}
+\entry {\code {barrier}}{247}
+\entry {\code {BASE{\_}REG{\_}CLASS}}{342}
+\entry {basic blocks}{211}
+\entry {\code {bcmp}}{419}
+\entry {\code {b\var {cond}} instruction pattern}{286}
+\entry {\code {bcopy}, implicit usage}{372}
+\entry {\code {BIGGEST{\_}ALIGNMENT}}{328}
+\entry {\code {BIGGEST{\_}FIELD{\_}ALIGNMENT}}{328}
+\entry {Bison parser generator}{86}
+\entry {bit fields}{237}
+\entry {bit shift overflow (88k)}{63}
+\entry {\code {BITFIELD{\_}NBYTES{\_}LIMITED}}{330}
+\entry {\code {BITS{\_}BIG{\_}ENDIAN}}{326}
+\entry {\code {BITS{\_}BIG{\_}ENDIAN}, effect on \code {sign{\_}extract}}{237}
+\entry {\code {BITS{\_}PER{\_}UNIT}}{326}
+\entry {\code {BITS{\_}PER{\_}WORD}}{326}
+\entry {bitwise complement}{234}
+\entry {bitwise exclusive-or}{234}
+\entry {bitwise inclusive-or}{234}
+\entry {bitwise logical-and}{234}
+\entry {\code {BLKmode}}{223}
+\entry {\code {BLKmode}, and function return values}{254}
+\entry {\code {BLOCK{\_}PROFILER}}{364}
+\entry {\code {BLOCK{\_}PROFILER{\_}CODE}}{365}
+\entry {\code {BRANCH{\_}COST}}{380}
+\entry {\code {break{\_}out{\_}memory{\_}refs}}{375}
+\entry {bug criteria}{187}
+\entry {bug report mailing lists}{188}
+\entry {bugs}{187}
+\entry {bugs, known}{163}
+\entry {builtin functions}{25}
+\entry {byte writes (29k)}{58}
+\entry {\code {byte{\_}mode}}{226}
+\entry {\code {BYTES{\_}BIG{\_}ENDIAN}}{326}
+\entry {\code {bzero}}{419}
+\entry {\code {bzero}, implicit usage}{372}
 \initial {C}
-\entry {C compilation options}{19}
-\entry {C intermediate output, nonexistent}{17}
-\entry {C language extensions}{119}
-\entry {C language, traditional}{28}
-\entry {C statements for assembler output}{271}
-\entry {\code {C{\_}INCLUDE{\_}PATH}}{82}
-\entry {\code {c{\tt\char43}{\tt\char43}}}{26}
-\entry {C{\tt\char43}{\tt\char43}}{17}
-\entry {C{\tt\char43}{\tt\char43} compilation options}{19}
-\entry {C{\tt\char43}{\tt\char43} interface and implementation headers}{162}
-\entry {C{\tt\char43}{\tt\char43} language extensions}{159}
-\entry {C{\tt\char43}{\tt\char43} member fns, automatically \code {inline}}{146}
-\entry {C{\tt\char43}{\tt\char43} misunderstandings}{185}
-\entry {C{\tt\char43}{\tt\char43} named return value}{159}
-\entry {C{\tt\char43}{\tt\char43} options, command line}{30}
-\entry {C{\tt\char43}{\tt\char43} pragmas, effect on inlining}{163}
-\entry {C{\tt\char43}{\tt\char43} signatures}{166}
-\entry {C{\tt\char43}{\tt\char43} source file suffixes}{26}
-\entry {C{\tt\char43}{\tt\char43} static data, declaring and defining}{186}
-\entry {C{\tt\char43}{\tt\char43} subtype polymorphism}{166}
-\entry {C{\tt\char43}{\tt\char43} type abstraction}{166}
-\entry {\code {call}}{246}
-\entry {\code {call} instruction pattern}{292}
-\entry {\code {call} usage}{259}
-\entry {call-clobbered register}{341}
-\entry {call-saved register}{341}
-\entry {call-used register}{341}
-\entry {\code {call{\_}insn}}{253}
-\entry {\code {call{\_}insn} and \samp {/u}}{226}
-\entry {\code {CALL{\_}INSN{\_}FUNCTION{\_}USAGE}}{253}
-\entry {\code {call{\_}pop} instruction pattern}{292}
-\entry {\code {CALL{\_}USED{\_}REGISTERS}}{341}
-\entry {\code {call{\_}used{\_}regs}}{341}
-\entry {\code {call{\_}value} instruction pattern}{292}
-\entry {\code {call{\_}value{\_}pop} instruction pattern}{292}
-\entry {\code {CALLER{\_}SAVE{\_}PROFITABLE}}{367}
-\entry {calling conventions}{353}
-\entry {calling functions in RTL}{259}
-\entry {\code {CAN{\_}DEBUG{\_}WITHOUT{\_}FP}}{332}
-\entry {\code {CAN{\_}ELIMINATE}}{358}
-\entry {canonicalization of instructions}{300}
-\entry {\code {CANONICALIZE{\_}COMPARISON}}{384}
-\entry {case labels in initializers}{135}
-\entry {case ranges}{137}
-\entry {case sensitivity and VMS}{209}
-\entry {\code {CASE{\_}DROPS{\_}THROUGH}}{418}
-\entry {\code {CASE{\_}VALUES{\_}THRESHOLD}}{418}
-\entry {\code {CASE{\_}VECTOR{\_}MODE}}{418}
-\entry {\code {CASE{\_}VECTOR{\_}PC{\_}RELATIVE}}{418}
-\entry {\code {casesi} instruction pattern}{294}
-\entry {cast to a union}{137}
-\entry {casts as lvalues}{127}
-\entry {\code {cc{\_}status}}{382}
-\entry {\code {CC{\_}STATUS{\_}MDEP}}{383}
-\entry {\code {CC{\_}STATUS{\_}MDEP{\_}INIT}}{383}
-\entry {\code {cc0}}{237}
-\entry {\code {cc0}, RTL sharing}{261}
-\entry {\code {cc0{\_}rtx}}{237}
-\entry {\code {CC1{\_}SPEC}}{326}
-\entry {\code {CC1PLUS{\_}SPEC}}{326}
-\entry {\code {CCmode}}{229}
-\entry {\code {CDImode}}{230}
-\entry {\code {change{\_}address}}{286}
-\entry {\code {CHAR{\_}TYPE{\_}SIZE}}{338}
-\entry {\code {CHECK{\_}FLOAT{\_}VALUE}}{337}
-\entry {\code {CHImode}}{230}
-\entry {class definitions, register}{347}
-\entry {class preference constraints}{278}
-\entry {\code {CLASS{\_}LIKELY{\_}SPILLED{\_}P}}{352}
-\entry {\code {CLASS{\_}MAX{\_}NREGS}}{352}
-\entry {classes of RTX codes}{223}
-\entry {\code {CLEAR{\_}INSN{\_}CACHE}}{375}
-\entry {\code {clobber}}{246}
-\entry {\code {cmp\var {m}} instruction pattern}{289}
-\entry {\code {cmpstr\var {m}} instruction pattern}{289}
-\entry {code generation conventions}{78}
-\entry {code generation RTL sequences}{305}
-\entry {code motion}{217}
-\entry {\code {code{\_}label}}{253}
-\entry {\code {code{\_}label} and \samp {/i}}{227}
-\entry {\code {CODE{\_}LABEL{\_}NUMBER}}{253}
-\entry {codes, RTL expression}{221}
-\entry {\code {COImode}}{230}
-\entry {combiner pass}{236}
-\entry {command options}{19}
-\entry {common subexpression elimination}{217}
-\entry {\code {COMP{\_}TYPE{\_}ATTRIBUTES}}{422}
-\entry {\code {compare}}{238}
-\entry {\code {compare}, canonicalization of}{300}
-\entry {compilation in a separate directory}{106}
-\entry {compiler bugs, reporting}{195}
-\entry {compiler compared to C{\tt\char43}{\tt\char43} preprocessor}{17}
-\entry {compiler options, C{\tt\char43}{\tt\char43}}{30}
-\entry {compiler passes and files}{215}
-\entry {compiler version, specifying}{54}
-\entry {\code {COMPILER{\_}PATH}}{82}
-\entry {complement, bitwise}{240}
-\entry {complex numbers}{129}
-\entry {compound expressions as lvalues}{127}
-\entry {computed gotos}{121}
-\entry {computing the length of an insn}{318}
-\entry {\code {cond}}{242}
-\entry {\code {cond} and attributes}{313}
-\entry {condition code register}{237}
-\entry {condition code status}{382}
-\entry {condition codes}{241}
-\entry {conditional expressions as lvalues}{127}
-\entry {conditional expressions, extensions}{128}
-\entry {\code {CONDITIONAL{\_}REGISTER{\_}USAGE}}{341}
-\entry {conditions, in patterns}{264}
-\entry {configuration file}{425}
-\entry {configurations supported by GNU CC}{93}
-\entry {conflicting types}{184}
-\entry {\code {const} applied to function}{138}
-\entry {\code {const} function attribute}{139}
-\entry {\code {CONST{\_}CALL{\_}P}}{226}
-\entry {\code {CONST{\_}COSTS}}{385}
-\entry {\code {const{\_}double}}{232}
-\entry {\code {const{\_}double}, RTL sharing}{261}
-\entry {\code {CONST{\_}DOUBLE{\_}CHAIN}}{232}
-\entry {\code {CONST{\_}DOUBLE{\_}LOW}}{233}
-\entry {\code {CONST{\_}DOUBLE{\_}MEM}}{232}
-\entry {\code {CONST{\_}DOUBLE{\_}OK{\_}FOR{\_}LETTER{\_}P}}{353}
-\entry {\code {const{\_}int}}{232}
-\entry {\code {const{\_}int} and attribute tests}{313}
-\entry {\code {const{\_}int} and attributes}{312}
-\entry {\code {const{\_}int}, RTL sharing}{261}
-\entry {\code {CONST{\_}OK{\_}FOR{\_}LETTER{\_}P}}{353}
-\entry {\code {const{\_}string}}{233}
-\entry {\code {const{\_}string} and attributes}{313}
-\entry {\code {const{\_}true{\_}rtx}}{232}
-\entry {\code {const0{\_}rtx}}{232}
-\entry {\code {CONST0{\_}RTX}}{233}
-\entry {\code {const1{\_}rtx}}{232}
-\entry {\code {CONST1{\_}RTX}}{233}
-\entry {\code {const2{\_}rtx}}{232}
-\entry {\code {CONST2{\_}RTX}}{233}
-\entry {constant attributes}{320}
-\entry {constant folding}{215}
-\entry {constant folding and floating point}{416}
-\entry {constant propagation}{217}
-\entry {\code {CONSTANT{\_}ADDRESS{\_}P}}{380}
-\entry {\code {CONSTANT{\_}ALIGNMENT}}{334}
-\entry {\code {CONSTANT{\_}P}}{380}
-\entry {\code {CONSTANT{\_}POOL{\_}ADDRESS{\_}P}}{226}
-\entry {constants in constraints}{274}
-\entry {\code {constm1{\_}rtx}}{232}
-\entry {constraint modifier characters}{279}
-\entry {constraint, matching}{274}
-\entry {constraints}{273}
-\entry {constraints, machine specific}{280}
-\entry {constructing calls}{125}
-\entry {constructor expressions}{134}
-\entry {constructors vs \code {goto}}{162}
-\entry {constructors, automatic calls}{117}
-\entry {constructors, output of}{399}
+\entry {C compilation options}{17}
+\entry {C intermediate output, nonexistent}{15}
+\entry {C language extensions}{115}
+\entry {C language, traditional}{26}
+\entry {C statements for assembler output}{265}
+\entry {\code {C{\_}INCLUDE{\_}PATH}}{78}
+\entry {\code {c{\tt\char43}{\tt\char43}}}{24}
+\entry {C{\tt\char43}{\tt\char43}}{15}
+\entry {C{\tt\char43}{\tt\char43} compilation options}{17}
+\entry {C{\tt\char43}{\tt\char43} interface and implementation headers}{158}
+\entry {C{\tt\char43}{\tt\char43} language extensions}{155}
+\entry {C{\tt\char43}{\tt\char43} member fns, automatically \code {inline}}{142}
+\entry {C{\tt\char43}{\tt\char43} misunderstandings}{179}
+\entry {C{\tt\char43}{\tt\char43} named return value}{155}
+\entry {C{\tt\char43}{\tt\char43} options, command line}{28}
+\entry {C{\tt\char43}{\tt\char43} pragmas, effect on inlining}{159}
+\entry {C{\tt\char43}{\tt\char43} signatures}{160}
+\entry {C{\tt\char43}{\tt\char43} source file suffixes}{24}
+\entry {C{\tt\char43}{\tt\char43} static data, declaring and defining}{180}
+\entry {C{\tt\char43}{\tt\char43} subtype polymorphism}{160}
+\entry {C{\tt\char43}{\tt\char43} type abstraction}{160}
+\entry {\code {call}}{240}
+\entry {\code {call} instruction pattern}{286}
+\entry {\code {call} usage}{253}
+\entry {call-clobbered register}{335}
+\entry {call-saved register}{335}
+\entry {call-used register}{335}
+\entry {\code {call{\_}insn}}{247}
+\entry {\code {call{\_}insn} and \samp {/u}}{220}
+\entry {\code {CALL{\_}INSN{\_}FUNCTION{\_}USAGE}}{247}
+\entry {\code {call{\_}pop} instruction pattern}{286}
+\entry {\code {CALL{\_}USED{\_}REGISTERS}}{335}
+\entry {\code {call{\_}used{\_}regs}}{335}
+\entry {\code {call{\_}value} instruction pattern}{286}
+\entry {\code {call{\_}value{\_}pop} instruction pattern}{286}
+\entry {\code {CALLER{\_}SAVE{\_}PROFITABLE}}{360}
+\entry {calling conventions}{347}
+\entry {calling functions in RTL}{253}
+\entry {\code {CAN{\_}DEBUG{\_}WITHOUT{\_}FP}}{325}
+\entry {\code {CAN{\_}ELIMINATE}}{351}
+\entry {canonicalization of instructions}{294}
+\entry {\code {CANONICALIZE{\_}COMPARISON}}{378}
+\entry {case labels in initializers}{131}
+\entry {case ranges}{133}
+\entry {case sensitivity and VMS}{203}
+\entry {\code {CASE{\_}DROPS{\_}THROUGH}}{411}
+\entry {\code {CASE{\_}VALUES{\_}THRESHOLD}}{411}
+\entry {\code {CASE{\_}VECTOR{\_}MODE}}{411}
+\entry {\code {CASE{\_}VECTOR{\_}PC{\_}RELATIVE}}{411}
+\entry {\code {casesi} instruction pattern}{288}
+\entry {cast to a union}{133}
+\entry {casts as lvalues}{123}
+\entry {\code {cc{\_}status}}{376}
+\entry {\code {CC{\_}STATUS{\_}MDEP}}{376}
+\entry {\code {CC{\_}STATUS{\_}MDEP{\_}INIT}}{376}
+\entry {\code {cc0}}{231}
+\entry {\code {cc0}, RTL sharing}{255}
+\entry {\code {cc0{\_}rtx}}{231}
+\entry {\code {CC1{\_}SPEC}}{320}
+\entry {\code {CC1PLUS{\_}SPEC}}{320}
+\entry {\code {CCmode}}{223}
+\entry {\code {CDImode}}{224}
+\entry {\code {change{\_}address}}{280}
+\entry {\code {CHAR{\_}TYPE{\_}SIZE}}{332}
+\entry {\code {CHECK{\_}FLOAT{\_}VALUE}}{330}
+\entry {\code {CHImode}}{224}
+\entry {class definitions, register}{340}
+\entry {class preference constraints}{272}
+\entry {\code {CLASS{\_}LIKELY{\_}SPILLED{\_}P}}{346}
+\entry {\code {CLASS{\_}MAX{\_}NREGS}}{346}
+\entry {classes of RTX codes}{217}
+\entry {\code {CLEAR{\_}INSN{\_}CACHE}}{369}
+\entry {\code {clobber}}{240}
+\entry {\code {cmp\var {m}} instruction pattern}{283}
+\entry {\code {cmpstr\var {m}} instruction pattern}{283}
+\entry {code generation conventions}{74}
+\entry {code generation RTL sequences}{299}
+\entry {code motion}{211}
+\entry {\code {code{\_}label}}{247}
+\entry {\code {code{\_}label} and \samp {/i}}{221}
+\entry {\code {CODE{\_}LABEL{\_}NUMBER}}{247}
+\entry {codes, RTL expression}{215}
+\entry {\code {COImode}}{224}
+\entry {combiner pass}{230}
+\entry {command options}{17}
+\entry {common subexpression elimination}{211}
+\entry {\code {COMP{\_}TYPE{\_}ATTRIBUTES}}{415}
+\entry {\code {compare}}{232}
+\entry {\code {compare}, canonicalization of}{294}
+\entry {compilation in a separate directory}{101}
+\entry {compiler bugs, reporting}{189}
+\entry {compiler compared to C{\tt\char43}{\tt\char43} preprocessor}{15}
+\entry {compiler options, C{\tt\char43}{\tt\char43}}{28}
+\entry {compiler passes and files}{209}
+\entry {compiler version, specifying}{51}
+\entry {\code {COMPILER{\_}PATH}}{78}
+\entry {complement, bitwise}{234}
+\entry {complex numbers}{125}
+\entry {compound expressions as lvalues}{123}
+\entry {computed gotos}{117}
+\entry {computing the length of an insn}{312}
+\entry {\code {cond}}{236}
+\entry {\code {cond} and attributes}{307}
+\entry {condition code register}{231}
+\entry {condition code status}{376}
+\entry {condition codes}{235}
+\entry {conditional expressions as lvalues}{123}
+\entry {conditional expressions, extensions}{124}
+\entry {\code {CONDITIONAL{\_}REGISTER{\_}USAGE}}{335}
+\entry {conditions, in patterns}{258}
+\entry {configuration file}{417}
+\entry {configurations supported by GNU CC}{89}
+\entry {conflicting types}{178}
+\entry {\code {const} applied to function}{134}
+\entry {\code {const} function attribute}{135}
+\entry {\code {CONST{\_}CALL{\_}P}}{220}
+\entry {\code {CONST{\_}COSTS}}{378}
+\entry {\code {const{\_}double}}{226}
+\entry {\code {const{\_}double}, RTL sharing}{255}
+\entry {\code {CONST{\_}DOUBLE{\_}CHAIN}}{226}
+\entry {\code {CONST{\_}DOUBLE{\_}LOW}}{227}
+\entry {\code {CONST{\_}DOUBLE{\_}MEM}}{226}
+\entry {\code {CONST{\_}DOUBLE{\_}OK{\_}FOR{\_}LETTER{\_}P}}{346}
+\entry {\code {const{\_}int}}{226}
+\entry {\code {const{\_}int} and attribute tests}{307}
+\entry {\code {const{\_}int} and attributes}{306}
+\entry {\code {const{\_}int}, RTL sharing}{255}
+\entry {\code {CONST{\_}OK{\_}FOR{\_}LETTER{\_}P}}{346}
+\entry {\code {const{\_}string}}{227}
+\entry {\code {const{\_}string} and attributes}{307}
+\entry {\code {const{\_}true{\_}rtx}}{226}
+\entry {\code {const0{\_}rtx}}{226}
+\entry {\code {CONST0{\_}RTX}}{227}
+\entry {\code {const1{\_}rtx}}{226}
+\entry {\code {CONST1{\_}RTX}}{227}
+\entry {\code {const2{\_}rtx}}{226}
+\entry {\code {CONST2{\_}RTX}}{227}
+\entry {constant attributes}{314}
+\entry {constant folding}{209}
+\entry {constant folding and floating point}{409}
+\entry {constant propagation}{211}
+\entry {\code {CONSTANT{\_}ADDRESS{\_}P}}{373}
+\entry {\code {CONSTANT{\_}ALIGNMENT}}{328}
+\entry {\code {CONSTANT{\_}P}}{374}
+\entry {\code {CONSTANT{\_}POOL{\_}ADDRESS{\_}P}}{220}
+\entry {constants in constraints}{268}
+\entry {\code {constm1{\_}rtx}}{226}
+\entry {constraint modifier characters}{273}
+\entry {constraint, matching}{268}
+\entry {constraints}{267}
+\entry {constraints, machine specific}{274}
+\entry {constructing calls}{121}
+\entry {constructor expressions}{130}
+\entry {constructors vs \code {goto}}{158}
+\entry {constructors, automatic calls}{112}
+\entry {constructors, output of}{393}
 \entry {contributors}{9}
-\entry {controlling register usage}{341}
-\entry {controlling the compilation driver}{325}
-\entry {conventions, run-time}{213}
-\entry {conversions}{243}
-\entry {Convex options}{60}
-\entry {\code {copy{\_}rtx{\_}if{\_}shared}}{261}
-\entry {core dump}{193}
-\entry {\code {cos}}{27}
-\entry {costs of instructions}{385}
-\entry {\code {COSTS{\_}N{\_}INSNS}}{385}
-\entry {\code {CPLUS{\_}INCLUDE{\_}PATH}}{82}
-\entry {\code {CPP{\_}PREDEFINES}}{329}
-\entry {\code {CPP{\_}SPEC}}{325}
-\entry {\code {CQImode}}{230}
-\entry {cross compilation and floating point}{415}
-\entry {cross compiling}{54}
-\entry {cross-compiler, installation}{106}
-\entry {cross-jumping}{219}
-\entry {\code {CSImode}}{230}
-\entry {\code {CTImode}}{230}
-\entry {\code {CUMULATIVE{\_}ARGS}}{362}
-\entry {\code {current{\_}function{\_}epilogue{\_}delay{\_}list}}{370}
-\entry {\code {current{\_}function{\_}outgoing{\_}args{\_}size}}{359}
-\entry {\code {current{\_}function{\_}pops{\_}args}}{369}
-\entry {\code {current{\_}function{\_}pretend{\_}args{\_}size}}{368}
+\entry {controlling register usage}{335}
+\entry {controlling the compilation driver}{319}
+\entry {conventions, run-time}{207}
+\entry {conversions}{237}
+\entry {Convex options}{57}
+\entry {\code {copy{\_}rtx{\_}if{\_}shared}}{255}
+\entry {core dump}{187}
+\entry {\code {cos}}{25}
+\entry {costs of instructions}{378}
+\entry {\code {COSTS{\_}N{\_}INSNS}}{379}
+\entry {\code {CPLUS{\_}INCLUDE{\_}PATH}}{78}
+\entry {\code {CPP{\_}PREDEFINES}}{323}
+\entry {\code {CPP{\_}SPEC}}{319}
+\entry {\code {CQImode}}{224}
+\entry {cross compilation and floating point}{408}
+\entry {cross compiling}{51}
+\entry {cross-compiler, installation}{102}
+\entry {cross-jumping}{213}
+\entry {\code {CSImode}}{224}
+\entry {\code {CTImode}}{224}
+\entry {\code {CUMULATIVE{\_}ARGS}}{356}
+\entry {\code {current{\_}function{\_}epilogue{\_}delay{\_}list}}{363}
+\entry {\code {current{\_}function{\_}outgoing{\_}args{\_}size}}{352}
+\entry {\code {current{\_}function{\_}pops{\_}args}}{363}
+\entry {\code {current{\_}function{\_}pretend{\_}args{\_}size}}{362}
 \initial {D}
-\entry {\samp {d} in constraint}{273}
-\entry {data flow analysis}{217}
-\entry {\code {DATA{\_}ALIGNMENT}}{334}
-\entry {\code {data{\_}section}}{388}
-\entry {\code {DATA{\_}SECTION{\_}ASM{\_}OP}}{388}
-\entry {\code {DBR{\_}OUTPUT{\_}SEQEND}}{405}
-\entry {\code {dbr{\_}sequence{\_}length}}{405}
-\entry {DBX}{175}
-\entry {\code {DBX{\_}BLOCKS{\_}FUNCTION{\_}RELATIVE}}{411}
-\entry {\code {DBX{\_}CONTIN{\_}CHAR}}{410}
-\entry {\code {DBX{\_}CONTIN{\_}LENGTH}}{410}
-\entry {\code {DBX{\_}DEBUGGING{\_}INFO}}{409}
-\entry {\code {DBX{\_}FUNCTION{\_}FIRST}}{411}
-\entry {\code {DBX{\_}LBRAC{\_}FIRST}}{411}
-\entry {\code {DBX{\_}MEMPARM{\_}STABS{\_}LETTER}}{411}
-\entry {\code {DBX{\_}NO{\_}XREFS}}{410}
-\entry {\code {DBX{\_}OUTPUT{\_}ENUM}}{412}
-\entry {\code {DBX{\_}OUTPUT{\_}FUNCTION{\_}END}}{412}
-\entry {\code {DBX{\_}OUTPUT{\_}LBRAC}}{411}
-\entry {\code {DBX{\_}OUTPUT{\_}MAIN{\_}SOURCE{\_}DIRECTORY}}{413}
-\entry {\code {DBX{\_}OUTPUT{\_}MAIN{\_}SOURCE{\_}FILE{\_}END}}{413}
-\entry {\code {DBX{\_}OUTPUT{\_}MAIN{\_}SOURCE{\_}FILENAME}}{413}
-\entry {\code {DBX{\_}OUTPUT{\_}RBRAC}}{411}
-\entry {\code {DBX{\_}OUTPUT{\_}SOURCE{\_}FILENAME}}{413}
-\entry {\code {DBX{\_}OUTPUT{\_}STANDARD{\_}TYPES}}{412}
-\entry {\code {DBX{\_}REGISTER{\_}NUMBER}}{408}
-\entry {\code {DBX{\_}REGPARM{\_}STABS{\_}CODE}}{411}
-\entry {\code {DBX{\_}REGPARM{\_}STABS{\_}LETTER}}{411}
-\entry {\code {DBX{\_}STATIC{\_}CONST{\_}VAR{\_}CODE}}{410}
-\entry {\code {DBX{\_}STATIC{\_}STAB{\_}DATA{\_}SECTION}}{410}
-\entry {\code {DBX{\_}TYPE{\_}DECL{\_}STABS{\_}CODE}}{410}
-\entry {\code {DBX{\_}WORKING{\_}DIRECTORY}}{413}
-\entry {\code {DCmode}}{229}
-\entry {De Morgan's law}{300}
-\entry {dead code}{216}
-\entry {\code {dead{\_}or{\_}set{\_}p}}{303}
-\entry {deallocating variable length arrays}{131}
-\entry {death notes}{346}
-\entry {\code {debug{\_}rtx}}{198}
-\entry {\code {DEBUG{\_}SYMS{\_}TEXT}}{409}
-\entry {\code {DEBUGGER{\_}ARG{\_}OFFSET}}{409}
-\entry {\code {DEBUGGER{\_}AUTO{\_}OFFSET}}{409}
-\entry {debugging information generation}{219}
-\entry {debugging information options}{41}
-\entry {debugging, 88k OCS}{64}
-\entry {declaration scope}{181}
-\entry {declarations inside expressions}{119}
-\entry {declarations, RTL}{244}
-\entry {declaring attributes of functions}{138}
-\entry {declaring static data in C{\tt\char43}{\tt\char43}}{186}
-\entry {default implementation, signature member function}{167}
-\entry {\code {DEFAULT{\_}CALLER{\_}SAVES}}{367}
-\entry {\code {DEFAULT{\_}GDB{\_}EXTENSIONS}}{409}
-\entry {\code {DEFAULT{\_}MAIN{\_}RETURN}}{422}
-\entry {\code {DEFAULT{\_}PCC{\_}STRUCT{\_}RETURN}}{365}
-\entry {\code {DEFAULT{\_}SHORT{\_}ENUMS}}{339}
-\entry {\code {DEFAULT{\_}SIGNED{\_}CHAR}}{338}
-\entry {\code {define{\_}asm{\_}attributes}}{317}
-\entry {\code {define{\_}attr}}{311}
-\entry {\code {define{\_}delay}}{321}
-\entry {\code {define{\_}expand}}{305}
-\entry {\code {define{\_}function{\_}unit}}{322}
-\entry {\code {define{\_}insn}}{263}
-\entry {\code {define{\_}insn} example}{264}
-\entry {\code {define{\_}peephole}}{305}
-\entry {define{\_}split}{308}
-\entry {defining attributes and their values}{311}
-\entry {defining jump instruction patterns}{298}
-\entry {defining peephole optimizers}{301}
-\entry {defining RTL sequences for code generation}{305}
-\entry {defining static data in C{\tt\char43}{\tt\char43}}{186}
-\entry {delay slots, defining}{320}
-\entry {\code {DELAY{\_}SLOTS{\_}FOR{\_}EPILOGUE}}{369}
-\entry {delayed branch scheduling}{219}
-\entry {dependencies for make as output}{82}
-\entry {dependencies, make}{50}
-\entry {\code {DEPENDENCIES{\_}OUTPUT}}{82}
-\entry {Dependent Patterns}{296}
-\entry {destructors vs \code {goto}}{162}
-\entry {destructors, output of}{399}
-\entry {detecting \w {\samp {-traditional}}}{29}
-\entry {\code {DFmode}}{229}
-\entry {dialect options}{27}
-\entry {digits in constraint}{274}
-\entry {\code {DImode}}{229}
-\entry {\code {DIR{\_}SEPARATOR}}{427}
-\entry {directory options}{53}
-\entry {disabling certain registers}{341}
-\entry {dispatch table}{406}
-\entry {\code {div}}{239}
-\entry {\code {div} and attributes}{313}
-\entry {\code {DIVDI3{\_}LIBCALL}}{377}
-\entry {divide instruction, 88k}{66}
-\entry {division}{239}
-\entry {\code {div\var {m}3} instruction pattern}{288}
-\entry {\code {divmod\var {m}4} instruction pattern}{288}
-\entry {\code {DIVSI3{\_}LIBCALL}}{376}
-\entry {dollar signs in identifier names}{142}
-\entry {\code {DOLLARS{\_}IN{\_}IDENTIFIERS}}{422}
-\entry {\code {DONE}}{306}
-\entry {\code {DONT{\_}DECLARE{\_}SYS{\_}SIGLIST}}{427}
-\entry {\code {DONT{\_}REDUCE{\_}ADDR}}{387}
-\entry {double-word arithmetic}{129}
-\entry {\code {DOUBLE{\_}TYPE{\_}SIZE}}{338}
-\entry {downward funargs}{122}
-\entry {driver}{325}
-\entry {DW bit (29k)}{62}
-\entry {\code {DWARF{\_}DEBUGGING{\_}INFO}}{414}
-\entry {\code {DYNAMIC{\_}CHAIN{\_}ADDRESS}}{354}
+\entry {\samp {d} in constraint}{267}
+\entry {data flow analysis}{211}
+\entry {\code {DATA{\_}ALIGNMENT}}{328}
+\entry {\code {data{\_}section}}{382}
+\entry {\code {DATA{\_}SECTION{\_}ASM{\_}OP}}{382}
+\entry {\code {DBR{\_}OUTPUT{\_}SEQEND}}{398}
+\entry {\code {dbr{\_}sequence{\_}length}}{398}
+\entry {DBX}{169}
+\entry {\code {DBX{\_}CONTIN{\_}CHAR}}{403}
+\entry {\code {DBX{\_}CONTIN{\_}LENGTH}}{403}
+\entry {\code {DBX{\_}DEBUGGING{\_}INFO}}{403}
+\entry {\code {DBX{\_}FUNCTION{\_}FIRST}}{404}
+\entry {\code {DBX{\_}LBRAC{\_}FIRST}}{404}
+\entry {\code {DBX{\_}MEMPARM{\_}STABS{\_}LETTER}}{404}
+\entry {\code {DBX{\_}NO{\_}XREFS}}{403}
+\entry {\code {DBX{\_}OUTPUT{\_}ENUM}}{405}
+\entry {\code {DBX{\_}OUTPUT{\_}FUNCTION{\_}END}}{405}
+\entry {\code {DBX{\_}OUTPUT{\_}LBRAC}}{405}
+\entry {\code {DBX{\_}OUTPUT{\_}MAIN{\_}SOURCE{\_}DIRECTORY}}{406}
+\entry {\code {DBX{\_}OUTPUT{\_}MAIN{\_}SOURCE{\_}FILE{\_}END}}{406}
+\entry {\code {DBX{\_}OUTPUT{\_}MAIN{\_}SOURCE{\_}FILENAME}}{406}
+\entry {\code {DBX{\_}OUTPUT{\_}RBRAC}}{405}
+\entry {\code {DBX{\_}OUTPUT{\_}SOURCE{\_}FILENAME}}{406}
+\entry {\code {DBX{\_}OUTPUT{\_}STANDARD{\_}TYPES}}{405}
+\entry {\code {DBX{\_}REGISTER{\_}NUMBER}}{402}
+\entry {\code {DBX{\_}REGPARM{\_}STABS{\_}CODE}}{404}
+\entry {\code {DBX{\_}REGPARM{\_}STABS{\_}LETTER}}{404}
+\entry {\code {DBX{\_}STATIC{\_}CONST{\_}VAR{\_}CODE}}{404}
+\entry {\code {DBX{\_}STATIC{\_}STAB{\_}DATA{\_}SECTION}}{404}
+\entry {\code {DBX{\_}TYPE{\_}DECL{\_}STABS{\_}CODE}}{404}
+\entry {\code {DBX{\_}WORKING{\_}DIRECTORY}}{406}
+\entry {\code {DCmode}}{223}
+\entry {De Morgan's law}{294}
+\entry {dead code}{210}
+\entry {\code {dead{\_}or{\_}set{\_}p}}{297}
+\entry {deallocating variable length arrays}{127}
+\entry {death notes}{340}
+\entry {\code {debug{\_}rtx}}{192}
+\entry {\code {DEBUG{\_}SYMS{\_}TEXT}}{403}
+\entry {\code {DEBUGGER{\_}ARG{\_}OFFSET}}{402}
+\entry {\code {DEBUGGER{\_}AUTO{\_}OFFSET}}{402}
+\entry {debugging information generation}{213}
+\entry {debugging information options}{37}
+\entry {debugging, 88k OCS}{61}
+\entry {declaration scope}{175}
+\entry {declarations inside expressions}{115}
+\entry {declarations, RTL}{238}
+\entry {declaring attributes of functions}{134}
+\entry {declaring static data in C{\tt\char43}{\tt\char43}}{180}
+\entry {default implementation, signature member function}{161}
+\entry {\code {DEFAULT{\_}CALLER{\_}SAVES}}{360}
+\entry {\code {DEFAULT{\_}GDB{\_}EXTENSIONS}}{403}
+\entry {\code {DEFAULT{\_}MAIN{\_}RETURN}}{415}
+\entry {\code {DEFAULT{\_}PCC{\_}STRUCT{\_}RETURN}}{359}
+\entry {\code {DEFAULT{\_}SHORT{\_}ENUMS}}{333}
+\entry {\code {DEFAULT{\_}SIGNED{\_}CHAR}}{332}
+\entry {\code {define{\_}asm{\_}attributes}}{311}
+\entry {\code {define{\_}attr}}{305}
+\entry {\code {define{\_}delay}}{315}
+\entry {\code {define{\_}expand}}{299}
+\entry {\code {define{\_}function{\_}unit}}{316}
+\entry {\code {define{\_}insn}}{257}
+\entry {\code {define{\_}insn} example}{258}
+\entry {\code {define{\_}peephole}}{299}
+\entry {define{\_}split}{302}
+\entry {defining attributes and their values}{305}
+\entry {defining jump instruction patterns}{292}
+\entry {defining peephole optimizers}{295}
+\entry {defining RTL sequences for code generation}{299}
+\entry {defining static data in C{\tt\char43}{\tt\char43}}{180}
+\entry {delay slots, defining}{314}
+\entry {\code {DELAY{\_}SLOTS{\_}FOR{\_}EPILOGUE}}{363}
+\entry {delayed branch scheduling}{213}
+\entry {dependencies for make as output}{78}
+\entry {dependencies, make}{47}
+\entry {\code {DEPENDENCIES{\_}OUTPUT}}{78}
+\entry {Dependent Patterns}{290}
+\entry {destructors vs \code {goto}}{158}
+\entry {destructors, output of}{393}
+\entry {detecting \w {\samp {-traditional}}}{27}
+\entry {\code {DFmode}}{223}
+\entry {dialect options}{25}
+\entry {digits in constraint}{268}
+\entry {\code {DImode}}{223}
+\entry {directory options}{50}
+\entry {disabling certain registers}{335}
+\entry {dispatch table}{400}
+\entry {\code {div}}{233}
+\entry {\code {div} and attributes}{307}
+\entry {\code {DIVDI3{\_}LIBCALL}}{371}
+\entry {divide instruction, 88k}{62}
+\entry {division}{233}
+\entry {\code {div\var {m}3} instruction pattern}{282}
+\entry {\code {divmod\var {m}4} instruction pattern}{282}
+\entry {\code {DIVSI3{\_}LIBCALL}}{370}
+\entry {dollar signs in identifier names}{138}
+\entry {\code {DOLLARS{\_}IN{\_}IDENTIFIERS}}{415}
+\entry {\code {DONE}}{300}
+\entry {\code {DONT{\_}DECLARE{\_}SYS{\_}SIGLIST}}{419}
+\entry {\code {DONT{\_}REDUCE{\_}ADDR}}{381}
+\entry {double-word arithmetic}{125}
+\entry {\code {DOUBLE{\_}TYPE{\_}SIZE}}{332}
+\entry {downward funargs}{118}
+\entry {driver}{319}
+\entry {DW bit (29k)}{58}
+\entry {\code {DWARF{\_}DEBUGGING{\_}INFO}}{407}
+\entry {\code {DYNAMIC{\_}CHAIN{\_}ADDRESS}}{348}
 \initial {E}
-\entry {\samp {E} in constraint}{274}
-\entry {\code {EASY{\_}DIV{\_}EXPR}}{419}
-\entry {\code {EDOM}, implicit usage}{377}
-\entry {\code {ELIGIBLE{\_}FOR{\_}EPILOGUE{\_}DELAY}}{369}
-\entry {\code {ELIMINABLE{\_}REGS}}{357}
-\entry {empty constraints}{285}
-\entry {\code {EMPTY{\_}FIELD{\_}BOUNDARY}}{335}
-\entry {\code {ENCODE{\_}SECTION{\_}INFO}}{389}
-\entry {\code {ENCODE{\_}SECTION{\_}INFO} and address validation}{381}
-\entry {\code {ENCODE{\_}SECTION{\_}INFO} usage}{405}
-\entry {\code {ENDFILE{\_}SPEC}}{327}
-\entry {endianness}{211}
-\entry {\code {enum machine{\_}mode}}{228}
-\entry {\code {enum reg{\_}class}}{348}
-\entry {enumeration clash warnings}{38}
-\entry {environment variables}{81}
-\entry {epilogue}{367}
-\entry {\code {eq}}{242}
-\entry {\code {eq} and attributes}{313}
-\entry {\code {eq{\_}attr}}{314}
-\entry {equal}{242}
-\entry {\code {errno}, implicit usage}{378}
-\entry {error messages}{191}
-\entry {escape sequences, traditional}{28}
-\entry {exclamation point}{278}
-\entry {exclusive-or, bitwise}{240}
-\entry {\code {EXECUTABLE{\_}SUFFIX}}{426}
-\entry {\code {exit}}{27}
-\entry {exit status and VMS}{209}
-\entry {\code {EXIT{\_}BODY}}{423}
-\entry {\code {EXIT{\_}IGNORE{\_}STACK}}{368}
-\entry {\code {EXPAND{\_}BUILTIN{\_}SAVEREGS}}{373}
-\entry {expander definitions}{305}
-\entry {explicit register variables}{152}
-\entry {\code {expr{\_}list}}{259}
-\entry {expression codes}{221}
-\entry {expressions containing statements}{119}
-\entry {expressions, compound, as lvalues}{127}
-\entry {expressions, conditional, as lvalues}{127}
-\entry {expressions, constructor}{134}
-\entry {extended \code {asm}}{147}
-\entry {\code {extend\var {mn}} instruction pattern}{290}
-\entry {extensible constraints}{275}
-\entry {extensions, \code {?:}}{127, 128}
-\entry {extensions, C language}{119}
-\entry {extensions, C{\tt\char43}{\tt\char43} language}{159}
-\entry {\code {extern int target{\_}flags}}{330}
-\entry {external declaration scope}{181}
-\entry {\code {EXTRA{\_}CC{\_}MODES}}{383}
-\entry {\code {EXTRA{\_}CC{\_}NAMES}}{384}
-\entry {\code {EXTRA{\_}CONSTRAINT}}{353}
-\entry {\code {EXTRA{\_}SECTION{\_}FUNCTIONS}}{388}
-\entry {\code {EXTRA{\_}SECTIONS}}{388}
-\entry {\code {extv} instruction pattern}{291}
-\entry {\code {extzv} instruction pattern}{291}
+\entry {\samp {E} in constraint}{268}
+\entry {\code {EASY{\_}DIV{\_}EXPR}}{411}
+\entry {\code {EDOM}, implicit usage}{371}
+\entry {\code {ELIGIBLE{\_}FOR{\_}EPILOGUE{\_}DELAY}}{363}
+\entry {\code {ELIMINABLE{\_}REGS}}{351}
+\entry {empty constraints}{279}
+\entry {\code {EMPTY{\_}FIELD{\_}BOUNDARY}}{328}
+\entry {\code {ENCODE{\_}SECTION{\_}INFO}}{383}
+\entry {\code {ENCODE{\_}SECTION{\_}INFO} and address validation}{374}
+\entry {\code {ENCODE{\_}SECTION{\_}INFO} usage}{398}
+\entry {\code {ENDFILE{\_}SPEC}}{321}
+\entry {endianness}{205}
+\entry {\code {enum machine{\_}mode}}{222}
+\entry {\code {enum reg{\_}class}}{342}
+\entry {enumeration clash warnings}{35}
+\entry {environment variables}{77}
+\entry {epilogue}{361}
+\entry {\code {eq}}{236}
+\entry {\code {eq} and attributes}{307}
+\entry {\code {eq{\_}attr}}{308}
+\entry {equal}{236}
+\entry {\code {errno}, implicit usage}{371}
+\entry {error messages}{186}
+\entry {escape sequences, traditional}{26}
+\entry {exclamation point}{272}
+\entry {exclusive-or, bitwise}{234}
+\entry {\code {EXECUTABLE{\_}SUFFIX}}{418}
+\entry {\code {exit}}{25}
+\entry {exit status and VMS}{203}
+\entry {\code {EXIT{\_}BODY}}{416}
+\entry {\code {EXIT{\_}IGNORE{\_}STACK}}{362}
+\entry {\code {EXPAND{\_}BUILTIN{\_}SAVEREGS}}{366}
+\entry {expander definitions}{299}
+\entry {explicit register variables}{148}
+\entry {\code {expr{\_}list}}{253}
+\entry {expression codes}{215}
+\entry {expressions containing statements}{115}
+\entry {expressions, compound, as lvalues}{123}
+\entry {expressions, conditional, as lvalues}{123}
+\entry {expressions, constructor}{130}
+\entry {extended \code {asm}}{143}
+\entry {\code {extend\var {mn}} instruction pattern}{284}
+\entry {extensible constraints}{269}
+\entry {extensions, \code {?:}}{123, 124}
+\entry {extensions, C language}{115}
+\entry {extensions, C{\tt\char43}{\tt\char43} language}{155}
+\entry {\code {extern int target{\_}flags}}{324}
+\entry {external declaration scope}{175}
+\entry {\code {EXTRA{\_}CC{\_}MODES}}{377}
+\entry {\code {EXTRA{\_}CC{\_}NAMES}}{377}
+\entry {\code {EXTRA{\_}CONSTRAINT}}{347}
+\entry {\code {EXTRA{\_}SECTION{\_}FUNCTIONS}}{382}
+\entry {\code {EXTRA{\_}SECTIONS}}{382}
+\entry {\code {extv} instruction pattern}{285}
+\entry {\code {extzv} instruction pattern}{285}
 \initial {F}
-\entry {\samp {F} in constraint}{274}
-\entry {\code {fabs}}{27}
-\entry {\code {FAIL}}{306}
-\entry {\code {FAILURE{\_}EXIT{\_}CODE}}{425}
-\entry {fatal signal}{193}
-\entry {features, optional, in system conventions}{330}
-\entry {\code {ffs}}{27, 241}
-\entry {\code {ffs\var {m}2} instruction pattern}{289}
-\entry {file name suffix}{24}
-\entry {file names}{51}
-\entry {files and passes of the compiler}{215}
-\entry {final pass}{219}
-\entry {\code {FINAL{\_}PRESCAN{\_}INSN}}{404}
-\entry {\code {FINAL{\_}REG{\_}PARM{\_}STACK{\_}SPACE}}{359}
-\entry {\code {final{\_}scan{\_}insn}}{370}
-\entry {\code {final{\_}sequence}}{405}
-\entry {\code {FINALIZE{\_}PIC}}{390}
-\entry {\code {FIRST{\_}INSN{\_}ADDRESS}}{319}
-\entry {\code {FIRST{\_}PARM{\_}OFFSET}}{354}
-\entry {\code {FIRST{\_}PARM{\_}OFFSET} and virtual registers}{235}
-\entry {\code {FIRST{\_}PSEUDO{\_}REGISTER}}{340}
-\entry {\code {FIRST{\_}STACK{\_}REG}}{345}
-\entry {\code {FIRST{\_}VIRTUAL{\_}REGISTER}}{235}
-\entry {\code {fix}}{244}
-\entry {\code {fix{\_}trunc\var {mn}2} instruction pattern}{290}
-\entry {fixed register}{341}
-\entry {\code {FIXED{\_}REGISTERS}}{341}
-\entry {\code {fixed{\_}regs}}{341}
-\entry {\code {fix\var {mn}2} instruction pattern}{290}
-\entry {\code {FIXUNS{\_}TRUNC{\_}LIKE{\_}FIX{\_}TRUNC}}{418}
-\entry {\code {fixuns{\_}trunc\var {mn}2} instruction pattern}{290}
-\entry {\code {fixuns\var {mn}2} instruction pattern}{290}
-\entry {flags in RTL expression}{225}
-\entry {\code {float}}{244}
-\entry {\code {float} as function value type}{182}
-\entry {\code {FLOAT{\_}ARG{\_}TYPE}}{378}
-\entry {\code {float{\_}extend}}{244}
-\entry {\code {FLOAT{\_}STORE{\_}FLAG{\_}VALUE}}{421}
-\entry {\code {float{\_}truncate}}{244}
-\entry {\code {FLOAT{\_}TYPE{\_}SIZE}}{338}
-\entry {\code {FLOAT{\_}VALUE{\_}TYPE}}{378}
-\entry {\code {FLOAT{\_}WORDS{\_}BIG{\_}ENDIAN}}{332}
-\entry {\code {FLOATIFY}}{378}
-\entry {floating point and cross compilation}{415}
-\entry {\code {float\var {mn}2} instruction pattern}{290}
-\entry {\code {floatuns\var {mn}2} instruction pattern}{290}
-\entry {\code {force{\_}reg}}{286}
-\entry {\code {format} function attribute}{140}
-\entry {forwarding calls}{125}
-\entry {frame layout}{353}
-\entry {\code {FRAME{\_}GROWS{\_}DOWNWARD}}{354}
-\entry {\code {FRAME{\_}GROWS{\_}DOWNWARD} and virtual registers}{235}
-\entry {\code {frame{\_}pointer{\_}needed}}{367}
-\entry {\code {FRAME{\_}POINTER{\_}REGNUM}}{355}
-\entry {\code {FRAME{\_}POINTER{\_}REGNUM} and virtual registers}{235}
-\entry {\code {FRAME{\_}POINTER{\_}REQUIRED}}{357}
-\entry {\code {frame{\_}pointer{\_}rtx}}{356}
-\entry {\code {fscanf}, and constant strings}{180}
-\entry {\code {ftrunc\var {m}2} instruction pattern}{290}
-\entry {function attributes}{138}
-\entry {function call conventions}{213}
-\entry {function entry and exit}{367}
-\entry {function pointers, arithmetic}{133}
-\entry {function prototype declarations}{141}
-\entry {function units, for scheduling}{322}
-\entry {function, size of pointer to}{133}
-\entry {function-call insns}{259}
-\entry {\code {FUNCTION{\_}ARG}}{360}
-\entry {\code {FUNCTION{\_}ARG{\_}ADVANCE}}{363}
-\entry {\code {FUNCTION{\_}ARG{\_}BOUNDARY}}{363}
-\entry {\code {FUNCTION{\_}ARG{\_}CALLEE{\_}COPIES}}{362}
-\entry {\code {FUNCTION{\_}ARG{\_}PADDING}}{363}
-\entry {\code {FUNCTION{\_}ARG{\_}PARTIAL{\_}NREGS}}{361}
-\entry {\code {FUNCTION{\_}ARG{\_}PASS{\_}BY{\_}REFERENCE}}{362}
-\entry {\code {FUNCTION{\_}ARG{\_}REGNO{\_}P}}{363}
-\entry {\code {FUNCTION{\_}BLOCK{\_}PROFILER}}{370}
-\entry {\code {FUNCTION{\_}BOUNDARY}}{334}
-\entry {\code {FUNCTION{\_}CONVERSION{\_}BUG}}{426}
-\entry {\code {FUNCTION{\_}EPILOGUE}}{368}
-\entry {\code {FUNCTION{\_}EPILOGUE} and trampolines}{374}
-\entry {\code {FUNCTION{\_}INCOMING{\_}ARG}}{361}
-\entry {\code {FUNCTION{\_}MODE}}{421}
-\entry {\code {FUNCTION{\_}OUTGOING{\_}VALUE}}{364}
-\entry {\code {FUNCTION{\_}PROFILER}}{370}
-\entry {\code {FUNCTION{\_}PROLOGUE}}{367}
-\entry {\code {FUNCTION{\_}PROLOGUE} and trampolines}{374}
-\entry {\code {FUNCTION{\_}VALUE}}{364}
-\entry {\code {FUNCTION{\_}VALUE{\_}REGNO{\_}P}}{364}
-\entry {functions in arbitrary sections}{138}
-\entry {functions that have no side effects}{138}
-\entry {functions that never return}{138}
-\entry {functions with \code {printf} or \code {scanf} style arguments}{138}
-\entry {functions, leaf}{344}
+\entry {\samp {F} in constraint}{268}
+\entry {\code {fabs}}{25}
+\entry {\code {FAIL}}{300}
+\entry {\code {FAILURE{\_}EXIT{\_}CODE}}{417}
+\entry {fatal signal}{187}
+\entry {features, optional, in system conventions}{324}
+\entry {\code {ffs}}{25, 235}
+\entry {\code {ffs\var {m}2} instruction pattern}{283}
+\entry {file name suffix}{22}
+\entry {file names}{48}
+\entry {files and passes of the compiler}{209}
+\entry {final pass}{213}
+\entry {\code {FINAL{\_}PRESCAN{\_}INSN}}{397}
+\entry {\code {FINAL{\_}REG{\_}PARM{\_}STACK{\_}SPACE}}{353}
+\entry {\code {final{\_}scan{\_}insn}}{363}
+\entry {\code {final{\_}sequence}}{399}
+\entry {\code {FINALIZE{\_}PIC}}{384}
+\entry {\code {FIRST{\_}INSN{\_}ADDRESS}}{313}
+\entry {\code {FIRST{\_}PARM{\_}OFFSET}}{348}
+\entry {\code {FIRST{\_}PARM{\_}OFFSET} and virtual registers}{229}
+\entry {\code {FIRST{\_}PSEUDO{\_}REGISTER}}{334}
+\entry {\code {FIRST{\_}STACK{\_}REG}}{339}
+\entry {\code {FIRST{\_}VIRTUAL{\_}REGISTER}}{229}
+\entry {\code {fix}}{238}
+\entry {\code {fix{\_}trunc\var {mn}2} instruction pattern}{284}
+\entry {fixed register}{335}
+\entry {\code {FIXED{\_}REGISTERS}}{335}
+\entry {\code {fixed{\_}regs}}{335}
+\entry {\code {fix\var {mn}2} instruction pattern}{284}
+\entry {\code {FIXUNS{\_}TRUNC{\_}LIKE{\_}FIX{\_}TRUNC}}{411}
+\entry {\code {fixuns{\_}trunc\var {mn}2} instruction pattern}{284}
+\entry {\code {fixuns\var {mn}2} instruction pattern}{284}
+\entry {flags in RTL expression}{219}
+\entry {\code {float}}{238}
+\entry {\code {float} as function value type}{176}
+\entry {\code {FLOAT{\_}ARG{\_}TYPE}}{372}
+\entry {\code {float{\_}extend}}{238}
+\entry {\code {FLOAT{\_}STORE{\_}FLAG{\_}VALUE}}{414}
+\entry {\code {float{\_}truncate}}{238}
+\entry {\code {FLOAT{\_}TYPE{\_}SIZE}}{332}
+\entry {\code {FLOAT{\_}VALUE{\_}TYPE}}{372}
+\entry {\code {FLOAT{\_}WORDS{\_}BIG{\_}ENDIAN}}{326}
+\entry {\code {FLOATIFY}}{372}
+\entry {floating point and cross compilation}{408}
+\entry {\code {float\var {mn}2} instruction pattern}{284}
+\entry {\code {floatuns\var {mn}2} instruction pattern}{284}
+\entry {\code {force{\_}reg}}{280}
+\entry {\code {format} function attribute}{136}
+\entry {forwarding calls}{121}
+\entry {frame layout}{347}
+\entry {\code {FRAME{\_}GROWS{\_}DOWNWARD}}{347}
+\entry {\code {FRAME{\_}GROWS{\_}DOWNWARD} and virtual registers}{229}
+\entry {\code {frame{\_}pointer{\_}needed}}{361}
+\entry {\code {FRAME{\_}POINTER{\_}REGNUM}}{349}
+\entry {\code {FRAME{\_}POINTER{\_}REGNUM} and virtual registers}{229}
+\entry {\code {FRAME{\_}POINTER{\_}REQUIRED}}{350}
+\entry {\code {frame{\_}pointer{\_}rtx}}{350}
+\entry {\code {fscanf}, and constant strings}{174}
+\entry {\code {ftrunc\var {m}2} instruction pattern}{284}
+\entry {function attributes}{134}
+\entry {function call conventions}{207}
+\entry {function entry and exit}{361}
+\entry {function pointers, arithmetic}{129}
+\entry {function prototype declarations}{137}
+\entry {function units, for scheduling}{316}
+\entry {function, size of pointer to}{129}
+\entry {function-call insns}{253}
+\entry {\code {FUNCTION{\_}ARG}}{354}
+\entry {\code {FUNCTION{\_}ARG{\_}ADVANCE}}{356}
+\entry {\code {FUNCTION{\_}ARG{\_}BOUNDARY}}{357}
+\entry {\code {FUNCTION{\_}ARG{\_}CALLEE{\_}COPIES}}{355}
+\entry {\code {FUNCTION{\_}ARG{\_}PADDING}}{356}
+\entry {\code {FUNCTION{\_}ARG{\_}PARTIAL{\_}NREGS}}{355}
+\entry {\code {FUNCTION{\_}ARG{\_}PASS{\_}BY{\_}REFERENCE}}{355}
+\entry {\code {FUNCTION{\_}ARG{\_}REGNO{\_}P}}{357}
+\entry {\code {FUNCTION{\_}BLOCK{\_}PROFILER}}{364}
+\entry {\code {FUNCTION{\_}BOUNDARY}}{328}
+\entry {\code {FUNCTION{\_}CONVERSION{\_}BUG}}{418}
+\entry {\code {FUNCTION{\_}EPILOGUE}}{362}
+\entry {\code {FUNCTION{\_}EPILOGUE} and trampolines}{368}
+\entry {\code {FUNCTION{\_}INCOMING{\_}ARG}}{355}
+\entry {\code {FUNCTION{\_}MODE}}{414}
+\entry {\code {FUNCTION{\_}OUTGOING{\_}VALUE}}{358}
+\entry {\code {FUNCTION{\_}PROFILER}}{364}
+\entry {\code {FUNCTION{\_}PROLOGUE}}{361}
+\entry {\code {FUNCTION{\_}PROLOGUE} and trampolines}{368}
+\entry {\code {FUNCTION{\_}VALUE}}{357}
+\entry {\code {FUNCTION{\_}VALUE{\_}REGNO{\_}P}}{358}
+\entry {functions in arbitrary sections}{134}
+\entry {functions that have no side effects}{134}
+\entry {functions that never return}{134}
+\entry {functions with \code {printf} or \code {scanf} style arguments}{134}
+\entry {functions, leaf}{338}
 \initial {G}
-\entry {\samp {g} in constraint}{274}
-\entry {\samp {G} in constraint}{274}
-\entry {\code {g{\tt\char43}{\tt\char43}}}{26}
-\entry {G{\tt\char43}{\tt\char43}}{17}
-\entry {\code {g{\tt\char43}{\tt\char43} 1.\var {xx}}}{26}
-\entry {\code {g{\tt\char43}{\tt\char43}} older version}{26}
-\entry {\code {g{\tt\char43}{\tt\char43}}, separate compiler}{26}
-\entry {GCC}{17}
-\entry {\code {GCC{\_}EXEC{\_}PREFIX}}{81}
-\entry {\code {ge}}{242}
-\entry {\code {ge} and attributes}{313}
-\entry {\code {GEN{\_}ERRNO{\_}RTX}}{378}
-\entry {\code {gencodes}}{216}
-\entry {\code {genconfig}}{219}
-\entry {\code {general{\_}operand}}{266}
-\entry {\code {GENERAL{\_}REGS}}{347}
-\entry {generalized lvalues}{127}
-\entry {generating assembler output}{271}
-\entry {generating insns}{265}
-\entry {\code {genflags}}{216}
-\entry {\code {genflags}, crash on Sun 4}{171}
-\entry {\code {get{\_}attr}}{314}
-\entry {\code {get{\_}attr{\_}length}}{319}
-\entry {\code {GET{\_}CLASS{\_}NARROWEST{\_}MODE}}{232}
-\entry {\code {GET{\_}CODE}}{221}
-\entry {\code {get{\_}frame{\_}size}}{357}
-\entry {\code {get{\_}insns}}{252}
-\entry {\code {get{\_}last{\_}insn}}{252}
-\entry {\code {GET{\_}MODE}}{231}
-\entry {\code {GET{\_}MODE{\_}ALIGNMENT}}{231}
-\entry {\code {GET{\_}MODE{\_}BITSIZE}}{231}
-\entry {\code {GET{\_}MODE{\_}CLASS}}{231}
-\entry {\code {GET{\_}MODE{\_}MASK}}{231}
-\entry {\code {GET{\_}MODE{\_}NAME}}{231}
-\entry {\code {GET{\_}MODE{\_}NUNITS}}{231}
-\entry {\code {GET{\_}MODE{\_}SIZE}}{231}
-\entry {\code {GET{\_}MODE{\_}UNIT{\_}SIZE}}{231}
-\entry {\code {GET{\_}MODE{\_}WIDER{\_}MODE}}{231}
-\entry {\code {GET{\_}RTX{\_}CLASS}}{223}
-\entry {\code {GET{\_}RTX{\_}FORMAT}}{223}
-\entry {\code {GET{\_}RTX{\_}LENGTH}}{223}
-\entry {\code {geu}}{242}
-\entry {\code {geu} and attributes}{313}
-\entry {global offset table}{80}
-\entry {global register after \code {longjmp}}{154}
-\entry {global register allocation}{218}
-\entry {global register variables}{153}
-\entry {\code {GLOBALDEF}}{206}
-\entry {\code {GLOBALREF}}{206}
-\entry {\code {GLOBALVALUEDEF}}{206}
-\entry {\code {GLOBALVALUEREF}}{206}
-\entry {GNU CC and portability}{211}
-\entry {GNU CC command options}{19}
-\entry {\code {GO{\_}IF{\_}LEGITIMATE{\_}ADDRESS}}{380}
-\entry {\code {GO{\_}IF{\_}MODE{\_}DEPENDENT{\_}ADDRESS}}{382}
-\entry {\code {goto} in C{\tt\char43}{\tt\char43}}{162}
-\entry {goto with computed label}{121}
-\entry {gp-relative references (MIPS)}{73}
-\entry {\code {gprof}}{42}
-\entry {greater than}{242}
-\entry {grouping options}{19}
-\entry {\code {gt}}{242}
-\entry {\code {gt} and attributes}{313}
-\entry {\code {gtu}}{242}
-\entry {\code {gtu} and attributes}{313}
+\entry {\samp {g} in constraint}{268}
+\entry {\samp {G} in constraint}{268}
+\entry {\code {g{\tt\char43}{\tt\char43}}}{24}
+\entry {G{\tt\char43}{\tt\char43}}{15}
+\entry {\code {g{\tt\char43}{\tt\char43} 1.\var {xx}}}{24}
+\entry {\code {g{\tt\char43}{\tt\char43}} older version}{24}
+\entry {\code {g{\tt\char43}{\tt\char43}}, separate compiler}{24}
+\entry {GCC}{15}
+\entry {\code {GCC{\_}EXEC{\_}PREFIX}}{77}
+\entry {\code {ge}}{236}
+\entry {\code {ge} and attributes}{307}
+\entry {\code {GEN{\_}ERRNO{\_}RTX}}{371}
+\entry {\code {gencodes}}{210}
+\entry {\code {genconfig}}{213}
+\entry {\code {general{\_}operand}}{260}
+\entry {\code {GENERAL{\_}REGS}}{341}
+\entry {generalized lvalues}{123}
+\entry {generating assembler output}{265}
+\entry {generating insns}{259}
+\entry {\code {genflags}}{210}
+\entry {\code {genflags}, crash on Sun 4}{165}
+\entry {\code {get{\_}attr}}{308}
+\entry {\code {get{\_}attr{\_}length}}{313}
+\entry {\code {GET{\_}CLASS{\_}NARROWEST{\_}MODE}}{226}
+\entry {\code {GET{\_}CODE}}{215}
+\entry {\code {get{\_}frame{\_}size}}{351}
+\entry {\code {get{\_}insns}}{246}
+\entry {\code {get{\_}last{\_}insn}}{246}
+\entry {\code {GET{\_}MODE}}{225}
+\entry {\code {GET{\_}MODE{\_}ALIGNMENT}}{225}
+\entry {\code {GET{\_}MODE{\_}BITSIZE}}{225}
+\entry {\code {GET{\_}MODE{\_}CLASS}}{225}
+\entry {\code {GET{\_}MODE{\_}MASK}}{225}
+\entry {\code {GET{\_}MODE{\_}NAME}}{225}
+\entry {\code {GET{\_}MODE{\_}NUNITS}}{225}
+\entry {\code {GET{\_}MODE{\_}SIZE}}{225}
+\entry {\code {GET{\_}MODE{\_}UNIT{\_}SIZE}}{225}
+\entry {\code {GET{\_}MODE{\_}WIDER{\_}MODE}}{225}
+\entry {\code {GET{\_}RTX{\_}CLASS}}{217}
+\entry {\code {GET{\_}RTX{\_}FORMAT}}{217}
+\entry {\code {GET{\_}RTX{\_}LENGTH}}{217}
+\entry {\code {geu}}{236}
+\entry {\code {geu} and attributes}{307}
+\entry {global offset table}{75}
+\entry {global register after \code {longjmp}}{149}
+\entry {global register allocation}{212}
+\entry {global register variables}{148}
+\entry {\code {GLOBALDEF}}{200}
+\entry {\code {GLOBALREF}}{200}
+\entry {\code {GLOBALVALUEDEF}}{200}
+\entry {\code {GLOBALVALUEREF}}{200}
+\entry {GNU CC and portability}{205}
+\entry {GNU CC command options}{17}
+\entry {\code {GO{\_}IF{\_}LEGITIMATE{\_}ADDRESS}}{374}
+\entry {\code {GO{\_}IF{\_}MODE{\_}DEPENDENT{\_}ADDRESS}}{376}
+\entry {\code {goto} in C{\tt\char43}{\tt\char43}}{158}
+\entry {goto with computed label}{117}
+\entry {gp-relative references (MIPS)}{69}
+\entry {\code {gprof}}{39}
+\entry {greater than}{236}
+\entry {grouping options}{17}
+\entry {\code {gt}}{236}
+\entry {\code {gt} and attributes}{307}
+\entry {\code {gtu}}{236}
+\entry {\code {gtu} and attributes}{307}
 \initial {H}
-\entry {\samp {H} in constraint}{274}
-\entry {\code {HANDLE{\_}PRAGMA}}{422}
-\entry {hard registers}{234}
-\entry {\code {HARD{\_}FRAME{\_}POINTER{\_}REGNUM}}{355}
-\entry {\code {HARD{\_}REGNO{\_}MODE{\_}OK}}{343}
-\entry {\code {HARD{\_}REGNO{\_}NREGS}}{343}
-\entry {hardware models and configurations, specifying}{56}
-\entry {\code {HAS{\_}INIT{\_}SECTION}}{402}
-\entry {\code {HAVE{\_}ATEXIT}}{423}
-\entry {\code {HAVE{\_}POST{\_}DECREMENT}}{380}
-\entry {\code {HAVE{\_}POST{\_}INCREMENT}}{379}
-\entry {\code {HAVE{\_}PRE{\_}DECREMENT}}{380}
-\entry {\code {HAVE{\_}PRE{\_}INCREMENT}}{380}
-\entry {\code {HAVE{\_}PUTENV}}{426}
-\entry {\code {HAVE{\_}VPRINTF}}{426}
-\entry {header files and VMS}{205}
-\entry {\code {high}}{233}
-\entry {\code {HImode}}{229}
-\entry {\code {HImode}, in \code {insn}}{254}
-\entry {\code {HOST{\_}BITS{\_}PER{\_}CHAR}}{425}
-\entry {\code {HOST{\_}BITS{\_}PER{\_}INT}}{425}
-\entry {\code {HOST{\_}BITS{\_}PER{\_}LONG}}{425}
-\entry {\code {HOST{\_}BITS{\_}PER{\_}SHORT}}{425}
-\entry {\code {HOST{\_}FLOAT{\_}FORMAT}}{425}
-\entry {\code {HOST{\_}FLOAT{\_}WORDS{\_}BIG{\_}ENDIAN}}{425}
-\entry {\code {HOST{\_}WORDS{\_}BIG{\_}ENDIAN}}{425}
-\entry {HPPA Options}{74}
+\entry {\samp {H} in constraint}{268}
+\entry {\code {HANDLE{\_}PRAGMA}}{414}
+\entry {hard registers}{228}
+\entry {\code {HARD{\_}FRAME{\_}POINTER{\_}REGNUM}}{349}
+\entry {\code {HARD{\_}REGNO{\_}MODE{\_}OK}}{337}
+\entry {\code {HARD{\_}REGNO{\_}NREGS}}{337}
+\entry {hardware models and configurations, specifying}{52}
+\entry {\code {HAVE{\_}ATEXIT}}{416}
+\entry {\code {HAVE{\_}POST{\_}DECREMENT}}{373}
+\entry {\code {HAVE{\_}POST{\_}INCREMENT}}{373}
+\entry {\code {HAVE{\_}PRE{\_}DECREMENT}}{373}
+\entry {\code {HAVE{\_}PRE{\_}INCREMENT}}{373}
+\entry {\code {HAVE{\_}PUTENV}}{418}
+\entry {\code {HAVE{\_}VPRINTF}}{418}
+\entry {header files and VMS}{199}
+\entry {\code {high}}{227}
+\entry {\code {HImode}}{223}
+\entry {\code {HImode}, in \code {insn}}{248}
+\entry {\code {HOST{\_}BITS{\_}PER{\_}CHAR}}{417}
+\entry {\code {HOST{\_}BITS{\_}PER{\_}INT}}{417}
+\entry {\code {HOST{\_}BITS{\_}PER{\_}LONG}}{417}
+\entry {\code {HOST{\_}BITS{\_}PER{\_}SHORT}}{417}
+\entry {\code {HOST{\_}FLOAT{\_}FORMAT}}{417}
+\entry {\code {HOST{\_}FLOAT{\_}WORDS{\_}BIG{\_}ENDIAN}}{417}
+\entry {\code {HOST{\_}WORDS{\_}BIG{\_}ENDIAN}}{417}
+\entry {HPPA Options}{70}
 \initial {I}
-\entry {\samp {i} in constraint}{274}
-\entry {\samp {I} in constraint}{274}
-\entry {i386 Options}{73}
-\entry {IBM RS/6000 and PowerPC Options}{67}
-\entry {IBM RT options}{69}
-\entry {IBM RT PC}{178}
-\entry {identifier names, dollar signs in}{142}
-\entry {identifiers, names in assembler code}{151}
-\entry {identifying source, compiler (88k)}{64}
-\entry {\code {IEEE{\_}FLOAT{\_}FORMAT}}{337}
-\entry {\code {if{\_}then{\_}else}}{242}
-\entry {\code {if{\_}then{\_}else} and attributes}{313}
-\entry {\code {if{\_}then{\_}else} usage}{245}
-\entry {\code {immediate{\_}operand}}{266}
-\entry {\code {IMMEDIATE{\_}PREFIX}}{405}
-\entry {implicit argument: return value}{159}
-\entry {\code {IMPLICIT{\_}FIX{\_}EXPR}}{418}
-\entry {implied \code {#pragma implementation}}{163}
-\entry {\code {in{\_}data}}{388}
-\entry {\code {in{\_}struct}}{227}
-\entry {\code {in{\_}struct}, in \code {code{\_}label}}{227}
-\entry {\code {in{\_}struct}, in \code {insn}}{226, 227}
-\entry {\code {in{\_}struct}, in \code {label{\_}ref}}{226}
-\entry {\code {in{\_}struct}, in \code {mem}}{225}
-\entry {\code {in{\_}struct}, in \code {reg}}{225}
-\entry {\code {in{\_}struct}, in \code {subreg}}{225}
-\entry {\code {in{\_}text}}{388}
-\entry {include files and VMS}{205}
-\entry {\code {INCLUDE{\_}DEFAULTS}}{328}
-\entry {inclusive-or, bitwise}{240}
-\entry {\code {INCOMING{\_}REGNO}}{342}
-\entry {incompatibilities of GNU CC}{180}
-\entry {increment operators}{193}
-\entry {\code {INDEX{\_}REG{\_}CLASS}}{348}
-\entry {\code {indirect{\_}jump} instruction pattern}{294}
-\entry {\code {INIT{\_}CUMULATIVE{\_}ARGS}}{362}
-\entry {\code {INIT{\_}CUMULATIVE{\_}INCOMING{\_}ARGS}}{362}
-\entry {\code {INIT{\_}SECTION{\_}ASM{\_}OP}}{388, 402}
-\entry {\code {INIT{\_}TARGET{\_}OPTABS}}{377}
-\entry {\code {INITIAL{\_}ELIMINATION{\_}OFFSET}}{358}
-\entry {\code {INITIAL{\_}FRAME{\_}POINTER{\_}OFFSET}}{357}
-\entry {initialization routines}{399}
-\entry {initializations in expressions}{134}
-\entry {\code {INITIALIZE{\_}TRAMPOLINE}}{374}
-\entry {initializers with labeled elements}{135}
-\entry {initializers, non-constant}{134}
-\entry {\code {inline} automatic for C{\tt\char43}{\tt\char43} member fns}{146}
-\entry {inline functions}{146}
-\entry {inline functions, omission of}{146}
-\entry {inline, automatic}{216}
-\entry {inlining and C{\tt\char43}{\tt\char43} pragmas}{163}
-\entry {\code {insn}}{252}
-\entry {\code {insn} and \samp {/i}}{227}
-\entry {\code {insn} and \samp {/s}}{226}
-\entry {\code {insn} and \samp {/u}}{226}
-\entry {insn attributes}{311}
-\entry {insn canonicalization}{300}
-\entry {insn lengths, computing}{318}
-\entry {insn splitting}{308}
-\entry {\code {insn-attr.h}}{312}
-\entry {\code {INSN{\_}ANNULLED{\_}BRANCH{\_}P}}{226}
-\entry {\code {INSN{\_}CACHE{\_}DEPTH}}{375}
-\entry {\code {INSN{\_}CACHE{\_}LINE{\_}WIDTH}}{375}
-\entry {\code {INSN{\_}CACHE{\_}SIZE}}{375}
-\entry {\code {INSN{\_}CLOBBERS{\_}REGNO{\_}P}}{346}
-\entry {\code {INSN{\_}CODE}}{255}
-\entry {\code {INSN{\_}DELETED{\_}P}}{226}
-\entry {\code {INSN{\_}FROM{\_}TARGET{\_}P}}{226}
-\entry {\code {insn{\_}list}}{259}
-\entry {\code {INSN{\_}REFERENCES{\_}ARE{\_}DELAYED}}{423}
-\entry {\code {INSN{\_}SETS{\_}ARE{\_}DELAYED}}{423}
-\entry {\code {INSN{\_}UID}}{251}
-\entry {insns}{251}
-\entry {insns, generating}{265}
-\entry {insns, recognizing}{265}
-\entry {installation trouble}{169}
-\entry {installing GNU CC}{87}
-\entry {installing GNU CC on the Sun}{112}
-\entry {installing GNU CC on VMS}{113}
-\entry {instruction attributes}{311}
-\entry {instruction combination}{218}
-\entry {instruction patterns}{263}
-\entry {instruction recognizer}{220}
-\entry {instruction scheduling}{218}
-\entry {instruction splitting}{308}
-\entry {\code {insv} instruction pattern}{291}
-\entry {\code {INT{\_}TYPE{\_}SIZE}}{337}
-\entry {\code {INTEGRATE{\_}THRESHOLD}}{421}
-\entry {\code {integrated}}{228}
-\entry {\code {integrated}, in \code {insn}}{226}
-\entry {\code {integrated}, in \code {reg}}{225}
-\entry {integrating function code}{146}
-\entry {Intel 386 Options}{73}
-\entry {Interdependence of Patterns}{296}
-\entry {interface and implementation headers, C{\tt\char43}{\tt\char43}}{162}
-\entry {interfacing to GNU CC output}{213}
-\entry {intermediate C version, nonexistent}{17}
-\entry {\code {INTIFY}}{378}
-\entry {invalid assembly code}{193}
-\entry {invalid input}{194}
-\entry {\code {INVOKE{\_}{\_}main}}{402}
-\entry {invoking \code {g{\tt\char43}{\tt\char43}}}{26}
-\entry {\code {ior}}{240}
-\entry {\code {ior} and attributes}{313}
-\entry {\code {ior}, canonicalization of}{300}
-\entry {\code {ior\var {m}3} instruction pattern}{288}
-\entry {\code {IS{\_}ASM{\_}LOGICAL{\_}LINE{\_}SEPARATOR}}{394}
-\entry {\code {isinf}}{416}
-\entry {\code {isnan}}{416}
+\entry {\samp {i} in constraint}{268}
+\entry {\samp {I} in constraint}{268}
+\entry {i386 Options}{69}
+\entry {IBM RS/6000 and PowerPC Options}{63}
+\entry {IBM RT options}{65}
+\entry {IBM RT PC}{172}
+\entry {identifier names, dollar signs in}{138}
+\entry {identifiers, names in assembler code}{147}
+\entry {identifying source, compiler (88k)}{60}
+\entry {\code {IEEE{\_}FLOAT{\_}FORMAT}}{331}
+\entry {\code {if{\_}then{\_}else}}{236}
+\entry {\code {if{\_}then{\_}else} and attributes}{307}
+\entry {\code {if{\_}then{\_}else} usage}{239}
+\entry {\code {immediate{\_}operand}}{260}
+\entry {\code {IMMEDIATE{\_}PREFIX}}{399}
+\entry {implicit argument: return value}{155}
+\entry {\code {IMPLICIT{\_}FIX{\_}EXPR}}{411}
+\entry {implied \code {#pragma implementation}}{159}
+\entry {\code {in{\_}data}}{382}
+\entry {\code {in{\_}struct}}{221}
+\entry {\code {in{\_}struct}, in \code {code{\_}label}}{221}
+\entry {\code {in{\_}struct}, in \code {insn}}{220, 221}
+\entry {\code {in{\_}struct}, in \code {label{\_}ref}}{220}
+\entry {\code {in{\_}struct}, in \code {mem}}{219}
+\entry {\code {in{\_}struct}, in \code {reg}}{219}
+\entry {\code {in{\_}struct}, in \code {subreg}}{219}
+\entry {\code {in{\_}text}}{382}
+\entry {include files and VMS}{199}
+\entry {\code {INCLUDE{\_}DEFAULTS}}{322}
+\entry {inclusive-or, bitwise}{234}
+\entry {\code {INCOMING{\_}REGNO}}{335}
+\entry {incompatibilities of GNU CC}{174}
+\entry {increment operators}{187}
+\entry {\code {INDEX{\_}REG{\_}CLASS}}{342}
+\entry {\code {indirect{\_}jump} instruction pattern}{288}
+\entry {\code {INIT{\_}CUMULATIVE{\_}ARGS}}{356}
+\entry {\code {INIT{\_}CUMULATIVE{\_}INCOMING{\_}ARGS}}{356}
+\entry {\code {INIT{\_}SECTION{\_}ASM{\_}OP}}{382, 395}
+\entry {\code {INIT{\_}TARGET{\_}OPTABS}}{371}
+\entry {\code {INITIAL{\_}ELIMINATION{\_}OFFSET}}{351}
+\entry {\code {INITIAL{\_}FRAME{\_}POINTER{\_}OFFSET}}{351}
+\entry {initialization routines}{393}
+\entry {initializations in expressions}{130}
+\entry {\code {INITIALIZE{\_}TRAMPOLINE}}{368}
+\entry {initializers with labeled elements}{131}
+\entry {initializers, non-constant}{130}
+\entry {\code {inline} automatic for C{\tt\char43}{\tt\char43} member fns}{142}
+\entry {inline functions}{141}
+\entry {inline functions, omission of}{142}
+\entry {inline, automatic}{210}
+\entry {inlining and C{\tt\char43}{\tt\char43} pragmas}{159}
+\entry {\code {insn}}{246}
+\entry {\code {insn} and \samp {/i}}{221}
+\entry {\code {insn} and \samp {/s}}{220}
+\entry {\code {insn} and \samp {/u}}{220}
+\entry {insn attributes}{305}
+\entry {insn canonicalization}{294}
+\entry {insn lengths, computing}{312}
+\entry {insn splitting}{302}
+\entry {\code {insn-attr.h}}{306}
+\entry {\code {INSN{\_}ANNULLED{\_}BRANCH{\_}P}}{220}
+\entry {\code {INSN{\_}CACHE{\_}DEPTH}}{369}
+\entry {\code {INSN{\_}CACHE{\_}LINE{\_}WIDTH}}{369}
+\entry {\code {INSN{\_}CACHE{\_}SIZE}}{369}
+\entry {\code {INSN{\_}CLOBBERS{\_}REGNO{\_}P}}{340}
+\entry {\code {INSN{\_}CODE}}{249}
+\entry {\code {INSN{\_}DELETED{\_}P}}{220}
+\entry {\code {INSN{\_}FROM{\_}TARGET{\_}P}}{220}
+\entry {\code {insn{\_}list}}{253}
+\entry {\code {INSN{\_}REFERENCES{\_}ARE{\_}DELAYED}}{416}
+\entry {\code {INSN{\_}SETS{\_}ARE{\_}DELAYED}}{416}
+\entry {\code {INSN{\_}UID}}{245}
+\entry {insns}{245}
+\entry {insns, generating}{259}
+\entry {insns, recognizing}{259}
+\entry {installation trouble}{163}
+\entry {installing GNU CC}{83}
+\entry {installing GNU CC on the Sun}{107}
+\entry {installing GNU CC on VMS}{108}
+\entry {instruction attributes}{305}
+\entry {instruction combination}{212}
+\entry {instruction patterns}{257}
+\entry {instruction recognizer}{214}
+\entry {instruction scheduling}{212}
+\entry {instruction splitting}{302}
+\entry {\code {insv} instruction pattern}{285}
+\entry {\code {INT{\_}TYPE{\_}SIZE}}{331}
+\entry {\code {INTEGRATE{\_}THRESHOLD}}{414}
+\entry {\code {integrated}}{222}
+\entry {\code {integrated}, in \code {insn}}{220}
+\entry {\code {integrated}, in \code {reg}}{219}
+\entry {integrating function code}{141}
+\entry {Intel 386 Options}{69}
+\entry {Interdependence of Patterns}{290}
+\entry {interface and implementation headers, C{\tt\char43}{\tt\char43}}{158}
+\entry {interfacing to GNU CC output}{207}
+\entry {intermediate C version, nonexistent}{15}
+\entry {\code {INTIFY}}{372}
+\entry {invalid assembly code}{187}
+\entry {invalid input}{188}
+\entry {invoking \code {g{\tt\char43}{\tt\char43}}}{24}
+\entry {\code {ior}}{234}
+\entry {\code {ior} and attributes}{307}
+\entry {\code {ior}, canonicalization of}{294}
+\entry {\code {ior\var {m}3} instruction pattern}{282}
+\entry {\code {IS{\_}ASM{\_}LOGICAL{\_}LINE{\_}SEPARATOR}}{388}
+\entry {\code {isinf}}{409}
+\entry {\code {isnan}}{409}
 \initial {J}
-\entry {jump instruction patterns}{298}
-\entry {jump instructions and \code {set}}{245}
-\entry {jump optimization}{216}
-\entry {jump threading}{217}
-\entry {\code {jump{\_}insn}}{252}
-\entry {\code {JUMP{\_}LABEL}}{253}
-\entry {\code {JUMP{\_}TABLES{\_}IN{\_}TEXT{\_}SECTION}}{389}
+\entry {jump instruction patterns}{292}
+\entry {jump instructions and \code {set}}{239}
+\entry {jump optimization}{210}
+\entry {jump threading}{211}
+\entry {\code {jump{\_}insn}}{246}
+\entry {\code {JUMP{\_}LABEL}}{247}
+\entry {\code {JUMP{\_}TABLES{\_}IN{\_}TEXT{\_}SECTION}}{383}
 \initial {K}
-\entry {kernel and user registers (29k)}{62}
-\entry {keywords, alternate}{155}
-\entry {known causes of trouble}{169}
+\entry {kernel and user registers (29k)}{59}
+\entry {keywords, alternate}{151}
+\entry {known causes of trouble}{163}
 \initial {L}
-\entry {\code {LABEL{\_}NUSES}}{253}
-\entry {\code {LABEL{\_}OUTSIDE{\_}LOOP{\_}P}}{226}
-\entry {\code {LABEL{\_}PRESERVE{\_}P}}{227}
-\entry {\code {label{\_}ref}}{233}
-\entry {\code {label{\_}ref} and \samp {/s}}{226}
-\entry {\code {label{\_}ref}, RTL sharing}{261}
-\entry {labeled elements in initializers}{135}
-\entry {labels as values}{121}
-\entry {\code {labs}}{27}
-\entry {language dialect options}{27}
-\entry {large bit shifts (88k)}{66}
-\entry {large return values}{365}
-\entry {\code {LAST{\_}STACK{\_}REG}}{345}
-\entry {\code {LAST{\_}VIRTUAL{\_}REGISTER}}{235}
-\entry {\code {ldexp}}{415}
-\entry {\code {le}}{242}
-\entry {\code {le} and attributes}{313}
-\entry {leaf functions}{344}
-\entry {\code {leaf{\_}function}}{345}
-\entry {\code {leaf{\_}function{\_}p}}{293}
-\entry {\code {LEAF{\_}REG{\_}REMAP}}{345}
-\entry {\code {LEAF{\_}REGISTERS}}{344}
-\entry {left rotate}{240}
-\entry {left shift}{240}
-\entry {\code {LEGITIMATE{\_}CONSTANT{\_}P}}{382}
-\entry {\code {LEGITIMATE{\_}PIC{\_}OPERAND{\_}P}}{390}
-\entry {\code {LEGITIMIZE{\_}ADDRESS}}{381}
-\entry {length-zero arrays}{130}
-\entry {less than}{242}
-\entry {less than or equal}{242}
-\entry {\code {leu}}{242}
-\entry {\code {leu} and attributes}{313}
-\entry {\code {LIB{\_}SPEC}}{326}
-\entry {\code {LIBCALL{\_}VALUE}}{364}
-\entry {\file {libgcc.a}}{376}
-\entry {\code {LIBGCC{\_}NEEDS{\_}DOUBLE}}{378}
-\entry {Libraries}{51}
-\entry {library subroutine names}{376}
-\entry {\code {LIBRARY{\_}PATH}}{82}
-\entry {\code {LIMIT{\_}RELOAD{\_}CLASS}}{349}
-\entry {link options}{51}
-\entry {\code {LINK{\_}LIBGCC{\_}SPECIAL}}{327}
-\entry {\code {LINK{\_}LIBGCC{\_}SPECIAL{\_}1}}{327}
-\entry {\code {LINK{\_}SPEC}}{326}
-\entry {\code {lo{\_}sum}}{238}
-\entry {load address instruction}{275}
-\entry {\code {LOAD{\_}EXTEND{\_}OP}}{418}
-\entry {\code {load{\_}multiple} instruction pattern}{287}
-\entry {local labels}{120}
-\entry {local register allocation}{218}
-\entry {local variables in macros}{126}
-\entry {local variables, specifying registers}{154}
-\entry {\code {LOCAL{\_}INCLUDE{\_}DIR}}{328}
-\entry {\code {LOCAL{\_}LABEL{\_}PREFIX}}{405}
-\entry {\code {LOG{\_}LINKS}}{255}
-\entry {logical-and, bitwise}{240}
-\entry {\code {long long} data types}{129}
-\entry {\code {LONG{\_}DOUBLE{\_}TYPE{\_}SIZE}}{338}
-\entry {\code {LONG{\_}LONG{\_}TYPE{\_}SIZE}}{338}
-\entry {\code {LONG{\_}TYPE{\_}SIZE}}{338}
-\entry {\code {longjmp}}{154}
-\entry {\code {longjmp} and automatic variables}{28, 213}
-\entry {\code {longjmp} incompatibilities}{181}
-\entry {\code {longjmp} warnings}{35}
-\entry {\code {LONGJMP{\_}RESTORE{\_}FROM{\_}STACK}}{358}
-\entry {loop optimization}{217}
-\entry {\code {lshiftrt}}{240}
-\entry {\code {lshiftrt} and attributes}{313}
-\entry {\code {lshr\var {m}3} instruction pattern}{289}
-\entry {\code {lt}}{242}
-\entry {\code {lt} and attributes}{313}
-\entry {\code {ltu}}{242}
-\entry {lvalues, generalized}{127}
+\entry {\code {LABEL{\_}NUSES}}{247}
+\entry {\code {LABEL{\_}OUTSIDE{\_}LOOP{\_}P}}{220}
+\entry {\code {LABEL{\_}PRESERVE{\_}P}}{221}
+\entry {\code {label{\_}ref}}{227}
+\entry {\code {label{\_}ref} and \samp {/s}}{220}
+\entry {\code {label{\_}ref}, RTL sharing}{255}
+\entry {labeled elements in initializers}{131}
+\entry {labels as values}{117}
+\entry {\code {labs}}{25}
+\entry {language dialect options}{25}
+\entry {large bit shifts (88k)}{63}
+\entry {large return values}{359}
+\entry {\code {LAST{\_}STACK{\_}REG}}{339}
+\entry {\code {LAST{\_}VIRTUAL{\_}REGISTER}}{229}
+\entry {\code {ldexp}}{408}
+\entry {\code {le}}{236}
+\entry {\code {le} and attributes}{307}
+\entry {leaf functions}{338}
+\entry {\code {leaf{\_}function}}{339}
+\entry {\code {leaf{\_}function{\_}p}}{287}
+\entry {\code {LEAF{\_}REG{\_}REMAP}}{339}
+\entry {\code {LEAF{\_}REGISTERS}}{338}
+\entry {left rotate}{234}
+\entry {left shift}{234}
+\entry {\code {LEGITIMATE{\_}CONSTANT{\_}P}}{376}
+\entry {\code {LEGITIMATE{\_}PIC{\_}OPERAND{\_}P}}{384}
+\entry {\code {LEGITIMIZE{\_}ADDRESS}}{375}
+\entry {length-zero arrays}{126}
+\entry {less than}{236}
+\entry {less than or equal}{236}
+\entry {\code {leu}}{236}
+\entry {\code {leu} and attributes}{307}
+\entry {\code {LIB{\_}SPEC}}{320}
+\entry {\code {LIBCALL{\_}VALUE}}{358}
+\entry {\file {libgcc.a}}{370}
+\entry {\code {LIBGCC{\_}NEEDS{\_}DOUBLE}}{372}
+\entry {Libraries}{48}
+\entry {library subroutine names}{370}
+\entry {\code {LIBRARY{\_}PATH}}{78}
+\entry {\code {LIMIT{\_}RELOAD{\_}CLASS}}{343}
+\entry {link options}{48}
+\entry {\code {LINK{\_}LIBGCC{\_}SPECIAL}}{321}
+\entry {\code {LINK{\_}LIBGCC{\_}SPECIAL{\_}1}}{321}
+\entry {\code {LINK{\_}SPEC}}{320}
+\entry {\code {lo{\_}sum}}{232}
+\entry {load address instruction}{269}
+\entry {\code {LOAD{\_}EXTEND{\_}OP}}{411}
+\entry {\code {load{\_}multiple} instruction pattern}{281}
+\entry {local labels}{116}
+\entry {local register allocation}{212}
+\entry {local variables in macros}{122}
+\entry {local variables, specifying registers}{150}
+\entry {\code {LOCAL{\_}INCLUDE{\_}DIR}}{322}
+\entry {\code {LOCAL{\_}LABEL{\_}PREFIX}}{399}
+\entry {\code {LOG{\_}LINKS}}{249}
+\entry {logical-and, bitwise}{234}
+\entry {\code {long long} data types}{125}
+\entry {\code {LONG{\_}DOUBLE{\_}TYPE{\_}SIZE}}{332}
+\entry {\code {LONG{\_}LONG{\_}TYPE{\_}SIZE}}{332}
+\entry {\code {LONG{\_}TYPE{\_}SIZE}}{332}
+\entry {\code {longjmp}}{149}
+\entry {\code {longjmp} and automatic variables}{26, 207}
+\entry {\code {longjmp} incompatibilities}{175}
+\entry {\code {longjmp} warnings}{33}
+\entry {\code {LONGJMP{\_}RESTORE{\_}FROM{\_}STACK}}{351}
+\entry {loop optimization}{211}
+\entry {\code {lshiftrt}}{234}
+\entry {\code {lshiftrt} and attributes}{307}
+\entry {\code {lshr\var {m}3} instruction pattern}{283}
+\entry {\code {lt}}{236}
+\entry {\code {lt} and attributes}{307}
+\entry {\code {ltu}}{236}
+\entry {lvalues, generalized}{123}
 \initial {M}
-\entry {\samp {m} in constraint}{273}
-\entry {M680x0 options}{56}
-\entry {M88k options}{63}
-\entry {machine dependent options}{56}
-\entry {machine description macros}{325}
-\entry {machine descriptions}{263}
-\entry {machine mode conversions}{243}
-\entry {machine modes}{228}
-\entry {machine specific constraints}{280}
-\entry {\code {MACHINE{\_}DEPENDENT{\_}REORG}}{423}
-\entry {macro with variable arguments}{132}
-\entry {macros containing \code {asm}}{150}
-\entry {macros, inline alternative}{146}
-\entry {macros, local labels}{120}
-\entry {macros, local variables in}{126}
-\entry {macros, statements in expressions}{119}
-\entry {macros, target description}{325}
-\entry {macros, types of arguments}{126}
-\entry {\code {main} and the exit status}{209}
-\entry {make}{50}
-\entry {\code {make{\_}safe{\_}from}}{307}
-\entry {\code {match{\_}dup}}{266}
-\entry {\code {match{\_}dup} and attributes}{318}
-\entry {\code {match{\_}op{\_}dup}}{268}
-\entry {\code {match{\_}operand}}{265}
-\entry {\code {match{\_}operand} and attributes}{313}
-\entry {\code {match{\_}operator}}{266}
-\entry {\code {match{\_}par{\_}dup}}{269}
-\entry {\code {match{\_}parallel}}{268}
-\entry {\code {match{\_}scratch}}{266}
-\entry {matching constraint}{274}
-\entry {matching operands}{270}
-\entry {math libraries}{214}
-\entry {math, in RTL}{238}
-\entry {\code {MAX{\_}BITS{\_}PER{\_}WORD}}{333}
-\entry {\code {MAX{\_}CHAR{\_}TYPE{\_}SIZE}}{338}
-\entry {\code {MAX{\_}FIXED{\_}MODE{\_}SIZE}}{336}
-\entry {\code {MAX{\_}INT{\_}TYPE{\_}SIZE}}{338}
-\entry {\code {MAX{\_}LONG{\_}TYPE{\_}SIZE}}{338}
-\entry {\code {MAX{\_}MOVE{\_}MAX}}{419}
-\entry {\code {MAX{\_}OFILE{\_}ALIGNMENT}}{334}
-\entry {\code {MAX{\_}REGS{\_}PER{\_}ADDRESS}}{380}
-\entry {\code {MAX{\_}UNITS{\_}PER{\_}WORD}}{333}
-\entry {\code {MAX{\_}WCHAR{\_}TYPE{\_}SIZE}}{339}
-\entry {maximum operator}{161}
-\entry {\code {max\var {m}3} instruction pattern}{288}
-\entry {\code {MAYBE{\_}REG{\_}PARM{\_}STACK{\_}SPACE}}{359}
-\entry {\code {mcount}}{370}
-\entry {\code {MD{\_}CALL{\_}PROTOTYPES}}{427}
-\entry {\code {MD{\_}EXEC{\_}PREFIX}}{327}
-\entry {\code {MD{\_}STARTFILE{\_}PREFIX}}{327}
-\entry {\code {MD{\_}STARTFILE{\_}PREFIX{\_}1}}{328}
-\entry {\code {mem}}{238}
-\entry {\code {mem} and \samp {/s}}{225}
-\entry {\code {mem} and \samp {/u}}{225}
-\entry {\code {mem} and \samp {/v}}{225}
-\entry {\code {mem}, RTL sharing}{261}
-\entry {\code {MEM{\_}IN{\_}STRUCT{\_}P}}{225}
-\entry {\code {MEM{\_}VOLATILE{\_}P}}{225}
-\entry {member fns, automatically \code {inline}}{146}
-\entry {\code {memcmp}}{27}
-\entry {\code {memcpy}}{27}
-\entry {\code {memcpy}, implicit usage}{378}
-\entry {memory model (29k)}{62}
-\entry {memory reference, nonoffsettable}{277}
-\entry {memory references in constraints}{273}
-\entry {\code {MEMORY{\_}MOVE{\_}COST}}{386}
-\entry {\code {memset}, implicit usage}{378}
-\entry {messages, warning}{34}
-\entry {messages, warning and error}{191}
-\entry {middle-operands, omitted}{128}
-\entry {minimum operator}{161}
-\entry {\code {min\var {m}3} instruction pattern}{288}
-\entry {\code {minus}}{238}
-\entry {\code {minus} and attributes}{313}
-\entry {\code {minus}, canonicalization of}{300}
-\entry {MIPS options}{70}
-\entry {misunderstandings in C{\tt\char43}{\tt\char43}}{185}
-\entry {\code {mktemp}, and constant strings}{180}
-\entry {\code {mod}}{239}
-\entry {\code {mod} and attributes}{313}
-\entry {\code {MODDI3{\_}LIBCALL}}{377}
-\entry {\code {mode} attribute}{144}
-\entry {mode classes}{230}
-\entry {\code {MODE{\_}CC}}{230}
-\entry {\code {MODE{\_}COMPLEX{\_}FLOAT}}{230}
-\entry {\code {MODE{\_}COMPLEX{\_}INT}}{230}
-\entry {\code {MODE{\_}FLOAT}}{230}
-\entry {\code {MODE{\_}FUNCTION}}{230}
-\entry {\code {MODE{\_}INT}}{230}
-\entry {\code {MODE{\_}PARTIAL{\_}INT}}{230}
-\entry {\code {MODE{\_}RANDOM}}{231}
-\entry {\code {MODES{\_}TIEABLE{\_}P}}{344}
-\entry {modifiers in constraints}{279}
-\entry {\code {mod\var {m}3} instruction pattern}{288}
-\entry {\code {MODSI3{\_}LIBCALL}}{376}
-\entry {\code {MOVE{\_}MAX}}{419}
-\entry {\code {MOVE{\_}RATIO}}{387}
-\entry {\code {mov\var {m}} instruction pattern}{286}
-\entry {\code {movstrict\var {m}} instruction pattern}{287}
-\entry {\code {movstr\var {m}} instruction pattern}{289}
-\entry {\code {MULDI3{\_}LIBCALL}}{377}
-\entry {\code {mulhisi3} instruction pattern}{288}
-\entry {\code {mul\var {m}3} instruction pattern}{288}
-\entry {\code {mulqihi3} instruction pattern}{288}
-\entry {\code {MULSI3{\_}LIBCALL}}{376}
-\entry {\code {mulsidi3} instruction pattern}{288}
-\entry {\code {mult}}{239}
-\entry {\code {mult} and attributes}{313}
-\entry {\code {mult}, canonicalization of}{300}
-\entry {\code {MULTIBYTE{\_}CHARS}}{426}
-\entry {multiple alternative constraints}{277}
-\entry {multiplication}{239}
-\entry {multiprecision arithmetic}{129}
-\entry {\code {MUST{\_}PASS{\_}IN{\_}STACK}, and \code {FUNCTION{\_}ARG}}{361}
+\entry {\samp {m} in constraint}{267}
+\entry {M680x0 options}{53}
+\entry {M88k options}{60}
+\entry {machine dependent options}{52}
+\entry {machine description macros}{319}
+\entry {machine descriptions}{257}
+\entry {machine mode conversions}{237}
+\entry {machine modes}{222}
+\entry {machine specific constraints}{274}
+\entry {\code {MACHINE{\_}DEPENDENT{\_}REORG}}{416}
+\entry {macro with variable arguments}{128}
+\entry {macros containing \code {asm}}{146}
+\entry {macros, inline alternative}{141}
+\entry {macros, local labels}{116}
+\entry {macros, local variables in}{122}
+\entry {macros, statements in expressions}{115}
+\entry {macros, target description}{319}
+\entry {macros, types of arguments}{122}
+\entry {\code {main} and the exit status}{203}
+\entry {make}{47}
+\entry {\code {make{\_}safe{\_}from}}{301}
+\entry {\code {match{\_}dup}}{260}
+\entry {\code {match{\_}dup} and attributes}{312}
+\entry {\code {match{\_}op{\_}dup}}{262}
+\entry {\code {match{\_}operand}}{259}
+\entry {\code {match{\_}operand} and attributes}{307}
+\entry {\code {match{\_}operator}}{260}
+\entry {\code {match{\_}par{\_}dup}}{263}
+\entry {\code {match{\_}parallel}}{262}
+\entry {\code {match{\_}scratch}}{260}
+\entry {matching constraint}{268}
+\entry {matching operands}{264}
+\entry {math libraries}{208}
+\entry {math, in RTL}{232}
+\entry {\code {MAX{\_}BITS{\_}PER{\_}WORD}}{326}
+\entry {\code {MAX{\_}CHAR{\_}TYPE{\_}SIZE}}{332}
+\entry {\code {MAX{\_}FIXED{\_}MODE{\_}SIZE}}{330}
+\entry {\code {MAX{\_}INT{\_}TYPE{\_}SIZE}}{331}
+\entry {\code {MAX{\_}LONG{\_}TYPE{\_}SIZE}}{332}
+\entry {\code {MAX{\_}MOVE{\_}MAX}}{412}
+\entry {\code {MAX{\_}OFILE{\_}ALIGNMENT}}{328}
+\entry {\code {MAX{\_}REGS{\_}PER{\_}ADDRESS}}{374}
+\entry {\code {MAX{\_}UNITS{\_}PER{\_}WORD}}{327}
+\entry {\code {MAX{\_}WCHAR{\_}TYPE{\_}SIZE}}{333}
+\entry {maximum operator}{157}
+\entry {\code {max\var {m}3} instruction pattern}{282}
+\entry {\code {MAYBE{\_}REG{\_}PARM{\_}STACK{\_}SPACE}}{353}
+\entry {\code {mcount}}{364}
+\entry {\code {MD{\_}CALL{\_}PROTOTYPES}}{419}
+\entry {\code {MD{\_}EXEC{\_}PREFIX}}{321}
+\entry {\code {MD{\_}STARTFILE{\_}PREFIX}}{321}
+\entry {\code {MD{\_}STARTFILE{\_}PREFIX{\_}1}}{321}
+\entry {\code {mem}}{232}
+\entry {\code {mem} and \samp {/s}}{219}
+\entry {\code {mem} and \samp {/u}}{219}
+\entry {\code {mem} and \samp {/v}}{219}
+\entry {\code {mem}, RTL sharing}{255}
+\entry {\code {MEM{\_}IN{\_}STRUCT{\_}P}}{219}
+\entry {\code {MEM{\_}VOLATILE{\_}P}}{219}
+\entry {member fns, automatically \code {inline}}{142}
+\entry {\code {memcmp}}{25}
+\entry {\code {memcpy}}{25}
+\entry {\code {memcpy}, implicit usage}{372}
+\entry {memory model (29k)}{59}
+\entry {memory reference, nonoffsettable}{271}
+\entry {memory references in constraints}{267}
+\entry {\code {MEMORY{\_}MOVE{\_}COST}}{380}
+\entry {\code {memset}, implicit usage}{372}
+\entry {messages, warning}{32}
+\entry {messages, warning and error}{186}
+\entry {middle-operands, omitted}{124}
+\entry {minimum operator}{157}
+\entry {\code {min\var {m}3} instruction pattern}{282}
+\entry {\code {minus}}{232}
+\entry {\code {minus} and attributes}{307}
+\entry {\code {minus}, canonicalization of}{294}
+\entry {MIPS options}{66}
+\entry {misunderstandings in C{\tt\char43}{\tt\char43}}{179}
+\entry {\code {mktemp}, and constant strings}{174}
+\entry {\code {mod}}{233}
+\entry {\code {mod} and attributes}{307}
+\entry {\code {MODDI3{\_}LIBCALL}}{371}
+\entry {\code {mode} attribute}{140}
+\entry {mode classes}{224}
+\entry {\code {MODE{\_}CC}}{224}
+\entry {\code {MODE{\_}COMPLEX{\_}FLOAT}}{224}
+\entry {\code {MODE{\_}COMPLEX{\_}INT}}{224}
+\entry {\code {MODE{\_}FLOAT}}{224}
+\entry {\code {MODE{\_}FUNCTION}}{224}
+\entry {\code {MODE{\_}INT}}{224}
+\entry {\code {MODE{\_}PARTIAL{\_}INT}}{224}
+\entry {\code {MODE{\_}RANDOM}}{225}
+\entry {\code {MODES{\_}TIEABLE{\_}P}}{338}
+\entry {modifiers in constraints}{273}
+\entry {\code {mod\var {m}3} instruction pattern}{282}
+\entry {\code {MODSI3{\_}LIBCALL}}{370}
+\entry {\code {MOVE{\_}MAX}}{412}
+\entry {\code {MOVE{\_}RATIO}}{381}
+\entry {\code {mov\var {m}} instruction pattern}{280}
+\entry {\code {movstrict\var {m}} instruction pattern}{281}
+\entry {\code {movstr\var {m}} instruction pattern}{283}
+\entry {\code {MULDI3{\_}LIBCALL}}{371}
+\entry {\code {mulhisi3} instruction pattern}{282}
+\entry {\code {mul\var {m}3} instruction pattern}{282}
+\entry {\code {mulqihi3} instruction pattern}{282}
+\entry {\code {MULSI3{\_}LIBCALL}}{370}
+\entry {\code {mulsidi3} instruction pattern}{282}
+\entry {\code {mult}}{233}
+\entry {\code {mult} and attributes}{307}
+\entry {\code {mult}, canonicalization of}{294}
+\entry {\code {MULTIBYTE{\_}CHARS}}{418}
+\entry {multiple alternative constraints}{271}
+\entry {multiplication}{233}
+\entry {multiprecision arithmetic}{125}
+\entry {\code {MUST{\_}PASS{\_}IN{\_}STACK}, and \code {FUNCTION{\_}ARG}}{354}
 \initial {N}
-\entry {\samp {n} in constraint}{274}
-\entry {\code {N{\_}REG{\_}CLASSES}}{348}
-\entry {name augmentation}{209}
-\entry {named patterns and conditions}{264}
-\entry {named return value in C{\tt\char43}{\tt\char43}}{159}
-\entry {names used in assembler code}{151}
-\entry {names, pattern}{286}
-\entry {naming convention, implementation headers}{163}
-\entry {naming types}{125}
-\entry {\code {ne}}{242}
-\entry {\code {ne} and attributes}{313}
-\entry {\code {neg}}{239}
-\entry {\code {neg} and attributes}{313}
-\entry {\code {neg}, canonicalization of}{300}
-\entry {\code {neg\var {m}2} instruction pattern}{289}
-\entry {nested functions}{122}
-\entry {nested functions, trampolines for}{373}
-\entry {newline vs string constants}{29}
-\entry {\code {next{\_}cc0{\_}user}}{299}
-\entry {\code {NEXT{\_}INSN}}{252}
-\entry {\code {NEXT{\_}OBJC{\_}RUNTIME}}{379}
-\entry {nil}{222}
-\entry {no constraints}{285}
-\entry {no-op move instructions}{219}
-\entry {\code {NO{\_}BUILTIN{\_}PTRDIFF{\_}TYPE}}{326}
-\entry {\code {NO{\_}BUILTIN{\_}SIZE{\_}TYPE}}{325}
-\entry {\code {NO{\_}DOLLAR{\_}IN{\_}LABEL}}{422}
-\entry {\code {NO{\_}DOT{\_}IN{\_}LABEL}}{422}
-\entry {\code {NO{\_}FUNCTION{\_}CSE}}{387}
-\entry {\code {NO{\_}IMPLICIT{\_}EXTERN{\_}C}}{421}
-\entry {\code {NO{\_}MD{\_}PROTOTYPES}}{427}
-\entry {\code {NO{\_}RECURSIVE{\_}FUNCTION{\_}CSE}}{387}
-\entry {\code {NO{\_}REGS}}{347}
-\entry {\code {NO{\_}STAB{\_}H}}{427}
-\entry {\code {NO{\_}SYS{\_}SIGLIST}}{426}
-\entry {non-constant initializers}{134}
-\entry {non-static inline function}{146}
-\entry {\code {NON{\_}SAVING{\_}SETJMP}}{341}
-\entry {\code {nongcc{\_}SI{\_}type}}{379}
-\entry {\code {nongcc{\_}word{\_}type}}{379}
-\entry {nonoffsettable memory reference}{277}
-\entry {\code {nop} instruction pattern}{293}
-\entry {\code {noreturn} function attribute}{139}
-\entry {\code {not}}{240}
-\entry {\code {not} and attributes}{313}
-\entry {not equal}{242}
-\entry {not using constraints}{285}
-\entry {\code {not}, canonicalization of}{300}
-\entry {\code {note}}{254}
-\entry {\code {NOTE{\_}INSN{\_}BLOCK{\_}BEG}}{254}
-\entry {\code {NOTE{\_}INSN{\_}BLOCK{\_}END}}{254}
-\entry {\code {NOTE{\_}INSN{\_}DELETED}}{254}
-\entry {\code {NOTE{\_}INSN{\_}FUNCTION{\_}END}}{254}
-\entry {\code {NOTE{\_}INSN{\_}LOOP{\_}BEG}}{254}
-\entry {\code {NOTE{\_}INSN{\_}LOOP{\_}CONT}}{254}
-\entry {\code {NOTE{\_}INSN{\_}LOOP{\_}END}}{254}
-\entry {\code {NOTE{\_}INSN{\_}LOOP{\_}VTOP}}{254}
-\entry {\code {NOTE{\_}INSN{\_}SETJMP}}{254}
-\entry {\code {NOTE{\_}LINE{\_}NUMBER}}{254}
-\entry {\code {NOTE{\_}SOURCE{\_}FILE}}{254}
-\entry {\code {NOTICE{\_}UPDATE{\_}CC}}{383}
-\entry {\code {NUM{\_}MACHINE{\_}MODES}}{231}
+\entry {\samp {n} in constraint}{268}
+\entry {\code {N{\_}REG{\_}CLASSES}}{342}
+\entry {name augmentation}{203}
+\entry {named patterns and conditions}{258}
+\entry {named return value in C{\tt\char43}{\tt\char43}}{155}
+\entry {names used in assembler code}{147}
+\entry {names, pattern}{280}
+\entry {naming convention, implementation headers}{159}
+\entry {naming types}{121}
+\entry {\code {ne}}{236}
+\entry {\code {ne} and attributes}{307}
+\entry {\code {neg}}{233}
+\entry {\code {neg} and attributes}{307}
+\entry {\code {neg}, canonicalization of}{294}
+\entry {\code {neg\var {m}2} instruction pattern}{283}
+\entry {nested functions}{118}
+\entry {nested functions, trampolines for}{367}
+\entry {newline vs string constants}{27}
+\entry {\code {next{\_}cc0{\_}user}}{293}
+\entry {\code {NEXT{\_}INSN}}{246}
+\entry {\code {NEXT{\_}OBJC{\_}RUNTIME}}{373}
+\entry {nil}{216}
+\entry {no constraints}{279}
+\entry {no-op move instructions}{213}
+\entry {\code {NO{\_}BUILTIN{\_}PTRDIFF{\_}TYPE}}{319}
+\entry {\code {NO{\_}BUILTIN{\_}SIZE{\_}TYPE}}{319}
+\entry {\code {NO{\_}DOLLAR{\_}IN{\_}LABEL}}{415}
+\entry {\code {NO{\_}DOT{\_}IN{\_}LABEL}}{415}
+\entry {\code {NO{\_}FUNCTION{\_}CSE}}{381}
+\entry {\code {NO{\_}IMPLICIT{\_}EXTERN{\_}C}}{414}
+\entry {\code {NO{\_}MD{\_}PROTOTYPES}}{419}
+\entry {\code {NO{\_}RECURSIVE{\_}FUNCTION{\_}CSE}}{381}
+\entry {\code {NO{\_}REGS}}{341}
+\entry {\code {NO{\_}STAB{\_}H}}{419}
+\entry {\code {NO{\_}SYS{\_}SIGLIST}}{418}
+\entry {non-constant initializers}{130}
+\entry {non-static inline function}{142}
+\entry {\code {NON{\_}SAVING{\_}SETJMP}}{335}
+\entry {\code {nongcc{\_}SI{\_}type}}{373}
+\entry {\code {nongcc{\_}word{\_}type}}{373}
+\entry {nonoffsettable memory reference}{271}
+\entry {\code {nop} instruction pattern}{287}
+\entry {\code {noreturn} function attribute}{134}
+\entry {\code {not}}{234}
+\entry {\code {not} and attributes}{307}
+\entry {not equal}{236}
+\entry {not using constraints}{279}
+\entry {\code {not}, canonicalization of}{294}
+\entry {\code {note}}{248}
+\entry {\code {NOTE{\_}INSN{\_}BLOCK{\_}BEG}}{248}
+\entry {\code {NOTE{\_}INSN{\_}BLOCK{\_}END}}{248}
+\entry {\code {NOTE{\_}INSN{\_}DELETED}}{248}
+\entry {\code {NOTE{\_}INSN{\_}FUNCTION{\_}END}}{248}
+\entry {\code {NOTE{\_}INSN{\_}LOOP{\_}BEG}}{248}
+\entry {\code {NOTE{\_}INSN{\_}LOOP{\_}CONT}}{248}
+\entry {\code {NOTE{\_}INSN{\_}LOOP{\_}END}}{248}
+\entry {\code {NOTE{\_}INSN{\_}LOOP{\_}VTOP}}{248}
+\entry {\code {NOTE{\_}INSN{\_}SETJMP}}{248}
+\entry {\code {NOTE{\_}LINE{\_}NUMBER}}{248}
+\entry {\code {NOTE{\_}SOURCE{\_}FILE}}{248}
+\entry {\code {NOTICE{\_}UPDATE{\_}CC}}{377}
+\entry {\code {NUM{\_}MACHINE{\_}MODES}}{225}
 \initial {O}
-\entry {\samp {o} in constraint}{273}
-\entry {\code {OBJC{\_}GEN{\_}METHOD{\_}LABEL}}{399}
-\entry {\code {OBJC{\_}INCLUDE{\_}PATH}}{82}
-\entry {\code {OBJC{\_}INT{\_}SELECTORS}}{339}
-\entry {\code {OBJC{\_}PROLOGUE}}{392}
-\entry {\code {OBJC{\_}SELECTORS{\_}WITHOUT{\_}LABELS}}{340}
-\entry {\code {OBJECT{\_}FORMAT{\_}COFF}}{403}
-\entry {\code {OBJECT{\_}FORMAT{\_}ROSE}}{403}
-\entry {Objective C}{17}
-\entry {\code {OBSTACK{\_}CHUNK{\_}ALLOC}}{426}
-\entry {\code {OBSTACK{\_}CHUNK{\_}FREE}}{426}
-\entry {\code {OBSTACK{\_}CHUNK{\_}SIZE}}{426}
-\entry {\code {obstack{\_}free}}{100}
-\entry {OCS (88k)}{64}
-\entry {offsettable address}{273}
-\entry {old-style function definitions}{141}
-\entry {omitted middle-operands}{128}
-\entry {\code {one{\_}cmpl\var {m}2} instruction pattern}{289}
-\entry {\code {ONLY{\_}INT{\_}FIELDS}}{425}
-\entry {open coding}{146}
-\entry {operand access}{222}
-\entry {operand constraints}{273}
-\entry {operand substitution}{269}
-\entry {\code {operands}}{264}
-\entry {\code {OPTIMIZATION{\_}OPTIONS}}{331}
-\entry {optimize options}{44}
-\entry {optional hardware or system features}{330}
-\entry {options to control warnings}{34}
-\entry {options, C{\tt\char43}{\tt\char43}}{30}
-\entry {options, code generation}{78}
-\entry {options, debugging}{41}
-\entry {options, dialect}{27}
-\entry {options, directory search}{53}
-\entry {options, GNU CC command}{19}
-\entry {options, grouping}{19}
-\entry {options, linking}{51}
-\entry {options, optimization}{44}
-\entry {options, order}{19}
-\entry {options, preprocessor}{48}
-\entry {order of evaluation, side effects}{191}
-\entry {order of options}{19}
-\entry {order of register allocation}{342}
-\entry {\code {ORDER{\_}REGS{\_}FOR{\_}LOCAL{\_}ALLOC}}{342}
-\entry {Ordering of Patterns}{296}
-\entry {other directory, compilation in}{106}
-\entry {\code {OUTGOING{\_}REG{\_}PARM{\_}STACK{\_}SPACE}}{359}
-\entry {\code {OUTGOING{\_}REGNO}}{342}
-\entry {output file option}{25}
-\entry {output of assembler code}{391}
-\entry {output statements}{271}
-\entry {output templates}{269}
-\entry {\code {output{\_}addr{\_}const}}{393}
-\entry {\code {output{\_}asm{\_}insn}}{272}
-\entry {overflow while constant folding}{417}
-\entry {\code {OVERLAPPING{\_}REGNO{\_}P}}{346}
-\entry {overloaded virtual fn, warning}{40}
-\entry {\code {OVERRIDE{\_}OPTIONS}}{331}
+\entry {\samp {o} in constraint}{267}
+\entry {\code {OBJC{\_}GEN{\_}METHOD{\_}LABEL}}{392}
+\entry {\code {OBJC{\_}INCLUDE{\_}PATH}}{78}
+\entry {\code {OBJC{\_}INT{\_}SELECTORS}}{333}
+\entry {\code {OBJC{\_}PROLOGUE}}{386}
+\entry {\code {OBJC{\_}SELECTORS{\_}WITHOUT{\_}LABELS}}{334}
+\entry {\code {OBJECT{\_}FORMAT{\_}COFF}}{396}
+\entry {\code {OBJECT{\_}FORMAT{\_}ROSE}}{396}
+\entry {Objective C}{15}
+\entry {\code {OBSTACK{\_}CHUNK{\_}ALLOC}}{418}
+\entry {\code {OBSTACK{\_}CHUNK{\_}FREE}}{418}
+\entry {\code {OBSTACK{\_}CHUNK{\_}SIZE}}{418}
+\entry {\code {obstack{\_}free}}{95}
+\entry {OCS (88k)}{61}
+\entry {offsettable address}{267}
+\entry {old-style function definitions}{137}
+\entry {omitted middle-operands}{124}
+\entry {\code {one{\_}cmpl\var {m}2} instruction pattern}{283}
+\entry {\code {ONLY{\_}INT{\_}FIELDS}}{417}
+\entry {open coding}{141}
+\entry {operand access}{216}
+\entry {operand constraints}{267}
+\entry {operand substitution}{263}
+\entry {\code {operands}}{258}
+\entry {\code {OPTIMIZATION{\_}OPTIONS}}{325}
+\entry {optimize options}{41}
+\entry {optional hardware or system features}{324}
+\entry {options to control warnings}{32}
+\entry {options, C{\tt\char43}{\tt\char43}}{28}
+\entry {options, code generation}{74}
+\entry {options, debugging}{37}
+\entry {options, dialect}{25}
+\entry {options, directory search}{50}
+\entry {options, GNU CC command}{17}
+\entry {options, grouping}{17}
+\entry {options, linking}{48}
+\entry {options, optimization}{41}
+\entry {options, order}{17}
+\entry {options, preprocessor}{45}
+\entry {order of evaluation, side effects}{185}
+\entry {order of options}{17}
+\entry {order of register allocation}{336}
+\entry {\code {ORDER{\_}REGS{\_}FOR{\_}LOCAL{\_}ALLOC}}{336}
+\entry {Ordering of Patterns}{290}
+\entry {other directory, compilation in}{101}
+\entry {\code {OUTGOING{\_}REG{\_}PARM{\_}STACK{\_}SPACE}}{353}
+\entry {\code {OUTGOING{\_}REGNO}}{336}
+\entry {output file option}{23}
+\entry {output of assembler code}{385}
+\entry {output statements}{265}
+\entry {output templates}{263}
+\entry {\code {output{\_}addr{\_}const}}{387}
+\entry {\code {output{\_}asm{\_}insn}}{266}
+\entry {overflow while constant folding}{410}
+\entry {\code {OVERLAPPING{\_}REGNO{\_}P}}{340}
+\entry {overloaded virtual fn, warning}{37}
+\entry {\code {OVERRIDE{\_}OPTIONS}}{325}
 \initial {P}
-\entry {\samp {p} in constraint}{275}
-\entry {\code {packed} attribute}{144}
-\entry {\code {parallel}}{247}
-\entry {parameter forward declaration}{132}
-\entry {parameters, miscellaneous}{417}
-\entry {\code {PARM{\_}BOUNDARY}}{334}
-\entry {parser generator, Bison}{90}
-\entry {parsing pass}{215}
-\entry {passes and files of the compiler}{215}
-\entry {passing arguments}{213}
-\entry {\code {PATH{\_}SEPARATOR}}{427}
-\entry {\code {PATTERN}}{255}
-\entry {pattern conditions}{264}
-\entry {pattern names}{286}
-\entry {Pattern Ordering}{296}
-\entry {patterns}{263}
-\entry {\code {pc}}{238}
-\entry {\code {pc} and attributes}{318}
-\entry {\code {pc}, RTL sharing}{261}
-\entry {\code {pc{\_}rtx}}{238}
-\entry {\code {PCC{\_}BITFIELD{\_}TYPE{\_}MATTERS}}{335}
-\entry {\code {PCC{\_}STATIC{\_}STRUCT{\_}RETURN}}{366}
-\entry {\code {PDImode}}{229}
-\entry {peephole optimization}{219}
-\entry {peephole optimization, RTL representation}{248}
-\entry {peephole optimizer definitions}{301}
-\entry {percent sign}{269}
-\entry {\code {perform{\_}\dots {}}}{379}
-\entry {PIC}{80, 390}
-\entry {\code {PIC{\_}OFFSET{\_}TABLE{\_}REGNUM}}{390}
-\entry {\code {plus}}{238}
-\entry {\code {plus} and attributes}{313}
-\entry {\code {plus}, canonicalization of}{300}
-\entry {\code {Pmode}}{421}
-\entry {pointer arguments}{140}
-\entry {\code {POINTER{\_}SIZE}}{333}
-\entry {portability}{211}
-\entry {portions of temporary objects, pointers to}{186}
-\entry {position independent code}{390}
-\entry {\code {post{\_}dec}}{250}
-\entry {\code {post{\_}inc}}{250}
-\entry {\code {pragma}}{422}
-\entry {pragma, reason for not using}{141}
-\entry {pragmas in C{\tt\char43}{\tt\char43}, effect on inlining}{163}
-\entry {pragmas, interface and implementation}{162}
-\entry {\code {pre{\_}dec}}{249}
-\entry {\code {pre{\_}inc}}{250}
-\entry {predefined macros}{329}
-\entry {\code {PREDICATE{\_}CODES}}{417}
-\entry {\code {PREFERRED{\_}DEBUGGING{\_}TYPE}}{409}
-\entry {\code {PREFERRED{\_}OUTPUT{\_}RELOAD{\_}CLASS}}{349}
-\entry {\code {PREFERRED{\_}RELOAD{\_}CLASS}}{349}
-\entry {preprocessing numbers}{183}
-\entry {preprocessing tokens}{183}
-\entry {preprocessor options}{48}
-\entry {\code {PRESERVE{\_}DEATH{\_}INFO{\_}REGNO{\_}P}}{346}
-\entry {\code {prev{\_}cc0{\_}setter}}{299}
-\entry {\code {PREV{\_}INSN}}{251}
-\entry {\code {prev{\_}nonnote{\_}insn}}{303}
-\entry {\code {PRINT{\_}OPERAND}}{404}
-\entry {\code {PRINT{\_}OPERAND{\_}ADDRESS}}{405}
-\entry {\code {PRINT{\_}OPERAND{\_}PUNCT{\_}VALID{\_}P}}{405}
-\entry {processor selection (29k)}{62}
-\entry {product}{239}
-\entry {\code {prof}}{42}
-\entry {\code {PROFILE{\_}BEFORE{\_}PROLOGUE}}{370}
-\entry {profiling, code generation}{370}
-\entry {program counter}{238}
-\entry {prologue}{367}
-\entry {\code {PROMOTE{\_}FOR{\_}CALL{\_}ONLY}}{334}
-\entry {\code {PROMOTE{\_}FUNCTION{\_}ARGS}}{333}
-\entry {\code {PROMOTE{\_}FUNCTION{\_}RETURN}}{333}
-\entry {\code {PROMOTE{\_}MODE}}{333}
-\entry {\code {PROMOTE{\_}PROTOTYPES}}{358}
-\entry {promotion of formal parameters}{141}
-\entry {pseudo registers}{234}
-\entry {\code {PSImode}}{229}
-\entry {\code {PTRDIFF{\_}TYPE}}{339}
-\entry {push address instruction}{275}
-\entry {\code {PUSH{\_}ROUNDING}}{358}
-\entry {\code {PUSH{\_}ROUNDING}, interaction with \code {STACK{\_}BOUNDARY}}{334}
-\entry {\code {PUT{\_}CODE}}{221}
-\entry {\code {PUT{\_}MODE}}{231}
-\entry {\code {PUT{\_}REG{\_}NOTE{\_}KIND}}{256}
-\entry {\code {PUT{\_}SDB{\_}\dots {}}}{414}
-\entry {\code {putenv}}{426}
+\entry {\samp {p} in constraint}{269}
+\entry {\code {packed} attribute}{140}
+\entry {\code {parallel}}{241}
+\entry {parameter forward declaration}{128}
+\entry {parameters, miscellaneous}{410}
+\entry {\code {PARM{\_}BOUNDARY}}{327}
+\entry {parser generator, Bison}{86}
+\entry {parsing pass}{209}
+\entry {passes and files of the compiler}{209}
+\entry {passing arguments}{207}
+\entry {\code {PATTERN}}{249}
+\entry {pattern conditions}{258}
+\entry {pattern names}{280}
+\entry {Pattern Ordering}{290}
+\entry {patterns}{257}
+\entry {\code {pc}}{232}
+\entry {\code {pc} and attributes}{312}
+\entry {\code {pc}, RTL sharing}{255}
+\entry {\code {pc{\_}rtx}}{232}
+\entry {\code {PCC{\_}BITFIELD{\_}TYPE{\_}MATTERS}}{329}
+\entry {\code {PCC{\_}STATIC{\_}STRUCT{\_}RETURN}}{360}
+\entry {\code {PDImode}}{223}
+\entry {peephole optimization}{213}
+\entry {peephole optimization, RTL representation}{242}
+\entry {peephole optimizer definitions}{295}
+\entry {percent sign}{263}
+\entry {\code {perform{\_}\dots {}}}{373}
+\entry {PIC}{75, 383}
+\entry {\code {PIC{\_}OFFSET{\_}TABLE{\_}REGNUM}}{384}
+\entry {\code {plus}}{232}
+\entry {\code {plus} and attributes}{307}
+\entry {\code {plus}, canonicalization of}{294}
+\entry {\code {Pmode}}{414}
+\entry {pointer arguments}{135}
+\entry {\code {POINTER{\_}SIZE}}{327}
+\entry {portability}{205}
+\entry {portions of temporary objects, pointers to}{180}
+\entry {position independent code}{383}
+\entry {\code {post{\_}dec}}{244}
+\entry {\code {post{\_}inc}}{244}
+\entry {\code {pragma}}{414}
+\entry {pragma, reason for not using}{136}
+\entry {pragmas in C{\tt\char43}{\tt\char43}, effect on inlining}{159}
+\entry {pragmas, interface and implementation}{158}
+\entry {\code {pre{\_}dec}}{243}
+\entry {\code {pre{\_}inc}}{244}
+\entry {predefined macros}{323}
+\entry {\code {PREDICATE{\_}CODES}}{410}
+\entry {\code {PREFERRED{\_}DEBUGGING{\_}TYPE}}{402}
+\entry {\code {PREFERRED{\_}OUTPUT{\_}RELOAD{\_}CLASS}}{343}
+\entry {\code {PREFERRED{\_}RELOAD{\_}CLASS}}{343}
+\entry {preprocessing numbers}{177}
+\entry {preprocessing tokens}{177}
+\entry {preprocessor options}{45}
+\entry {\code {PRESERVE{\_}DEATH{\_}INFO{\_}REGNO{\_}P}}{340}
+\entry {\code {prev{\_}cc0{\_}setter}}{293}
+\entry {\code {PREV{\_}INSN}}{245}
+\entry {\code {prev{\_}nonnote{\_}insn}}{297}
+\entry {\code {PRINT{\_}OPERAND}}{398}
+\entry {\code {PRINT{\_}OPERAND{\_}ADDRESS}}{398}
+\entry {\code {PRINT{\_}OPERAND{\_}PUNCT{\_}VALID{\_}P}}{398}
+\entry {processor selection (29k)}{59}
+\entry {product}{233}
+\entry {\code {prof}}{39}
+\entry {\code {PROFILE{\_}BEFORE{\_}PROLOGUE}}{364}
+\entry {profiling, code generation}{364}
+\entry {program counter}{232}
+\entry {prologue}{361}
+\entry {\code {PROMOTE{\_}FOR{\_}CALL{\_}ONLY}}{327}
+\entry {\code {PROMOTE{\_}FUNCTION{\_}ARGS}}{327}
+\entry {\code {PROMOTE{\_}FUNCTION{\_}RETURN}}{327}
+\entry {\code {PROMOTE{\_}MODE}}{327}
+\entry {\code {PROMOTE{\_}PROTOTYPES}}{352}
+\entry {promotion of formal parameters}{137}
+\entry {pseudo registers}{228}
+\entry {\code {PSImode}}{223}
+\entry {\code {PTRDIFF{\_}TYPE}}{333}
+\entry {push address instruction}{269}
+\entry {\code {PUSH{\_}ROUNDING}}{352}
+\entry {\code {PUSH{\_}ROUNDING}, interaction with \code {STACK{\_}BOUNDARY}}{328}
+\entry {\code {PUT{\_}CODE}}{215}
+\entry {\code {PUT{\_}MODE}}{225}
+\entry {\code {PUT{\_}REG{\_}NOTE{\_}KIND}}{250}
+\entry {\code {PUT{\_}SDB{\_}\dots {}}}{407}
+\entry {\code {putenv}}{418}
 \initial {Q}
-\entry {\samp {Q}, in constraint}{275}
-\entry {\code {QImode}}{229}
-\entry {\code {QImode}, in \code {insn}}{254}
-\entry {\code {qsort}, and global register variables}{153}
-\entry {question mark}{278}
-\entry {quotient}{239}
+\entry {\samp {Q}, in constraint}{269}
+\entry {\code {QImode}}{223}
+\entry {\code {QImode}, in \code {insn}}{248}
+\entry {\code {qsort}, and global register variables}{149}
+\entry {question mark}{272}
+\entry {quotient}{233}
 \initial {R}
-\entry {\samp {r} in constraint}{273}
-\entry {r0-relative references (88k)}{65}
-\entry {ranges in case statements}{137}
-\entry {read-only strings}{180}
-\entry {\code {READONLY{\_}DATA{\_}SECTION}}{389}
-\entry {\code {REAL{\_}ARITHMETIC}}{416}
-\entry {\code {REAL{\_}INFINITY}}{416}
-\entry {\code {REAL{\_}NM{\_}FILE{\_}NAME}}{403}
-\entry {\code {REAL{\_}VALUE{\_}ATOF}}{416}
-\entry {\code {REAL{\_}VALUE{\_}FIX}}{415}
-\entry {\code {REAL{\_}VALUE{\_}FROM{\_}INT}}{417}
-\entry {\code {REAL{\_}VALUE{\_}ISINF}}{416}
-\entry {\code {REAL{\_}VALUE{\_}ISNAN}}{416}
-\entry {\code {REAL{\_}VALUE{\_}LDEXP}}{415}
-\entry {\code {REAL{\_}VALUE{\_}NEGATE}}{417}
-\entry {\code {REAL{\_}VALUE{\_}RNDZINT}}{416}
-\entry {\code {REAL{\_}VALUE{\_}TO{\_}DECIMAL}}{395}
-\entry {\code {REAL{\_}VALUE{\_}TO{\_}INT}}{417}
-\entry {\code {REAL{\_}VALUE{\_}TO{\_}TARGET{\_}DOUBLE}}{395}
-\entry {\code {REAL{\_}VALUE{\_}TO{\_}TARGET{\_}LONG{\_}DOUBLE}}{395}
-\entry {\code {REAL{\_}VALUE{\_}TO{\_}TARGET{\_}SINGLE}}{395}
-\entry {\code {REAL{\_}VALUE{\_}TRUNCATE}}{417}
-\entry {\code {REAL{\_}VALUE{\_}TYPE}}{415}
-\entry {\code {REAL{\_}VALUE{\_}UNSIGNED{\_}FIX}}{416}
-\entry {\code {REAL{\_}VALUE{\_}UNSIGNED{\_}RNDZINT}}{416}
-\entry {\code {REAL{\_}VALUES{\_}EQUAL}}{415}
-\entry {\code {REAL{\_}VALUES{\_}LESS}}{415}
-\entry {\code {recog{\_}operand}}{404}
-\entry {recognizing insns}{265}
-\entry {\code {reg}}{234}
-\entry {\code {reg} and \samp {/i}}{225}
-\entry {\code {reg} and \samp {/s}}{225}
-\entry {\code {reg} and \samp {/u}}{225}
-\entry {\code {reg} and \samp {/v}}{225}
-\entry {\code {reg}, RTL sharing}{261}
-\entry {\code {REG{\_}ALLOC{\_}ORDER}}{342}
-\entry {\code {REG{\_}CC{\_}SETTER}}{259}
-\entry {\code {REG{\_}CC{\_}USER}}{259}
-\entry {\code {REG{\_}CLASS{\_}CONTENTS}}{348}
-\entry {\code {REG{\_}CLASS{\_}FROM{\_}LETTER}}{349}
-\entry {\code {REG{\_}CLASS{\_}NAMES}}{348}
-\entry {\code {REG{\_}DEAD}}{256}
-\entry {\code {REG{\_}DEP{\_}ANTI}}{259}
-\entry {\code {REG{\_}DEP{\_}OUTPUT}}{259}
-\entry {\code {REG{\_}EQUAL}}{257}
-\entry {\code {REG{\_}EQUIV}}{257}
-\entry {\code {REG{\_}FUNCTION{\_}VALUE{\_}P}}{225}
-\entry {\code {REG{\_}INC}}{256}
-\entry {\code {REG{\_}LABEL}}{257}
-\entry {\code {REG{\_}LIBCALL}}{259}
-\entry {\code {REG{\_}LOOP{\_}TEST{\_}P}}{225}
-\entry {\code {reg{\_}names}}{405}
-\entry {\code {REG{\_}NO{\_}CONFLICT}}{257}
-\entry {\code {REG{\_}NONNEG}}{256}
-\entry {\code {REG{\_}NOTE{\_}KIND}}{256}
-\entry {\code {REG{\_}NOTES}}{255}
-\entry {\code {REG{\_}OK{\_}FOR{\_}BASE{\_}P}}{381}
-\entry {\code {REG{\_}OK{\_}FOR{\_}INDEX{\_}P}}{381}
-\entry {\code {REG{\_}OK{\_}STRICT}}{380}
-\entry {\code {REG{\_}PARM{\_}STACK{\_}SPACE}}{359}
-\entry {\code {REG{\_}PARM{\_}STACK{\_}SPACE}, and \code {FUNCTION{\_}ARG}}{361}
-\entry {\code {REG{\_}RETVAL}}{258}
-\entry {\code {REG{\_}UNUSED}}{258}
-\entry {\code {REG{\_}USERVAR{\_}P}}{225}
-\entry {\code {REG{\_}WAS{\_}0}}{258}
-\entry {register allocation}{218}
-\entry {register allocation order}{342}
-\entry {register allocation, stupid}{217}
-\entry {register class definitions}{347}
-\entry {register class preference constraints}{278}
-\entry {register class preference pass}{218}
-\entry {register pairs}{343}
-\entry {register positions in frame (88k)}{64}
-\entry {Register Transfer Language (RTL)}{221}
-\entry {register usage}{340}
-\entry {register use analysis}{217}
-\entry {register variable after \code {longjmp}}{154}
-\entry {register-to-stack conversion}{219}
-\entry {\code {REGISTER{\_}MOVE{\_}COST}}{386}
-\entry {\code {REGISTER{\_}NAMES}}{403}
-\entry {\code {register{\_}operand}}{266}
-\entry {\code {REGISTER{\_}PREFIX}}{405}
-\entry {registers}{147}
-\entry {registers arguments}{360}
-\entry {registers for local variables}{154}
-\entry {registers in constraints}{273}
-\entry {registers, global allocation}{152}
-\entry {registers, global variables in}{153}
-\entry {\code {REGNO{\_}OK{\_}FOR{\_}BASE{\_}P}}{349}
-\entry {\code {REGNO{\_}OK{\_}FOR{\_}INDEX{\_}P}}{349}
-\entry {\code {REGNO{\_}REG{\_}CLASS}}{348}
-\entry {\code {regs{\_}ever{\_}live}}{367}
-\entry {relative costs}{385}
-\entry {\code {RELATIVE{\_}PREFIX{\_}NOT{\_}LINKDIR}}{327}
-\entry {reload pass}{236}
-\entry {\code {reload{\_}completed}}{293}
-\entry {\code {reload{\_}in} instruction pattern}{287}
-\entry {\code {reload{\_}in{\_}progress}}{286}
-\entry {\code {reload{\_}out} instruction pattern}{287}
-\entry {reloading}{218}
-\entry {remainder}{239}
-\entry {reordering, warning}{38}
-\entry {reporting bugs}{193}
-\entry {representation of RTL}{221}
-\entry {rest argument (in macro)}{132}
-\entry {\code {rest{\_}of{\_}compilation}}{215}
-\entry {\code {rest{\_}of{\_}decl{\_}compilation}}{215}
-\entry {\code {restore{\_}stack{\_}block} instruction pattern}{294}
-\entry {\code {restore{\_}stack{\_}function} instruction pattern}{294}
-\entry {\code {restore{\_}stack{\_}nonlocal} instruction pattern}{294}
-\entry {\code {return}}{246}
-\entry {\code {return} instruction pattern}{293}
-\entry {return value of \code {main}}{209}
-\entry {return value, named, in C{\tt\char43}{\tt\char43}}{159}
-\entry {return values in registers}{363}
-\entry {\code {return}, in C{\tt\char43}{\tt\char43} function header}{159}
-\entry {\code {RETURN{\_}ADDR{\_}IN{\_}PREVIOUS{\_}FRAME}}{355}
-\entry {\code {RETURN{\_}ADDR{\_}RTX}}{355}
-\entry {\code {RETURN{\_}IN{\_}MEMORY}}{365}
-\entry {\code {RETURN{\_}POPS{\_}ARGS}}{360}
-\entry {returning aggregate values}{365}
-\entry {returning structures and unions}{213}
-\entry {\code {REVERSIBLE{\_}CC{\_}MODE}}{384}
-\entry {right rotate}{240}
-\entry {right shift}{240}
-\entry {\code {rotate}}{240}
-\entry {\code {rotatert}}{240}
-\entry {\code {rotl\var {m}3} instruction pattern}{289}
-\entry {\code {rotr\var {m}3} instruction pattern}{289}
-\entry {\code {ROUND{\_}TYPE{\_}ALIGN}}{336}
-\entry {\code {ROUND{\_}TYPE{\_}SIZE}}{336}
-\entry {RS/6000 and PowerPC Options}{67}
-\entry {RT options}{69}
-\entry {RT PC}{178}
-\entry {RTL addition}{238}
-\entry {RTL comparison}{238}
-\entry {RTL comparison operations}{241}
-\entry {RTL constant expression types}{232}
-\entry {RTL constants}{232}
-\entry {RTL declarations}{244}
-\entry {RTL difference}{238}
-\entry {RTL expression}{221}
-\entry {RTL expressions for arithmetic}{238}
-\entry {RTL format}{222}
-\entry {RTL format characters}{222}
-\entry {RTL function-call insns}{259}
-\entry {RTL generation}{216}
-\entry {RTL insn template}{265}
-\entry {RTL integers}{221}
-\entry {RTL memory expressions}{234}
-\entry {RTL object types}{221}
-\entry {RTL postdecrement}{249}
-\entry {RTL postincrement}{249}
-\entry {RTL predecrement}{249}
-\entry {RTL preincrement}{249}
-\entry {RTL register expressions}{234}
-\entry {RTL representation}{221}
-\entry {RTL side effect expressions}{245}
-\entry {RTL strings}{221}
-\entry {RTL structure sharing assumptions}{261}
-\entry {RTL subtraction}{238}
-\entry {RTL sum}{238}
-\entry {RTL vectors}{221}
-\entry {RTX (See RTL)}{221}
-\entry {\code {RTX{\_}COSTS}}{385}
-\entry {\code {RTX{\_}INTEGRATED{\_}P}}{226}
-\entry {\code {RTX{\_}UNCHANGING{\_}P}}{225}
-\entry {run-time conventions}{213}
-\entry {run-time options}{78}
-\entry {run-time target specification}{329}
+\entry {\samp {r} in constraint}{267}
+\entry {r0-relative references (88k)}{61}
+\entry {ranges in case statements}{133}
+\entry {read-only strings}{174}
+\entry {\code {READONLY{\_}DATA{\_}SECTION}}{382}
+\entry {\code {REAL{\_}ARITHMETIC}}{409}
+\entry {\code {REAL{\_}INFINITY}}{409}
+\entry {\code {REAL{\_}NM{\_}FILE{\_}NAME}}{396}
+\entry {\code {REAL{\_}VALUE{\_}ATOF}}{409}
+\entry {\code {REAL{\_}VALUE{\_}FIX}}{408}
+\entry {\code {REAL{\_}VALUE{\_}FROM{\_}INT}}{410}
+\entry {\code {REAL{\_}VALUE{\_}ISINF}}{409}
+\entry {\code {REAL{\_}VALUE{\_}ISNAN}}{409}
+\entry {\code {REAL{\_}VALUE{\_}LDEXP}}{408}
+\entry {\code {REAL{\_}VALUE{\_}NEGATE}}{410}
+\entry {\code {REAL{\_}VALUE{\_}RNDZINT}}{409}
+\entry {\code {REAL{\_}VALUE{\_}TO{\_}DECIMAL}}{389}
+\entry {\code {REAL{\_}VALUE{\_}TO{\_}INT}}{410}
+\entry {\code {REAL{\_}VALUE{\_}TO{\_}TARGET{\_}DOUBLE}}{388}
+\entry {\code {REAL{\_}VALUE{\_}TO{\_}TARGET{\_}LONG{\_}DOUBLE}}{388}
+\entry {\code {REAL{\_}VALUE{\_}TO{\_}TARGET{\_}SINGLE}}{388}
+\entry {\code {REAL{\_}VALUE{\_}TRUNCATE}}{410}
+\entry {\code {REAL{\_}VALUE{\_}TYPE}}{408}
+\entry {\code {REAL{\_}VALUE{\_}UNSIGNED{\_}FIX}}{409}
+\entry {\code {REAL{\_}VALUE{\_}UNSIGNED{\_}RNDZINT}}{409}
+\entry {\code {REAL{\_}VALUES{\_}EQUAL}}{408}
+\entry {\code {REAL{\_}VALUES{\_}LESS}}{408}
+\entry {\code {recog{\_}operand}}{397}
+\entry {recognizing insns}{259}
+\entry {\code {reg}}{228}
+\entry {\code {reg} and \samp {/i}}{219}
+\entry {\code {reg} and \samp {/s}}{219}
+\entry {\code {reg} and \samp {/u}}{219}
+\entry {\code {reg} and \samp {/v}}{219}
+\entry {\code {reg}, RTL sharing}{255}
+\entry {\code {REG{\_}ALLOC{\_}ORDER}}{336}
+\entry {\code {REG{\_}CC{\_}SETTER}}{253}
+\entry {\code {REG{\_}CC{\_}USER}}{253}
+\entry {\code {REG{\_}CLASS{\_}CONTENTS}}{342}
+\entry {\code {REG{\_}CLASS{\_}FROM{\_}LETTER}}{342}
+\entry {\code {REG{\_}CLASS{\_}NAMES}}{342}
+\entry {\code {REG{\_}DEAD}}{250}
+\entry {\code {REG{\_}DEP{\_}ANTI}}{253}
+\entry {\code {REG{\_}DEP{\_}OUTPUT}}{253}
+\entry {\code {REG{\_}EQUAL}}{251}
+\entry {\code {REG{\_}EQUIV}}{251}
+\entry {\code {REG{\_}FUNCTION{\_}VALUE{\_}P}}{219}
+\entry {\code {REG{\_}INC}}{250}
+\entry {\code {REG{\_}LABEL}}{251}
+\entry {\code {REG{\_}LIBCALL}}{253}
+\entry {\code {REG{\_}LOOP{\_}TEST{\_}P}}{219}
+\entry {\code {reg{\_}names}}{398}
+\entry {\code {REG{\_}NO{\_}CONFLICT}}{251}
+\entry {\code {REG{\_}NONNEG}}{250}
+\entry {\code {REG{\_}NOTE{\_}KIND}}{250}
+\entry {\code {REG{\_}NOTES}}{249}
+\entry {\code {REG{\_}OK{\_}FOR{\_}BASE{\_}P}}{375}
+\entry {\code {REG{\_}OK{\_}FOR{\_}INDEX{\_}P}}{375}
+\entry {\code {REG{\_}OK{\_}STRICT}}{374}
+\entry {\code {REG{\_}PARM{\_}STACK{\_}SPACE}}{352}
+\entry {\code {REG{\_}PARM{\_}STACK{\_}SPACE}, and \code {FUNCTION{\_}ARG}}{354}
+\entry {\code {REG{\_}RETVAL}}{252}
+\entry {\code {REG{\_}UNUSED}}{252}
+\entry {\code {REG{\_}USERVAR{\_}P}}{219}
+\entry {\code {REG{\_}WAS{\_}0}}{252}
+\entry {register allocation}{212}
+\entry {register allocation order}{336}
+\entry {register allocation, stupid}{211}
+\entry {register class definitions}{340}
+\entry {register class preference constraints}{272}
+\entry {register class preference pass}{212}
+\entry {register pairs}{337}
+\entry {register positions in frame (88k)}{61}
+\entry {Register Transfer Language (RTL)}{215}
+\entry {register usage}{334}
+\entry {register use analysis}{211}
+\entry {register variable after \code {longjmp}}{149}
+\entry {register-to-stack conversion}{213}
+\entry {\code {REGISTER{\_}MOVE{\_}COST}}{380}
+\entry {\code {REGISTER{\_}NAMES}}{397}
+\entry {\code {register{\_}operand}}{260}
+\entry {\code {REGISTER{\_}PREFIX}}{399}
+\entry {registers}{143}
+\entry {registers arguments}{354}
+\entry {registers for local variables}{150}
+\entry {registers in constraints}{267}
+\entry {registers, global allocation}{148}
+\entry {registers, global variables in}{148}
+\entry {\code {REGNO{\_}OK{\_}FOR{\_}BASE{\_}P}}{343}
+\entry {\code {REGNO{\_}OK{\_}FOR{\_}INDEX{\_}P}}{343}
+\entry {\code {REGNO{\_}REG{\_}CLASS}}{342}
+\entry {\code {regs{\_}ever{\_}live}}{361}
+\entry {relative costs}{378}
+\entry {\code {RELATIVE{\_}PREFIX{\_}NOT{\_}LINKDIR}}{321}
+\entry {reload pass}{230}
+\entry {\code {reload{\_}completed}}{287}
+\entry {\code {reload{\_}in} instruction pattern}{281}
+\entry {\code {reload{\_}in{\_}progress}}{280}
+\entry {\code {reload{\_}out} instruction pattern}{281}
+\entry {reloading}{212}
+\entry {remainder}{233}
+\entry {reporting bugs}{187}
+\entry {representation of RTL}{215}
+\entry {rest argument (in macro)}{128}
+\entry {\code {rest{\_}of{\_}compilation}}{209}
+\entry {\code {rest{\_}of{\_}decl{\_}compilation}}{209}
+\entry {\code {restore{\_}stack{\_}block} instruction pattern}{288}
+\entry {\code {restore{\_}stack{\_}function} instruction pattern}{288}
+\entry {\code {restore{\_}stack{\_}nonlocal} instruction pattern}{288}
+\entry {\code {return}}{240}
+\entry {\code {return} instruction pattern}{287}
+\entry {return value of \code {main}}{203}
+\entry {return value, named, in C{\tt\char43}{\tt\char43}}{155}
+\entry {return values in registers}{357}
+\entry {\code {return}, in C{\tt\char43}{\tt\char43} function header}{155}
+\entry {\code {RETURN{\_}ADDR{\_}IN{\_}PREVIOUS{\_}FRAME}}{349}
+\entry {\code {RETURN{\_}ADDR{\_}RTX}}{348}
+\entry {\code {RETURN{\_}IN{\_}MEMORY}}{359}
+\entry {\code {RETURN{\_}POPS{\_}ARGS}}{353}
+\entry {returning aggregate values}{359}
+\entry {returning structures and unions}{207}
+\entry {\code {REVERSIBLE{\_}CC{\_}MODE}}{378}
+\entry {right rotate}{234}
+\entry {right shift}{234}
+\entry {\code {rotate}}{234}
+\entry {\code {rotatert}}{234}
+\entry {\code {rotl\var {m}3} instruction pattern}{283}
+\entry {\code {rotr\var {m}3} instruction pattern}{283}
+\entry {\code {ROUND{\_}TYPE{\_}ALIGN}}{330}
+\entry {\code {ROUND{\_}TYPE{\_}SIZE}}{330}
+\entry {RS/6000 and PowerPC Options}{63}
+\entry {RT options}{65}
+\entry {RT PC}{172}
+\entry {RTL addition}{232}
+\entry {RTL comparison}{232}
+\entry {RTL comparison operations}{235}
+\entry {RTL constant expression types}{226}
+\entry {RTL constants}{226}
+\entry {RTL declarations}{238}
+\entry {RTL difference}{232}
+\entry {RTL expression}{215}
+\entry {RTL expressions for arithmetic}{232}
+\entry {RTL format}{216}
+\entry {RTL format characters}{216}
+\entry {RTL function-call insns}{253}
+\entry {RTL generation}{210}
+\entry {RTL insn template}{259}
+\entry {RTL integers}{215}
+\entry {RTL memory expressions}{228}
+\entry {RTL object types}{215}
+\entry {RTL postdecrement}{243}
+\entry {RTL postincrement}{243}
+\entry {RTL predecrement}{243}
+\entry {RTL preincrement}{243}
+\entry {RTL register expressions}{228}
+\entry {RTL representation}{215}
+\entry {RTL side effect expressions}{239}
+\entry {RTL strings}{215}
+\entry {RTL structure sharing assumptions}{255}
+\entry {RTL subtraction}{232}
+\entry {RTL sum}{232}
+\entry {RTL vectors}{215}
+\entry {RTX (See RTL)}{215}
+\entry {\code {RTX{\_}COSTS}}{379}
+\entry {\code {RTX{\_}INTEGRATED{\_}P}}{220}
+\entry {\code {RTX{\_}UNCHANGING{\_}P}}{219}
+\entry {run-time conventions}{207}
+\entry {run-time options}{74}
+\entry {run-time target specification}{323}
 \initial {S}
-\entry {\samp {s} in constraint}{274}
-\entry {\code {save{\_}stack{\_}block} instruction pattern}{294}
-\entry {\code {save{\_}stack{\_}function} instruction pattern}{294}
-\entry {\code {save{\_}stack{\_}nonlocal} instruction pattern}{294}
-\entry {\code {saveable{\_}obstack}}{381}
-\entry {scalars, returned as values}{363}
-\entry {\code {scanf}, and constant strings}{180}
-\entry {\code {SCCS{\_}DIRECTIVE}}{421}
-\entry {\code {SCHED{\_}GROUP{\_}P}}{227}
-\entry {scheduling, delayed branch}{219}
-\entry {scheduling, instruction}{218}
-\entry {\code {SCmode}}{229}
-\entry {\code {s\var {cond}} instruction pattern}{291}
-\entry {scope of a variable length array}{131}
-\entry {scope of declaration}{184}
-\entry {scope of external declarations}{181}
-\entry {\code {scratch}}{236}
-\entry {scratch operands}{236}
-\entry {\code {scratch}, RTL sharing}{261}
-\entry {\code {SDB{\_}ALLOW{\_}FORWARD{\_}REFERENCES}}{414}
-\entry {\code {SDB{\_}ALLOW{\_}UNKNOWN{\_}REFERENCES}}{414}
-\entry {\code {SDB{\_}DEBUGGING{\_}INFO}}{414}
-\entry {\code {SDB{\_}DELIM}}{414}
-\entry {\code {SDB{\_}GENERATE{\_}FAKE}}{414}
-\entry {search path}{53}
-\entry {second include path}{49}
-\entry {\code {SECONDARY{\_}INPUT{\_}RELOAD{\_}CLASS}}{350}
-\entry {\code {SECONDARY{\_}MEMORY{\_}NEEDED}}{351}
-\entry {\code {SECONDARY{\_}MEMORY{\_}NEEDED{\_}MODE}}{351}
-\entry {\code {SECONDARY{\_}MEMORY{\_}NEEDED{\_}RTX}}{351}
-\entry {\code {SECONDARY{\_}OUTPUT{\_}RELOAD{\_}CLASS}}{350}
-\entry {\code {SECONDARY{\_}RELOAD{\_}CLASS}}{350}
-\entry {\code {section} function attribute}{140}
-\entry {\code {section} variable attribute}{144}
-\entry {\code {SELECT{\_}CC{\_}MODE}}{384}
-\entry {\code {SELECT{\_}RTX{\_}SECTION}}{389}
-\entry {\code {SELECT{\_}SECTION}}{389}
-\entry {separate directory, compilation in}{106}
-\entry {\code {sequence}}{248}
-\entry {sequential consistency on 88k}{65}
-\entry {\code {set}}{245}
-\entry {\code {set{\_}attr}}{316}
-\entry {\code {set{\_}attr{\_}alternative}}{316}
-\entry {\code {SET{\_}DEFAULT{\_}TYPE{\_}ATTRIBUTES}}{422}
-\entry {\code {SET{\_}DEST}}{246}
-\entry {\code {SET{\_}SRC}}{246}
-\entry {\code {setjmp}}{154}
-\entry {\code {setjmp} incompatibilities}{181}
-\entry {\code {SETUP{\_}FRAME{\_}ADDRESSES}}{355}
-\entry {\code {SETUP{\_}INCOMING{\_}VARARGS}}{373}
-\entry {\code {SFmode}}{229}
-\entry {shared strings}{180}
-\entry {shared VMS run time system}{209}
-\entry {\code {SHARED{\_}SECTION{\_}ASM{\_}OP}}{388}
-\entry {sharing of RTL components}{261}
-\entry {shift}{240}
-\entry {\code {SHIFT{\_}COUNT{\_}TRUNCATED}}{419}
-\entry {\code {SHORT{\_}TYPE{\_}SIZE}}{338}
-\entry {side effect in ?:}{129}
-\entry {side effects, macro argument}{120}
-\entry {side effects, order of evaluation}{191}
-\entry {\code {sign{\_}extend}}{244}
-\entry {\code {sign{\_}extract}}{243}
-\entry {\code {sign{\_}extract}, canonicalization of}{301}
-\entry {\code {signature}}{166}
-\entry {\code {signature} in C{\tt\char43}{\tt\char43}, advantages}{167}
-\entry {signature member function default implemention}{167}
-\entry {signatures, C{\tt\char43}{\tt\char43}}{166}
-\entry {signed division}{239}
-\entry {signed maximum}{240}
-\entry {signed minimum}{240}
-\entry {\code {SIGNED{\_}CHAR{\_}SPEC}}{326}
-\entry {\code {SImode}}{229}
-\entry {simple constraints}{273}
-\entry {simplifications, arithmetic}{215}
-\entry {\code {sin}}{27}
-\entry {\code {SIZE{\_}TYPE}}{339}
-\entry {\code {sizeof}}{126}
-\entry {\code {SLOW{\_}BYTE{\_}ACCESS}}{386}
-\entry {\code {SLOW{\_}UNALIGNED{\_}ACCESS}}{387}
-\entry {\code {SLOW{\_}ZERO{\_}EXTEND}}{387}
-\entry {\code {SMALL{\_}REGISTER{\_}CLASSES}}{351}
-\entry {smaller data references (88k)}{65}
-\entry {smaller data references (MIPS)}{73}
-\entry {\code {smax}}{240}
-\entry {\code {smin}}{240}
-\entry {SPARC options}{58}
-\entry {specified registers}{152}
-\entry {specifying compiler version and target machine}{54}
-\entry {specifying hardware config}{56}
-\entry {specifying machine version}{54}
-\entry {specifying registers for local variables}{154}
-\entry {speed of instructions}{385}
-\entry {splitting instructions}{308}
-\entry {\code {sqrt}}{27, 240}
-\entry {\code {sqrt\var {m}2} instruction pattern}{289}
-\entry {square root}{240}
-\entry {\code {sscanf}, and constant strings}{180}
-\entry {stack arguments}{358}
-\entry {stack checks (29k)}{62}
-\entry {stack frame layout}{353}
-\entry {\code {STACK{\_}BOUNDARY}}{334}
-\entry {\code {STACK{\_}DYNAMIC{\_}OFFSET}}{354}
-\entry {\code {STACK{\_}DYNAMIC{\_}OFFSET} and virtual registers}{235}
-\entry {\code {STACK{\_}GROWS{\_}DOWNWARD}}{354}
-\entry {\code {STACK{\_}PARMS{\_}IN{\_}REG{\_}PARM{\_}AREA}}{360}
-\entry {\code {STACK{\_}POINTER{\_}OFFSET}}{354}
-\entry {\code {STACK{\_}POINTER{\_}OFFSET} and virtual registers}{235}
-\entry {\code {STACK{\_}POINTER{\_}REGNUM}}{355}
-\entry {\code {STACK{\_}POINTER{\_}REGNUM} and virtual registers}{235}
-\entry {\code {stack{\_}pointer{\_}rtx}}{356}
-\entry {\code {STACK{\_}REGS}}{345}
-\entry {stage1}{91}
-\entry {standard pattern names}{286}
-\entry {\code {STANDARD{\_}EXEC{\_}PREFIX}}{327}
-\entry {\code {STANDARD{\_}INCLUDE{\_}DIR}}{328}
-\entry {\code {STANDARD{\_}STARTFILE{\_}PREFIX}}{327}
-\entry {start files}{109}
-\entry {\code {STARTFILE{\_}SPEC}}{327}
-\entry {\code {STARTING{\_}FRAME{\_}OFFSET}}{354}
-\entry {\code {STARTING{\_}FRAME{\_}OFFSET} and virtual registers}{235}
-\entry {statements inside expressions}{119}
-\entry {static data in C{\tt\char43}{\tt\char43}, declaring and defining}{186}
-\entry {\code {STATIC{\_}CHAIN}}{356}
-\entry {\code {STATIC{\_}CHAIN{\_}INCOMING}}{356}
-\entry {\code {STATIC{\_}CHAIN{\_}INCOMING{\_}REGNUM}}{356}
-\entry {\code {STATIC{\_}CHAIN{\_}REGNUM}}{356}
-\entry {\file {stdarg.h} and register arguments}{361}
-\entry {\file {stdarg.h} and RT PC}{70}
-\entry {\code {STDC{\_}VALUE}}{330}
-\entry {storage layout}{332}
-\entry {\code {STORE{\_}FLAG{\_}VALUE}}{420}
-\entry {\samp {store{\_}multiple} instruction pattern}{288}
-\entry {storem bug (29k)}{62}
-\entry {\code {strcmp}}{27}
-\entry {\code {strcpy}}{27, 334}
-\entry {strength-reduction}{217}
-\entry {\code {STRICT{\_}ALIGNMENT}}{335}
-\entry {\code {strict{\_}low{\_}part}}{245}
-\entry {string constants}{180}
-\entry {string constants vs newline}{29}
-\entry {\code {STRIP{\_}NAME{\_}ENCODING}}{389}
-\entry {\code {strlen}}{27}
-\entry {\code {strlen\var {m}} instruction pattern}{290}
-\entry {\code {STRUCT{\_}VALUE}}{366}
-\entry {\code {STRUCT{\_}VALUE{\_}INCOMING}}{366}
-\entry {\code {STRUCT{\_}VALUE{\_}INCOMING{\_}REGNUM}}{366}
-\entry {\code {STRUCT{\_}VALUE{\_}REGNUM}}{366}
-\entry {structure passing (88k)}{67}
-\entry {structure value address}{365}
-\entry {\code {STRUCTURE{\_}SIZE{\_}BOUNDARY}}{335}
-\entry {structures}{182}
-\entry {structures, constructor expression}{134}
-\entry {structures, returning}{213}
-\entry {stupid register allocation}{217}
-\entry {\code {sub\var {m}3} instruction pattern}{288}
-\entry {submodel options}{56}
-\entry {\code {subreg}}{235}
-\entry {\code {subreg} and \samp {/s}}{225}
-\entry {\code {subreg} and \samp {/u}}{225}
-\entry {\code {subreg}, in \code {strict{\_}low{\_}part}}{245}
-\entry {\code {subreg}, special reload handling}{236}
-\entry {\code {SUBREG{\_}PROMOTED{\_}UNSIGNED{\_}P}}{225}
-\entry {\code {SUBREG{\_}PROMOTED{\_}VAR{\_}P}}{225}
-\entry {\code {SUBREG{\_}REG}}{236}
-\entry {\code {SUBREG{\_}WORD}}{236}
-\entry {subscripting}{133}
-\entry {subscripting and function values}{133}
-\entry {subtype polymorphism, C{\tt\char43}{\tt\char43}}{166}
-\entry {\code {SUCCESS{\_}EXIT{\_}CODE}}{425}
-\entry {suffixes for C{\tt\char43}{\tt\char43} source}{26}
-\entry {Sun installation}{112}
-\entry {suppressing warnings}{34}
-\entry {surprises in C{\tt\char43}{\tt\char43}}{185}
-\entry {SVr4}{65}
-\entry {\code {SWITCH{\_}TAKES{\_}ARG}}{325}
-\entry {\code {SWITCHES{\_}NEED{\_}SPACES}}{325}
-\entry {\code {symbol{\_}ref}}{233}
-\entry {\code {symbol{\_}ref} and \samp {/u}}{226}
-\entry {\code {symbol{\_}ref} and \samp {/v}}{226}
-\entry {\code {symbol{\_}ref}, RTL sharing}{261}
-\entry {\code {SYMBOL{\_}REF{\_}FLAG}}{226}
-\entry {\code {SYMBOL{\_}REF{\_}FLAG}, in \code {ENCODE{\_}SECTION{\_}INFO}}{389}
-\entry {\code {SYMBOL{\_}REF{\_}USED}}{226}
-\entry {symbolic label}{261}
-\entry {syntax checking}{34}
-\entry {synthesized methods, warning}{40}
-\entry {\code {sys{\_}siglist}}{427}
-\entry {\code {SYSTEM{\_}INCLUDE{\_}DIR}}{328}
+\entry {\samp {s} in constraint}{268}
+\entry {\code {save{\_}stack{\_}block} instruction pattern}{288}
+\entry {\code {save{\_}stack{\_}function} instruction pattern}{288}
+\entry {\code {save{\_}stack{\_}nonlocal} instruction pattern}{288}
+\entry {\code {saveable{\_}obstack}}{375}
+\entry {scalars, returned as values}{357}
+\entry {\code {scanf}, and constant strings}{174}
+\entry {\code {SCCS{\_}DIRECTIVE}}{414}
+\entry {\code {SCHED{\_}GROUP{\_}P}}{221}
+\entry {scheduling, delayed branch}{213}
+\entry {scheduling, instruction}{212}
+\entry {\code {SCmode}}{223}
+\entry {\code {s\var {cond}} instruction pattern}{285}
+\entry {scope of a variable length array}{127}
+\entry {scope of declaration}{178}
+\entry {scope of external declarations}{175}
+\entry {\code {scratch}}{230}
+\entry {scratch operands}{230}
+\entry {\code {scratch}, RTL sharing}{255}
+\entry {\code {SDB{\_}ALLOW{\_}FORWARD{\_}REFERENCES}}{407}
+\entry {\code {SDB{\_}ALLOW{\_}UNKNOWN{\_}REFERENCES}}{407}
+\entry {\code {SDB{\_}DEBUGGING{\_}INFO}}{407}
+\entry {\code {SDB{\_}DELIM}}{407}
+\entry {\code {SDB{\_}GENERATE{\_}FAKE}}{407}
+\entry {search path}{50}
+\entry {second include path}{46}
+\entry {\code {SECONDARY{\_}INPUT{\_}RELOAD{\_}CLASS}}{344}
+\entry {\code {SECONDARY{\_}MEMORY{\_}NEEDED}}{345}
+\entry {\code {SECONDARY{\_}MEMORY{\_}NEEDED{\_}MODE}}{345}
+\entry {\code {SECONDARY{\_}MEMORY{\_}NEEDED{\_}RTX}}{345}
+\entry {\code {SECONDARY{\_}OUTPUT{\_}RELOAD{\_}CLASS}}{344}
+\entry {\code {SECONDARY{\_}RELOAD{\_}CLASS}}{344}
+\entry {\code {section} function attribute}{136}
+\entry {\code {section} variable attribute}{140}
+\entry {\code {SELECT{\_}CC{\_}MODE}}{377}
+\entry {\code {SELECT{\_}RTX{\_}SECTION}}{383}
+\entry {\code {SELECT{\_}SECTION}}{382}
+\entry {separate directory, compilation in}{101}
+\entry {\code {sequence}}{242}
+\entry {sequential consistency on 88k}{61}
+\entry {\code {set}}{239}
+\entry {\code {set{\_}attr}}{310}
+\entry {\code {set{\_}attr{\_}alternative}}{310}
+\entry {\code {SET{\_}DEFAULT{\_}TYPE{\_}ATTRIBUTES}}{415}
+\entry {\code {SET{\_}DEST}}{240}
+\entry {\code {SET{\_}SRC}}{240}
+\entry {\code {setjmp}}{149}
+\entry {\code {setjmp} incompatibilities}{175}
+\entry {\code {SETUP{\_}FRAME{\_}ADDRESSES}}{348}
+\entry {\code {SETUP{\_}INCOMING{\_}VARARGS}}{367}
+\entry {\code {SFmode}}{223}
+\entry {shared strings}{174}
+\entry {shared VMS run time system}{203}
+\entry {\code {SHARED{\_}SECTION{\_}ASM{\_}OP}}{382}
+\entry {sharing of RTL components}{255}
+\entry {shift}{234}
+\entry {\code {SHIFT{\_}COUNT{\_}TRUNCATED}}{412}
+\entry {\code {SHORT{\_}TYPE{\_}SIZE}}{332}
+\entry {side effect in ?:}{125}
+\entry {side effects, macro argument}{116}
+\entry {side effects, order of evaluation}{185}
+\entry {\code {sign{\_}extend}}{238}
+\entry {\code {sign{\_}extract}}{237}
+\entry {\code {sign{\_}extract}, canonicalization of}{295}
+\entry {\code {signature}}{160}
+\entry {\code {signature} in C{\tt\char43}{\tt\char43}, advantages}{161}
+\entry {signature member function default implemention}{161}
+\entry {signatures, C{\tt\char43}{\tt\char43}}{160}
+\entry {signed division}{233}
+\entry {signed maximum}{234}
+\entry {signed minimum}{234}
+\entry {\code {SIGNED{\_}CHAR{\_}SPEC}}{320}
+\entry {\code {SImode}}{223}
+\entry {simple constraints}{267}
+\entry {simplifications, arithmetic}{209}
+\entry {\code {sin}}{25}
+\entry {\code {SIZE{\_}TYPE}}{333}
+\entry {\code {sizeof}}{122}
+\entry {\code {SLOW{\_}BYTE{\_}ACCESS}}{380}
+\entry {\code {SLOW{\_}UNALIGNED{\_}ACCESS}}{381}
+\entry {\code {SLOW{\_}ZERO{\_}EXTEND}}{380}
+\entry {\code {SMALL{\_}REGISTER{\_}CLASSES}}{345}
+\entry {smaller data references (88k)}{61}
+\entry {smaller data references (MIPS)}{69}
+\entry {\code {smax}}{234}
+\entry {\code {smin}}{234}
+\entry {SPARC options}{54}
+\entry {specified registers}{148}
+\entry {specifying compiler version and target machine}{51}
+\entry {specifying hardware config}{52}
+\entry {specifying machine version}{51}
+\entry {specifying registers for local variables}{150}
+\entry {speed of instructions}{378}
+\entry {splitting instructions}{302}
+\entry {\code {sqrt}}{25, 234}
+\entry {\code {sqrt\var {m}2} instruction pattern}{283}
+\entry {square root}{234}
+\entry {\code {sscanf}, and constant strings}{174}
+\entry {stack arguments}{352}
+\entry {stack checks (29k)}{59}
+\entry {stack frame layout}{347}
+\entry {\code {STACK{\_}BOUNDARY}}{328}
+\entry {\code {STACK{\_}DYNAMIC{\_}OFFSET}}{348}
+\entry {\code {STACK{\_}DYNAMIC{\_}OFFSET} and virtual registers}{229}
+\entry {\code {STACK{\_}GROWS{\_}DOWNWARD}}{347}
+\entry {\code {STACK{\_}PARMS{\_}IN{\_}REG{\_}PARM{\_}AREA}}{353}
+\entry {\code {STACK{\_}POINTER{\_}OFFSET}}{348}
+\entry {\code {STACK{\_}POINTER{\_}OFFSET} and virtual registers}{229}
+\entry {\code {STACK{\_}POINTER{\_}REGNUM}}{349}
+\entry {\code {STACK{\_}POINTER{\_}REGNUM} and virtual registers}{229}
+\entry {\code {stack{\_}pointer{\_}rtx}}{350}
+\entry {\code {STACK{\_}REGS}}{339}
+\entry {stage1}{87}
+\entry {standard pattern names}{280}
+\entry {\code {STANDARD{\_}EXEC{\_}PREFIX}}{321}
+\entry {\code {STANDARD{\_}INCLUDE{\_}DIR}}{322}
+\entry {\code {STANDARD{\_}STARTFILE{\_}PREFIX}}{321}
+\entry {start files}{104}
+\entry {\code {STARTFILE{\_}SPEC}}{321}
+\entry {\code {STARTING{\_}FRAME{\_}OFFSET}}{347}
+\entry {\code {STARTING{\_}FRAME{\_}OFFSET} and virtual registers}{229}
+\entry {statements inside expressions}{115}
+\entry {static data in C{\tt\char43}{\tt\char43}, declaring and defining}{180}
+\entry {\code {STATIC{\_}CHAIN}}{350}
+\entry {\code {STATIC{\_}CHAIN{\_}INCOMING}}{350}
+\entry {\code {STATIC{\_}CHAIN{\_}INCOMING{\_}REGNUM}}{349}
+\entry {\code {STATIC{\_}CHAIN{\_}REGNUM}}{349}
+\entry {\file {stdarg.h} and register arguments}{354}
+\entry {\file {stdarg.h} and RT PC}{66}
+\entry {\code {STDC{\_}VALUE}}{323}
+\entry {storage layout}{326}
+\entry {\code {STORE{\_}FLAG{\_}VALUE}}{412}
+\entry {\samp {store{\_}multiple} instruction pattern}{282}
+\entry {storem bug (29k)}{59}
+\entry {\code {strcmp}}{25}
+\entry {\code {strcpy}}{25, 328}
+\entry {strength-reduction}{211}
+\entry {\code {STRICT{\_}ALIGNMENT}}{329}
+\entry {\code {strict{\_}low{\_}part}}{239}
+\entry {string constants}{174}
+\entry {string constants vs newline}{27}
+\entry {\code {STRIP{\_}NAME{\_}ENCODING}}{383}
+\entry {\code {strlen}}{25}
+\entry {\code {strlen\var {m}} instruction pattern}{284}
+\entry {\code {STRUCT{\_}VALUE}}{359}
+\entry {\code {STRUCT{\_}VALUE{\_}INCOMING}}{360}
+\entry {\code {STRUCT{\_}VALUE{\_}INCOMING{\_}REGNUM}}{360}
+\entry {\code {STRUCT{\_}VALUE{\_}REGNUM}}{359}
+\entry {structure passing (88k)}{63}
+\entry {structure value address}{359}
+\entry {\code {STRUCTURE{\_}SIZE{\_}BOUNDARY}}{329}
+\entry {structures}{176}
+\entry {structures, constructor expression}{130}
+\entry {structures, returning}{207}
+\entry {stupid register allocation}{211}
+\entry {\code {sub\var {m}3} instruction pattern}{282}
+\entry {submodel options}{52}
+\entry {\code {subreg}}{229}
+\entry {\code {subreg} and \samp {/s}}{219}
+\entry {\code {subreg} and \samp {/u}}{219}
+\entry {\code {subreg}, in \code {strict{\_}low{\_}part}}{239}
+\entry {\code {subreg}, special reload handling}{230}
+\entry {\code {SUBREG{\_}PROMOTED{\_}UNSIGNED{\_}P}}{219}
+\entry {\code {SUBREG{\_}PROMOTED{\_}VAR{\_}P}}{219}
+\entry {\code {SUBREG{\_}REG}}{230}
+\entry {\code {SUBREG{\_}WORD}}{230}
+\entry {subscripting}{129}
+\entry {subscripting and function values}{129}
+\entry {subtype polymorphism, C{\tt\char43}{\tt\char43}}{160}
+\entry {\code {SUCCESS{\_}EXIT{\_}CODE}}{417}
+\entry {suffixes for C{\tt\char43}{\tt\char43} source}{24}
+\entry {Sun installation}{107}
+\entry {suppressing warnings}{32}
+\entry {surprises in C{\tt\char43}{\tt\char43}}{179}
+\entry {SVr4}{62}
+\entry {\code {SWITCH{\_}TAKES{\_}ARG}}{319}
+\entry {\code {SWITCHES{\_}NEED{\_}SPACES}}{319}
+\entry {\code {symbol{\_}ref}}{227}
+\entry {\code {symbol{\_}ref} and \samp {/u}}{220}
+\entry {\code {symbol{\_}ref} and \samp {/v}}{220}
+\entry {\code {symbol{\_}ref}, RTL sharing}{255}
+\entry {\code {SYMBOL{\_}REF{\_}FLAG}}{220}
+\entry {\code {SYMBOL{\_}REF{\_}FLAG}, in \code {ENCODE{\_}SECTION{\_}INFO}}{383}
+\entry {\code {SYMBOL{\_}REF{\_}USED}}{220}
+\entry {symbolic label}{255}
+\entry {syntax checking}{32}
+\entry {\code {sys{\_}siglist}}{419}
+\entry {\code {SYSTEM{\_}INCLUDE{\_}DIR}}{322}
 \initial {T}
-\entry {\code {tablejump} instruction pattern}{294}
-\entry {tagging insns}{315}
-\entry {tail recursion optimization}{216}
-\entry {target description macros}{325}
-\entry {target machine, specifying}{54}
-\entry {target options}{54}
-\entry {target specifications}{329}
-\entry {target-parameter-dependent code}{216}
-\entry {\code {TARGET{\_}BELL}}{340}
-\entry {\code {TARGET{\_}BS}}{340}
-\entry {\code {TARGET{\_}CR}}{340}
-\entry {\code {TARGET{\_}EDOM}}{377}
-\entry {\code {TARGET{\_}FF}}{340}
-\entry {\code {TARGET{\_}FLOAT{\_}FORMAT}}{337}
-\entry {\code {TARGET{\_}MEM{\_}FUNCTIONS}}{378}
-\entry {\code {TARGET{\_}NEWLINE}}{340}
-\entry {\code {TARGET{\_}OPTIONS}}{331}
-\entry {\code {TARGET{\_}SWITCHES}}{330}
-\entry {\code {TARGET{\_}TAB}}{340}
-\entry {\code {TARGET{\_}VERSION}}{331}
-\entry {\code {TARGET{\_}VT}}{340}
-\entry {\code {TCmode}}{229}
-\entry {\code {tcov}}{42}
-\entry {template debugging}{38}
-\entry {template instantiation}{164}
-\entry {temporaries, lifetime of}{186}
-\entry {termination routines}{399}
-\entry {\code {text{\_}section}}{388}
-\entry {\code {TEXT{\_}SECTION{\_}ASM{\_}OP}}{388}
-\entry {\code {TFmode}}{229}
-\entry {thunks}{122}
-\entry {\code {TImode}}{229}
-\entry {\file {tm.h} macros}{325}
-\entry {\code {TMPDIR}}{81}
-\entry {top level of compiler}{215}
-\entry {traditional C language}{28}
-\entry {\code {TRADITIONAL{\_}RETURN{\_}FLOAT}}{364}
-\entry {\code {TRAMPOLINE{\_}ALIGNMENT}}{374}
-\entry {\code {TRAMPOLINE{\_}SECTION}}{374}
-\entry {\code {TRAMPOLINE{\_}SIZE}}{374}
-\entry {\code {TRAMPOLINE{\_}TEMPLATE}}{374}
-\entry {trampolines for nested functions}{373}
-\entry {\code {TRANSFER{\_}FROM{\_}TRAMPOLINE}}{376}
-\entry {\code {TRULY{\_}NOOP{\_}TRUNCATION}}{419}
-\entry {\code {truncate}}{244}
-\entry {\code {trunc\var {mn}} instruction pattern}{290}
-\entry {\code {tst\var {m}} instruction pattern}{289}
-\entry {type abstraction, C{\tt\char43}{\tt\char43}}{166}
-\entry {type alignment}{143}
-\entry {typedef names as function parameters}{182}
-\entry {\code {typeof}}{126}
+\entry {\code {tablejump} instruction pattern}{288}
+\entry {tagging insns}{309}
+\entry {tail recursion optimization}{210}
+\entry {target description macros}{319}
+\entry {target machine, specifying}{51}
+\entry {target options}{51}
+\entry {target specifications}{323}
+\entry {target-parameter-dependent code}{210}
+\entry {\code {TARGET{\_}BELL}}{334}
+\entry {\code {TARGET{\_}BS}}{334}
+\entry {\code {TARGET{\_}CR}}{334}
+\entry {\code {TARGET{\_}EDOM}}{371}
+\entry {\code {TARGET{\_}FF}}{334}
+\entry {\code {TARGET{\_}FLOAT{\_}FORMAT}}{331}
+\entry {\code {TARGET{\_}MEM{\_}FUNCTIONS}}{372}
+\entry {\code {TARGET{\_}NEWLINE}}{334}
+\entry {\code {TARGET{\_}OPTIONS}}{324}
+\entry {\code {TARGET{\_}SWITCHES}}{324}
+\entry {\code {TARGET{\_}TAB}}{334}
+\entry {\code {TARGET{\_}VERSION}}{325}
+\entry {\code {TARGET{\_}VT}}{334}
+\entry {\code {TCmode}}{223}
+\entry {\code {tcov}}{39}
+\entry {template debugging}{35}
+\entry {temporaries, lifetime of}{180}
+\entry {termination routines}{393}
+\entry {\code {text{\_}section}}{382}
+\entry {\code {TEXT{\_}SECTION{\_}ASM{\_}OP}}{382}
+\entry {\code {TFmode}}{223}
+\entry {thunks}{118}
+\entry {\code {TImode}}{223}
+\entry {\file {tm.h} macros}{319}
+\entry {\code {TMPDIR}}{77}
+\entry {top level of compiler}{209}
+\entry {traditional C language}{26}
+\entry {\code {TRADITIONAL{\_}RETURN{\_}FLOAT}}{357}
+\entry {\code {TRAMPOLINE{\_}ALIGNMENT}}{368}
+\entry {\code {TRAMPOLINE{\_}SECTION}}{368}
+\entry {\code {TRAMPOLINE{\_}SIZE}}{368}
+\entry {\code {TRAMPOLINE{\_}TEMPLATE}}{368}
+\entry {trampolines for nested functions}{367}
+\entry {\code {TRANSFER{\_}FROM{\_}TRAMPOLINE}}{370}
+\entry {\code {TRULY{\_}NOOP{\_}TRUNCATION}}{412}
+\entry {\code {truncate}}{238}
+\entry {\code {trunc\var {mn}} instruction pattern}{284}
+\entry {\code {tst\var {m}} instruction pattern}{283}
+\entry {type abstraction, C{\tt\char43}{\tt\char43}}{160}
+\entry {type alignment}{139}
+\entry {typedef names as function parameters}{176}
+\entry {\code {typeof}}{122}
 \initial {U}
-\entry {\code {udiv}}{239}
-\entry {\code {UDIVDI3{\_}LIBCALL}}{377}
-\entry {\code {udiv\var {m}3} instruction pattern}{288}
-\entry {\code {udivmod\var {m}4} instruction pattern}{288}
-\entry {\code {UDIVSI3{\_}LIBCALL}}{376}
-\entry {Ultrix calling convention}{178}
-\entry {\code {umax}}{240}
-\entry {\code {umax\var {m}3} instruction pattern}{288}
-\entry {\code {umin}}{240}
-\entry {\code {umin\var {m}3} instruction pattern}{288}
-\entry {\code {umod}}{239}
-\entry {\code {UMODDI3{\_}LIBCALL}}{377}
-\entry {\code {umod\var {m}3} instruction pattern}{288}
-\entry {\code {UMODSI3{\_}LIBCALL}}{377}
-\entry {\code {umulhisi3} instruction pattern}{288}
-\entry {\code {umulqihi3} instruction pattern}{288}
-\entry {\code {umulsidi3} instruction pattern}{288}
-\entry {\code {unchanging}}{228}
-\entry {\code {unchanging}, in \code {call{\_}insn}}{226}
-\entry {\code {unchanging}, in \code {insn}}{226}
-\entry {\code {unchanging}, in \code {reg} and \code {mem}}{225}
-\entry {\code {unchanging}, in \code {subreg}}{225}
-\entry {\code {unchanging}, in \code {symbol{\_}ref}}{226}
-\entry {undefined behavior}{193}
-\entry {undefined function value}{193}
-\entry {underscores in variables in macros}{126}
-\entry {underscores, avoiding (88k)}{64}
-\entry {union, casting to a}{137}
-\entry {unions}{182}
-\entry {unions, returning}{213}
-\entry {\code {UNITS{\_}PER{\_}WORD}}{333}
-\entry {\code {UNKNOWN{\_}FLOAT{\_}FORMAT}}{337}
-\entry {unreachable code}{216}
-\entry {unresolved references and \code {-nostdlib}}{52}
-\entry {\code {unshare{\_}all{\_}rtl}}{261}
-\entry {unsigned division}{239}
-\entry {unsigned greater than}{242}
-\entry {unsigned less than}{242}
-\entry {unsigned minimum and maximum}{240}
-\entry {\code {unsigned{\_}fix}}{244}
-\entry {\code {unsigned{\_}float}}{244}
-\entry {\code {unspec}}{249}
-\entry {\code {unspec{\_}volatile}}{249}
-\entry {\code {untyped{\_}call} instruction pattern}{292}
-\entry {\code {untyped{\_}return} instruction pattern}{293}
-\entry {\code {use}}{247}
-\entry {\code {USE{\_}C{\_}ALLOCA}}{426}
-\entry {\code {USE{\_}PROTOTYPES}}{427}
-\entry {\code {used}}{227}
-\entry {\code {used}, in \code {symbol{\_}ref}}{226}
-\entry {\code {USER{\_}LABEL{\_}PREFIX}}{405}
-\entry {\code {USG}}{425}
+\entry {\code {udiv}}{233}
+\entry {\code {UDIVDI3{\_}LIBCALL}}{371}
+\entry {\code {udiv\var {m}3} instruction pattern}{282}
+\entry {\code {udivmod\var {m}4} instruction pattern}{282}
+\entry {\code {UDIVSI3{\_}LIBCALL}}{370}
+\entry {Ultrix calling convention}{172}
+\entry {\code {umax}}{234}
+\entry {\code {umax\var {m}3} instruction pattern}{282}
+\entry {\code {umin}}{234}
+\entry {\code {umin\var {m}3} instruction pattern}{282}
+\entry {\code {umod}}{233}
+\entry {\code {UMODDI3{\_}LIBCALL}}{371}
+\entry {\code {umod\var {m}3} instruction pattern}{282}
+\entry {\code {UMODSI3{\_}LIBCALL}}{370}
+\entry {\code {umulhisi3} instruction pattern}{282}
+\entry {\code {umulqihi3} instruction pattern}{282}
+\entry {\code {umulsidi3} instruction pattern}{282}
+\entry {\code {unchanging}}{222}
+\entry {\code {unchanging}, in \code {call{\_}insn}}{220}
+\entry {\code {unchanging}, in \code {insn}}{220}
+\entry {\code {unchanging}, in \code {reg} and \code {mem}}{219}
+\entry {\code {unchanging}, in \code {subreg}}{219}
+\entry {\code {unchanging}, in \code {symbol{\_}ref}}{220}
+\entry {undefined behavior}{187}
+\entry {undefined function value}{187}
+\entry {underscores in variables in macros}{122}
+\entry {underscores, avoiding (88k)}{61}
+\entry {union, casting to a}{133}
+\entry {unions}{176}
+\entry {unions, returning}{207}
+\entry {\code {UNITS{\_}PER{\_}WORD}}{327}
+\entry {\code {UNKNOWN{\_}FLOAT{\_}FORMAT}}{331}
+\entry {unreachable code}{210}
+\entry {unresolved references and \code {-nostdlib}}{49}
+\entry {\code {unshare{\_}all{\_}rtl}}{255}
+\entry {unsigned division}{233}
+\entry {unsigned greater than}{236}
+\entry {unsigned less than}{236}
+\entry {unsigned minimum and maximum}{234}
+\entry {\code {unsigned{\_}fix}}{238}
+\entry {\code {unsigned{\_}float}}{238}
+\entry {\code {unspec}}{243}
+\entry {\code {unspec{\_}volatile}}{243}
+\entry {\code {untyped{\_}call} instruction pattern}{286}
+\entry {\code {untyped{\_}return} instruction pattern}{287}
+\entry {\code {use}}{241}
+\entry {\code {USE{\_}C{\_}ALLOCA}}{418}
+\entry {\code {USE{\_}PROTOTYPES}}{419}
+\entry {\code {used}}{221}
+\entry {\code {used}, in \code {symbol{\_}ref}}{220}
+\entry {\code {USER{\_}LABEL{\_}PREFIX}}{399}
+\entry {\code {USG}}{417}
 \initial {V}
-\entry {\samp {V} in constraint}{273}
-\entry {\code {VALID{\_}MACHINE{\_}ATTRIBUTE}}{422}
-\entry {value after \code {longjmp}}{154}
-\entry {values, returned by functions}{363}
-\entry {varargs implementation}{371}
-\entry {\file {varargs.h} and RT PC}{70}
-\entry {variable alignment}{143}
-\entry {variable attributes}{143}
-\entry {variable number of arguments}{132}
-\entry {variable-length array scope}{131}
-\entry {variable-length arrays}{131}
-\entry {variables in specified registers}{152}
-\entry {variables, local, in macros}{126}
-\entry {Vax calling convention}{178}
-\entry {VAX options}{57}
-\entry {\code {VAX{\_}FLOAT{\_}FORMAT}}{337}
-\entry {\file {VAXCRTL}}{209}
-\entry {\code {VIRTUAL{\_}INCOMING{\_}ARGS{\_}REGNUM}}{235}
-\entry {\code {VIRTUAL{\_}OUTGOING{\_}ARGS{\_}REGNUM}}{235}
-\entry {\code {VIRTUAL{\_}STACK{\_}DYNAMIC{\_}REGNUM}}{235}
-\entry {\code {VIRTUAL{\_}STACK{\_}VARS{\_}REGNUM}}{235}
-\entry {\code {VMS}}{425}
-\entry {VMS and case sensitivity}{209}
-\entry {VMS and include files}{205}
-\entry {VMS installation}{113}
-\entry {void pointers, arithmetic}{133}
-\entry {void, size of pointer to}{133}
-\entry {\code {VOIDmode}}{229}
-\entry {\code {volatil}}{227}
-\entry {\code {volatil}, in \code {insn}}{226}
-\entry {\code {volatil}, in \code {mem}}{225}
-\entry {\code {volatil}, in \code {reg}}{225}
-\entry {\code {volatil}, in \code {symbol{\_}ref}}{226}
-\entry {\code {volatile} applied to function}{138}
-\entry {volatile memory references}{227}
-\entry {voting between constraint alternatives}{278}
-\entry {\code {vprintf}}{426}
+\entry {\samp {V} in constraint}{267}
+\entry {\code {VALID{\_}MACHINE{\_}ATTRIBUTE}}{415}
+\entry {value after \code {longjmp}}{149}
+\entry {values, returned by functions}{357}
+\entry {varargs implementation}{365}
+\entry {\file {varargs.h} and RT PC}{66}
+\entry {variable alignment}{139}
+\entry {variable attributes}{139}
+\entry {variable number of arguments}{128}
+\entry {variable-length array scope}{127}
+\entry {variable-length arrays}{127}
+\entry {variables in specified registers}{148}
+\entry {variables, local, in macros}{122}
+\entry {Vax calling convention}{172}
+\entry {VAX options}{54}
+\entry {\code {VAX{\_}FLOAT{\_}FORMAT}}{331}
+\entry {\file {VAXCRTL}}{203}
+\entry {\code {VIRTUAL{\_}INCOMING{\_}ARGS{\_}REGNUM}}{229}
+\entry {\code {VIRTUAL{\_}OUTGOING{\_}ARGS{\_}REGNUM}}{229}
+\entry {\code {VIRTUAL{\_}STACK{\_}DYNAMIC{\_}REGNUM}}{229}
+\entry {\code {VIRTUAL{\_}STACK{\_}VARS{\_}REGNUM}}{229}
+\entry {\code {VMS}}{417}
+\entry {VMS and case sensitivity}{203}
+\entry {VMS and include files}{199}
+\entry {VMS installation}{108}
+\entry {void pointers, arithmetic}{129}
+\entry {void, size of pointer to}{129}
+\entry {\code {VOIDmode}}{223}
+\entry {\code {volatil}}{221}
+\entry {\code {volatil}, in \code {insn}}{220}
+\entry {\code {volatil}, in \code {mem}}{219}
+\entry {\code {volatil}, in \code {reg}}{219}
+\entry {\code {volatil}, in \code {symbol{\_}ref}}{220}
+\entry {\code {volatile} applied to function}{134}
+\entry {volatile memory references}{221}
+\entry {voting between constraint alternatives}{272}
+\entry {\code {vprintf}}{418}
 \initial {W}
-\entry {warning for enumeration conversions}{38}
-\entry {warning for overloaded virtual fn}{40}
-\entry {warning for reordering of member initializers}{38}
-\entry {warning for synthesized methods}{40}
-\entry {warning messages}{34}
-\entry {warnings vs errors}{191}
-\entry {\code {WCHAR{\_}TYPE}}{339}
-\entry {\code {WCHAR{\_}TYPE{\_}SIZE}}{339}
-\entry {\code {which{\_}alternative}}{272}
-\entry {whitespace}{182}
-\entry {\code {word{\_}mode}}{232}
-\entry {\code {WORD{\_}REGISTER{\_}OPERATIONS}}{418}
-\entry {\code {WORD{\_}SWITCH{\_}TAKES{\_}ARG}}{325}
-\entry {\code {WORDS{\_}BIG{\_}ENDIAN}}{332}
-\entry {\code {WORDS{\_}BIG{\_}ENDIAN}, effect on \code {subreg}}{236}
+\entry {warning for enumeration conversions}{35}
+\entry {warning for overloaded virtual fn}{37}
+\entry {warning messages}{32}
+\entry {warnings vs errors}{186}
+\entry {\code {WCHAR{\_}TYPE}}{333}
+\entry {\code {WCHAR{\_}TYPE{\_}SIZE}}{333}
+\entry {\code {which{\_}alternative}}{266}
+\entry {whitespace}{176}
+\entry {\code {word{\_}mode}}{226}
+\entry {\code {WORD{\_}REGISTER{\_}OPERATIONS}}{411}
+\entry {\code {WORD{\_}SWITCH{\_}TAKES{\_}ARG}}{319}
+\entry {\code {WORDS{\_}BIG{\_}ENDIAN}}{326}
+\entry {\code {WORDS{\_}BIG{\_}ENDIAN}, effect on \code {subreg}}{230}
 \initial {X}
-\entry {\samp {X} in constraint}{274}
-\entry {\code {XCmode}}{229}
-\entry {\code {XCOFF{\_}DEBUGGING{\_}INFO}}{409}
-\entry {\code {XEXP}}{223}
-\entry {\code {XFmode}}{229}
-\entry {\code {XINT}}{223}
-\entry {\file {xm-\var {machine}.h}}{425}
-\entry {\code {xor}}{240}
-\entry {\code {xor}, canonicalization of}{301}
-\entry {\code {xor\var {m}3} instruction pattern}{288}
-\entry {\code {XSTR}}{223}
-\entry {\code {XVEC}}{224}
-\entry {\code {XVECEXP}}{224}
-\entry {\code {XVECLEN}}{224}
-\entry {\code {XWINT}}{223}
+\entry {\samp {X} in constraint}{268}
+\entry {\code {XCmode}}{223}
+\entry {\code {XCOFF{\_}DEBUGGING{\_}INFO}}{403}
+\entry {\code {XEXP}}{217}
+\entry {\code {XFmode}}{223}
+\entry {\code {XINT}}{217}
+\entry {\file {xm-\var {machine}.h}}{417}
+\entry {\code {xor}}{234}
+\entry {\code {xor}, canonicalization of}{295}
+\entry {\code {xor\var {m}3} instruction pattern}{282}
+\entry {\code {XSTR}}{217}
+\entry {\code {XVEC}}{218}
+\entry {\code {XVECEXP}}{218}
+\entry {\code {XVECLEN}}{218}
+\entry {\code {XWINT}}{217}
 \initial {Z}
-\entry {zero division on 88k}{66}
-\entry {zero-length arrays}{130}
-\entry {\code {zero{\_}extend}}{244}
-\entry {\code {zero{\_}extend\var {mn}} instruction pattern}{290}
-\entry {\code {zero{\_}extract}}{243}
-\entry {\code {zero{\_}extract}, canonicalization of}{301}
+\entry {zero division on 88k}{62}
+\entry {zero-length arrays}{126}
+\entry {\code {zero{\_}extend}}{238}
+\entry {\code {zero{\_}extend\var {mn}} instruction pattern}{284}
+\entry {\code {zero{\_}extract}}{237}
+\entry {\code {zero{\_}extract}, canonicalization of}{295}
diff -r -u -H -N gcc-2.6.3/gcc.info gcc-i2.6.3/gcc.info
--- gcc-2.6.3/gcc.info	Wed Nov 23 17:54:18 1994
+++ gcc-i2.6.3/gcc.info	Thu Feb 16 15:08:40 1995
@@ -37,24 +37,24 @@
 gcc.info-4: 141516
 gcc.info-5: 189933
 gcc.info-6: 221957
-gcc.info-7: 269574
-gcc.info-8: 319268
-gcc.info-9: 368568
-gcc.info-10: 417318
-gcc.info-11: 458309
-gcc.info-12: 495659
-gcc.info-13: 545024
-gcc.info-14: 588340
-gcc.info-15: 637892
-gcc.info-16: 670616
-gcc.info-17: 718011
-gcc.info-18: 763563
-gcc.info-19: 813295
-gcc.info-20: 862496
-gcc.info-21: 912088
-gcc.info-22: 956435
-gcc.info-23: 999520
-gcc.info-24: 1022946
+gcc.info-7: 269579
+gcc.info-8: 319273
+gcc.info-9: 368573
+gcc.info-10: 417323
+gcc.info-11: 458314
+gcc.info-12: 495664
+gcc.info-13: 545029
+gcc.info-14: 588345
+gcc.info-15: 637897
+gcc.info-16: 670621
+gcc.info-17: 718016
+gcc.info-18: 763568
+gcc.info-19: 813300
+gcc.info-20: 862501
+gcc.info-21: 912093
+gcc.info-22: 956440
+gcc.info-23: 999525
+gcc.info-24: 1022951
 
 Tag Table:
 (Indirect)
@@ -101,190 +101,190 @@
 Node: Running Protoize194233
 Node: Installation200462
 Node: Configurations221957
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-Node: Uninitialized Data945316
-Node: Label Output948023
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-Node: DBX Hooks986031
-Node: File Names and DBX989370
-Node: SDB and DWARF991343
-Node: Cross-compilation993073
-Node: Misc999520
-Node: Config1016085
-Node: Index1022946
+Node: Other Dir253058
+Node: Cross-Compiler254774
+Node: Steps of Cross256605
+Node: Configure Cross257723
+Node: Tools and Libraries258360
+Node: Cross Runtime260803
+Node: Cross Headers264557
+Node: Build Cross266542
+Node: Sun Install268447
+Node: VMS Install269579
+Node: Collect2279508
+Node: Header Dirs282217
+Node: C Extensions283631
+Node: Statement Exprs286805
+Node: Local Labels288699
+Node: Labels as Values290761
+Node: Nested Functions292626
+Node: Constructing Calls296482
+Node: Naming Types298539
+Node: Typeof299633
+Node: Lvalues301498
+Node: Conditionals303938
+Node: Long Long304829
+Node: Complex306273
+Node: Zero Length308135
+Node: Variable Length308809
+Node: Macro Varargs311334
+Node: Subscripting313437
+Node: Pointer Arith313920
+Node: Initializers314485
+Node: Constructors314950
+Node: Labeled Elements316644
+Node: Case Ranges319273
+Node: Cast to Union319954
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+Node: Function Prototypes327909
+Node: Dollar Signs329708
+Node: Character Escapes330495
+Node: Alignment330776
+Node: Variable Attributes332252
+Node: Inline337971
+Node: Extended Asm341848
+Node: Asm Labels352135
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+Node: Local Reg Vars359267
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+Node: Incomplete Enums362261
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+Node: Min and Max368573
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+Node: C++ Interface370573
+Node: Template Instantiation375796
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+Node: Actual Bugs387417
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+Node: Interoperation403943
+Node: External Bugs417323
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+Node: Fixed Headers428003
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+Node: Static Definitions435209
+Node: Temporaries436263
+Node: Protoize Caveats438467
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+Node: Warnings and Errors451382
+Node: Bugs453153
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+Node: Bug Lists456943
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+Node: Service475789
+Node: VMS476350
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+Node: Passes495664
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+Node: Regs and Memory545029
+Node: Arithmetic556739
+Node: Comparisons562637
+Node: Bit Fields566699
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+Node: RTL Declarations570951
+Node: Side Effects571760
+Node: Incdec584307
+Node: Assembler586823
+Node: Insns588345
+Node: Calls609198
+Node: Sharing611793
+Node: Reading RTL614869
+Node: Machine Desc615813
+Node: Patterns617666
+Node: Example620610
+Node: RTL Template621738
+Node: Output Template633936
+Node: Output Statement637897
+Node: Constraints641610
+Node: Simple Constraints642613
+Node: Multi-Alternative654046
+Node: Class Preferences656882
+Node: Modifiers657762
+Node: Machine Constraints660922
+Node: No Constraints669500
+Node: Standard Names670621
+Node: Pattern Ordering697620
+Node: Dependent Patterns698846
+Node: Jump Patterns701786
+Node: Insn Canonicalizations707602
+Node: Peephole Definitions711097
+Node: Expander Definitions718016
+Node: Insn Splitting725156
+Node: Insn Attributes732170
+Node: Defining Attributes733217
+Node: Expressions735229
+Node: Tagging Insns741541
+Node: Attr Example745904
+Node: Insn Lengths748280
+Node: Constant Attributes751644
+Node: Delay Slots752804
+Node: Function Units756015
+Node: Target Macros761685
+Node: Driver763568
+Node: Run-time Target773875
+Node: Storage Layout779882
+Node: Type Layout792849
+Node: Registers799178
+Node: Register Basics800158
+Node: Allocation Order804195
+Node: Values in Registers805613
+Node: Leaf Functions809992
+Node: Stack Registers812467
+Node: Obsolete Register Macros813300
+Node: Register Classes815995
+Node: Stack and Calling835567
+Node: Frame Layout836003
+Node: Frame Registers839444
+Node: Elimination843254
+Node: Stack Arguments847510
+Node: Register Arguments853826
+Node: Scalar Return862501
+Node: Aggregate Return866464
+Node: Caller Saves870179
+Node: Function Entry871329
+Node: Profiling880257
+Node: Varargs883161
+Node: Trampolines889985
+Node: Library Calls896447
+Node: Addressing Modes904505
+Node: Condition Code912093
+Node: Costs918292
+Node: Sections926671
+Node: PIC931460
+Node: Assembler Format934219
+Node: File Framework935224
+Node: Data Output939397
+Node: Uninitialized Data945321
+Node: Label Output948028
+Node: Initialization956440
+Node: Macros for Initialization962583
+Node: Instruction Output966016
+Node: Dispatch Tables974011
+Node: Alignment Output976388
+Node: Debugging Info978128
+Node: All Debuggers978737
+Node: DBX Options981151
+Node: DBX Hooks986036
+Node: File Names and DBX989375
+Node: SDB and DWARF991348
+Node: Cross-compilation993078
+Node: Misc999525
+Node: Config1016090
+Node: Index1022951
 
 End Tag Table
diff -r -u -H -N gcc-2.6.3/gcc.info-24 gcc-i2.6.3/gcc.info-24
--- gcc-2.6.3/gcc.info-24	Wed Nov 23 17:54:18 1994
+++ gcc-i2.6.3/gcc.info-24	Thu Feb 16 15:08:40 1995
@@ -50,8 +50,8 @@
 * * in template:                        Output Statement.
 * -lgcc, use with -nostdlib:            Link Options.
 * -nostdlib and unresolved references:  Link Options.
-* ?: extensions:                        Lvalues.
 * ?: extensions:                        Conditionals.
+* ?: extensions:                        Lvalues.
 * absM2 instruction pattern:            Standard Names.
 * abs and attributes:                   Expressions.
 * ACCUMULATE_OUTGOING_ARGS and stack frames: Function Entry.
@@ -316,8 +316,8 @@
 * d in constraint:                      Simple Constraints.
 * E in constraint:                      Simple Constraints.
 * F in constraint:                      Simple Constraints.
-* G in constraint:                      Simple Constraints.
 * g in constraint:                      Simple Constraints.
+* G in constraint:                      Simple Constraints.
 * H in constraint:                      Simple Constraints.
 * I in constraint:                      Simple Constraints.
 * i in constraint:                      Simple Constraints.
@@ -332,10 +332,10 @@
 * V in constraint:                      Simple Constraints.
 * X in constraint:                      Simple Constraints.
 * _ in variables in macros:             Naming Types.
-* abort:                                C Dialect Options.
 * abort:                                Portability.
-* abs:                                  C Dialect Options.
+* abort:                                C Dialect Options.
 * abs:                                  Arithmetic.
+* abs:                                  C Dialect Options.
 * absolute value:                       Arithmetic.
 * access to operands:                   Accessors.
 * accessors:                            Accessors.
@@ -507,8 +507,8 @@
 * C language extensions:                C Extensions.
 * C language, traditional:              C Dialect Options.
 * C statements for assembler output:    Output Statement.
-* C++:                                  G++ and GCC.
 * c++:                                  Invoking G++.
+* C++:                                  G++ and GCC.
 * C++ compilation options:              Invoking GCC.
 * C++ interface and implementation headers: C++ Interface.
 * C++ language extensions:              C++ Extensions.
@@ -603,8 +603,8 @@
 * conflicting types:                    Disappointments.
 * CONST0_RTX:                           Constants.
 * const0_rtx:                           Constants.
-* const1_rtx:                           Constants.
 * CONST1_RTX:                           Constants.
+* const1_rtx:                           Constants.
 * CONST2_RTX:                           Constants.
 * const2_rtx:                           Constants.
 * constant attributes:                  Constant Attributes.
@@ -822,8 +822,8 @@
 * FAILURE_EXIT_CODE:                    Config.
 * fatal signal:                         Bug Criteria.
 * features, optional, in system conventions: Run-time Target.
-* ffs:                                  C Dialect Options.
 * ffs:                                  Arithmetic.
+* ffs:                                  C Dialect Options.
 * file name suffix:                     Overall Options.
 * file names:                           Link Options.
 * files and passes of the compiler:     Passes.
@@ -895,8 +895,8 @@
 * FUNCTION_PROLOGUE:                    Function Entry.
 * FUNCTION_VALUE:                       Scalar Return.
 * FUNCTION_VALUE_REGNO_P:               Scalar Return.
-* G++:                                  G++ and GCC.
 * g++:                                  Invoking G++.
+* G++:                                  G++ and GCC.
 * GCC:                                  G++ and GCC.
 * GCC_EXEC_PREFIX:                      Environment Variables.
 * ge:                                   Comparisons.
@@ -1005,8 +1005,8 @@
 * INITIAL_FRAME_POINTER_OFFSET:         Elimination.
 * INIT_CUMULATIVE_ARGS:                 Register Arguments.
 * INIT_CUMULATIVE_INCOMING_ARGS:        Register Arguments.
-* INIT_SECTION_ASM_OP:                  Sections.
 * INIT_SECTION_ASM_OP:                  Macros for Initialization.
+* INIT_SECTION_ASM_OP:                  Sections.
 * INIT_TARGET_OPTABS:                   Library Calls.
 * inline functions:                     Inline.
 * inline functions, omission of:        Inline.
@@ -1652,8 +1652,8 @@
 * specifying registers for local variables: Local Reg Vars.
 * speed of instructions:                Costs.
 * splitting instructions:               Insn Splitting.
-* sqrt:                                 C Dialect Options.
 * sqrt:                                 Arithmetic.
+* sqrt:                                 C Dialect Options.
 * square root:                          Arithmetic.
 * stack arguments:                      Stack Arguments.
 * stack checks (29k):                   AMD29K Options.
diff -r -u -H -N gcc-2.6.3/gcc.info-6 gcc-i2.6.3/gcc.info-6
--- gcc-2.6.3/gcc.info-6	Wed Nov 23 17:54:08 1994
+++ gcc-i2.6.3/gcc.info-6	Thu Feb 16 15:08:30 1995
@@ -669,8 +669,10 @@
      to AIX 3.2.4 include a version of the IBM assembler which does not
      accept debugging directives: assembler updates are available as
      PTFs.  See the file `README.RS6000' for more details on both of
-     these problems.  Only AIX is supported on the PowerPC.  GNU CC
-     does not yet support the 64-bit PowerPC instructions.
+     these problems.
+
+     Only AIX is supported on the PowerPC.  GNU CC does not yet support
+     the 64-bit PowerPC instructions.
 
      Objective C does not work on this architecture.
 
diff -r -u -H -N gcc-2.6.3/gcci.results gcc-i2.6.3/gcci.results
--- gcc-2.6.3/gcci.results	Wed Dec 31 19:00:00 1969
+++ gcc-i2.6.3/gcci.results	Wed Feb 15 22:47:32 1995
@@ -0,0 +1,526 @@
+Hmm...  Looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/Makefile.in gcc-i2.5.8/Makefile.in
+|*** gcc-2.5.8/Makefile.in	Thu Dec 23 16:13:50 1993
+|--- gcc-i2.5.8/Makefile.in	Mon Jun 20 08:28:31 1994
+--------------------------
+Patching file Makefile.in using Plan A...
+Reversed (or previously applied) patch detected!  Assume -R? [y] n
+Apply anyway? [n] 
+Hunk #1 ignored at 1123.
+1 out of 1 hunks ignored--saving rejects to Makefile.in.rej
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/c-decl.c gcc-i2.5.8/c-decl.c
+|*** gcc-2.5.8/c-decl.c	Mon Nov 22 23:20:10 1993
+|--- gcc-i2.5.8/c-decl.c	Mon Jun 20 08:22:29 1994
+--------------------------
+Patching file c-decl.c using Plan A...
+Hunk #1 succeeded at 2119 (offset 68 lines).
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/combine.c gcc-i2.5.8/combine.c
+|*** gcc-2.5.8/combine.c	Fri Dec 31 04:28:52 1993
+|--- gcc-i2.5.8/combine.c	Mon Jun 20 09:00:03 1994
+--------------------------
+Patching file combine.c using Plan A...
+Hunk #1 succeeded at 93 (offset 4 lines).
+Hunk #2 succeeded at 374 (offset 13 lines).
+Hunk #3 failed at 447.
+Hunk #4 succeeded at 886 (offset 13 lines).
+Hunk #5 failed at 1058.
+Hunk #6 failed at 1128.
+Hunk #7 succeeded at 1408 (offset 26 lines).
+Hunk #8 failed at 2050.
+Hunk #9 failed at 4257.
+Hunk #10 succeeded at 9824 (offset 291 lines).
+Hunk #11 failed at 10553.
+Hunk #12 succeeded at 10683 (offset 152 lines).
+6 out of 12 hunks failed--saving rejects to combine.c.rej
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/config/i386/i386.c gcc-i2.5.8/config/i386/i386.c
+|*** gcc-2.5.8/config/i386/i386.c	Sat Oct 30 16:07:33 1993
+|--- gcc-i2.5.8/config/i386/i386.c	Mon Jun 20 10:53:39 1994
+--------------------------
+Patching file config/i386/i386.c using Plan A...
+Hunk #1 failed at 1.
+Hunk #2 succeeded at 33.
+Hunk #3 succeeded at 2270 (offset 761 lines).
+Hunk #4 succeeded at 1900 (offset -25 lines).
+Hunk #5 succeeded at 2762 (offset 761 lines).
+Hunk #6 succeeded at 2153 (offset -25 lines).
+1 out of 6 hunks failed--saving rejects to config/i386/i386.c.rej
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/config/i386/i386.h gcc-i2.5.8/config/i386/i386.h
+|*** gcc-2.5.8/config/i386/i386.h	Wed Oct 13 00:02:45 1993
+|--- gcc-i2.5.8/config/i386/i386.h	Mon Jun 20 10:15:31 1994
+--------------------------
+Patching file config/i386/i386.h using Plan A...
+Hunk #1 failed at 1.
+Hunk #2 failed at 54.
+Hunk #3 failed at 138.
+Hunk #4 succeeded at 317 (offset 59 lines).
+Hunk #5 succeeded at 345 (offset 59 lines).
+Hunk #6 succeeded at 404 (offset 38 lines).
+Hunk #7 failed at 612.
+Hunk #8 failed at 687.
+Hunk #9 failed at 1269.
+Hunk #10 succeeded at 1474 (offset 139 lines).
+Hunk #11 succeeded at 1504 (offset 37 lines).
+6 out of 11 hunks failed--saving rejects to config/i386/i386.h.rej
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/config/i386/i386.md gcc-i2.5.8/config/i386/i386.md
+|*** gcc-2.5.8/config/i386/i386.md	Mon Oct  4 23:43:48 1993
+|--- gcc-i2.5.8/config/i386/i386.md	Mon Jun 20 10:56:24 1994
+--------------------------
+Patching file config/i386/i386.md using Plan A...
+Hunk #1 failed at 1.
+Hunk #2 succeeded at 70.
+Hunk #3 failed at 172.
+Hunk #4 failed at 372.
+Hunk #5 failed at 434.
+Hunk #6 failed at 481.
+Hunk #7 failed at 520.
+Hunk #8 failed at 561.
+Hunk #9 failed at 1029.
+Hunk #10 failed at 1092.
+Hunk #11 failed at 1140.
+Hunk #12 failed at 1203.
+Hunk #13 failed at 1333.
+Hunk #14 failed at 1376.
+Hunk #15 failed at 1420.
+Hunk #16 succeeded at 2147 (offset 360 lines).
+Hunk #17 succeeded at 2212 (offset 360 lines).
+Hunk #18 failed at 2268.
+Hunk #19 succeeded at 2300 with fuzz 1 (offset 360 lines).
+Hunk #20 failed at 2342.
+Hunk #21 succeeded at 2398 (offset 360 lines).
+Hunk #22 succeeded at 2480 (offset 360 lines).
+Hunk #23 failed at 2540.
+Hunk #24 failed at 2602.
+Hunk #25 succeeded at 2385 (offset 50 lines).
+Hunk #26 succeeded at 2808 (offset 403 lines).
+Hunk #27 succeeded at 2577 with fuzz 1 (offset 87 lines).
+Hunk #28 succeeded at 2932 (offset 403 lines).
+Hunk #29 failed at 3038.
+Hunk #30 failed at 3084.
+Hunk #31 succeeded at 2897 (offset 87 lines).
+Hunk #32 succeeded at 3259 (offset 403 lines).
+Hunk #33 succeeded at 2994 (offset 87 lines).
+Hunk #34 succeeded at 3368 (offset 403 lines).
+Hunk #35 succeeded at 3103 (offset 87 lines).
+Hunk #36 failed at 3182.
+Hunk #37 failed at 3450.
+Hunk #38 failed at 3951.
+Hunk #39 failed at 3969.
+Hunk #40 succeeded at 4655 (offset 415 lines).
+Hunk #41 succeeded at 4368 (offset 87 lines).
+Hunk #42 succeeded at 4730 (offset 415 lines).
+Hunk #43 succeeded at 4453 (offset 87 lines).
+Hunk #44 succeeded at 4832 (offset 415 lines).
+Hunk #45 succeeded at 4555 (offset 87 lines).
+Hunk #46 succeeded at 4928 (offset 415 lines).
+Hunk #47 succeeded at 4623 (offset 87 lines).
+Hunk #48 succeeded at 4973 (offset 415 lines).
+Hunk #49 succeeded at 4676 (offset 87 lines).
+Hunk #50 succeeded at 5036 (offset 415 lines).
+Hunk #51 succeeded at 4740 (offset 87 lines).
+Hunk #52 succeeded at 5506 (offset 331 lines).
+Hunk #53 succeeded at 5338 (offset 87 lines).
+Hunk #54 succeeded at 5619 (offset 331 lines).
+Hunk #55 succeeded at 5427 (offset 87 lines).
+Hunk #56 succeeded at 5717 (offset 331 lines).
+Hunk #57 failed at 5744.
+Hunk #58 failed at 5808.
+Hunk #59 succeeded at 5721 (offset 87 lines).
+26 out of 59 hunks failed--saving rejects to config/i386/i386.md.rej
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/config/i386/osfrose.h gcc-i2.5.8/config/i386/osfrose.h
+|*** gcc-2.5.8/config/i386/osfrose.h	Wed Oct 20 20:42:59 1993
+|--- gcc-i2.5.8/config/i386/osfrose.h	Mon Jun 20 06:05:37 1994
+--------------------------
+Patching file config/i386/osfrose.h using Plan A...
+Hunk #1 succeeded at 465 (offset -105 lines).
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/config.sub gcc-i2.5.8/config.sub
+|*** gcc-2.5.8/config.sub	Thu Jan 13 03:43:41 1994
+|--- gcc-i2.5.8/config.sub	Mon Jun 20 08:28:42 1994
+--------------------------
+Patching file config.sub using Plan A...
+Hunk #1 failed at 104.
+Hunk #2 failed at 146.
+Hunk #3 failed at 677.
+3 out of 3 hunks failed--saving rejects to config.sub.rej
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/configure gcc-i2.5.8/configure
+|*** gcc-2.5.8/configure	Fri Nov 19 14:44:34 1993
+|--- gcc-i2.5.8/configure	Mon Jun 20 08:22:53 1994
+--------------------------
+Patching file configure using Plan A...
+Hunk #1 failed at 349.
+Hunk #2 failed at 411.
+Hunk #3 failed at 427.
+Hunk #4 failed at 457.
+Hunk #5 failed at 477.
+Hunk #6 failed at 513.
+Hunk #7 failed at 532.
+Hunk #8 failed at 1598.
+8 out of 8 hunks failed--saving rejects to configure.rej
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/cse.c gcc-i2.5.8/cse.c
+|*** gcc-2.5.8/cse.c	Fri Dec 24 19:55:44 1993
+|--- gcc-i2.5.8/cse.c	Mon Jun 20 08:28:44 1994
+--------------------------
+Patching file cse.c using Plan A...
+Hunk #1 succeeded at 6004 (offset 192 lines).
+Hunk #2 succeeded at 6453 (offset 46 lines).
+Hunk #3 succeeded at 7068 with fuzz 1 (offset 200 lines).
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/expr.c gcc-i2.5.8/expr.c
+|*** gcc-2.5.8/expr.c	Mon Jan 10 17:26:14 1994
+|--- gcc-i2.5.8/expr.c	Mon Jun 20 08:28:45 1994
+--------------------------
+Patching file expr.c using Plan A...
+Hunk #1 failed at 20.
+Hunk #2 failed at 8299.
+Hunk #3 succeeded at 8756 (offset 396 lines).
+2 out of 3 hunks failed--saving rejects to expr.c.rej
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/flags.h gcc-i2.5.8/flags.h
+|*** gcc-2.5.8/flags.h	Thu Sep 16 00:08:16 1993
+|--- gcc-i2.5.8/flags.h	Mon Jun 20 06:08:08 1994
+--------------------------
+Patching file flags.h using Plan A...
+Hunk #1 succeeded at 354 (offset 11 lines).
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/flow.c gcc-i2.5.8/flow.c
+|*** gcc-2.5.8/flow.c	Wed Dec  8 04:16:59 1993
+|--- gcc-i2.5.8/flow.c	Mon Jun 20 08:27:45 1994
+--------------------------
+Patching file flow.c using Plan A...
+Hunk #1 failed at 283.
+Hunk #2 succeeded at 388 (offset 5 lines).
+Hunk #3 succeeded at 425 (offset 5 lines).
+Hunk #4 succeeded at 650 (offset 30 lines).
+Hunk #5 succeeded at 788 (offset 37 lines).
+Hunk #6 succeeded at 812 (offset 30 lines).
+Hunk #7 succeeded at 871 (offset 44 lines).
+Hunk #8 succeeded at 943 (offset 30 lines).
+Hunk #9 succeeded at 1100 with fuzz 2 (offset 44 lines).
+Hunk #10 succeeded at 1151 (offset 30 lines).
+Hunk #11 succeeded at 1262 (offset 49 lines).
+Hunk #12 succeeded at 1280 (offset 30 lines).
+Hunk #13 succeeded at 1349 (offset 49 lines).
+Hunk #14 succeeded at 1413 (offset 30 lines).
+Hunk #15 succeeded at 1474 (offset 49 lines).
+Hunk #16 succeeded at 1499 (offset 30 lines).
+Hunk #17 succeeded at 1582 (offset 58 lines).
+Hunk #18 succeeded at 1572 (offset 30 lines).
+Hunk #19 succeeded at 2806 (offset 107 lines).
+Hunk #20 succeeded at 2810 (offset 30 lines).
+1 out of 20 hunks failed--saving rejects to flow.c.rej
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/fold-const.c gcc-i2.5.8/fold-const.c
+|*** gcc-2.5.8/fold-const.c	Wed Dec  8 03:45:24 1993
+|--- gcc-i2.5.8/fold-const.c	Mon Jun 20 08:27:45 1994
+--------------------------
+Patching file fold-const.c using Plan A...
+Hunk #1 succeeded at 3544 (offset -42 lines).
+Hunk #2 failed at 3873.
+1 out of 2 hunks failed--saving rejects to fold-const.c.rej
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/jump.c gcc-i2.5.8/jump.c
+|*** gcc-2.5.8/jump.c	Sun Jan  9 03:38:38 1994
+|--- gcc-i2.5.8/jump.c	Mon Jun 20 08:28:47 1994
+--------------------------
+Patching file jump.c using Plan A...
+Hunk #1 succeeded at 1824 (offset 49 lines).
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/loop.c gcc-i2.5.8/loop.c
+|*** gcc-2.5.8/loop.c	Thu Dec  2 06:10:07 1993
+|--- gcc-i2.5.8/loop.c	Mon Jun 20 08:26:52 1994
+--------------------------
+Patching file loop.c using Plan A...
+Hunk #1 succeeded at 35.
+Hunk #2 succeeded at 184.
+Hunk #3 succeeded at 282.
+Hunk #4 succeeded at 399 (offset -4 lines).
+Hunk #5 succeeded at 422 (offset -4 lines).
+Hunk #6 succeeded at 459 (offset -4 lines).
+Hunk #7 succeeded at 511 (offset -4 lines).
+Hunk #8 failed at 605.
+Hunk #9 failed at 719.
+Hunk #10 succeeded at 779 (offset 2 lines).
+Hunk #11 succeeded at 826 (offset -4 lines).
+Hunk #12 failed at 888.
+Hunk #13 succeeded at 1110 (offset 9 lines).
+Hunk #14 succeeded at 1401 (offset -5 lines).
+Hunk #15 succeeded at 1692 (offset 9 lines).
+Hunk #16 failed at 1713.
+Hunk #17 succeeded at 1817 (offset -5 lines).
+Hunk #18 succeeded at 1887 (offset 9 lines).
+Hunk #19 failed at 1931.
+Hunk #20 succeeded at 1953 (offset -3 lines).
+Hunk #21 succeeded at 2073 (offset 17 lines).
+Hunk #22 succeeded at 2114 (offset 5 lines).
+Hunk #23 succeeded at 2160 (offset 17 lines).
+Hunk #24 succeeded at 2218 (offset 5 lines).
+Hunk #25 succeeded at 2281 (offset 17 lines).
+Hunk #26 succeeded at 2578 (offset 5 lines).
+Hunk #27 succeeded at 2606 (offset 17 lines).
+Hunk #28 succeeded at 2618 (offset 5 lines).
+Hunk #29 succeeded at 2676 (offset 17 lines).
+Hunk #30 succeeded at 2724 (offset 5 lines).
+Hunk #31 succeeded at 2761 (offset 17 lines).
+Hunk #32 succeeded at 2791 (offset 5 lines).
+Hunk #33 succeeded at 2926 (offset 16 lines).
+Hunk #34 succeeded at 3144 (offset 8 lines).
+Hunk #35 succeeded at 3380 (offset 16 lines).
+Hunk #36 failed at 3592.
+Hunk #37 failed at 3723.
+Hunk #38 succeeded at 3834 (offset 15 lines).
+Hunk #39 succeeded at 3868 (offset 16 lines).
+Hunk #40 failed at 4025.
+Hunk #41 succeeded at 4094 (offset 21 lines).
+Hunk #42 succeeded at 4152 (offset 16 lines).
+Hunk #43 succeeded at 4506 (offset 21 lines).
+Hunk #44 succeeded at 4560 (offset 16 lines).
+Hunk #45 succeeded at 4659 (offset 21 lines).
+Hunk #46 succeeded at 4687 (offset 16 lines).
+Hunk #47 succeeded at 4824 (offset 21 lines).
+Hunk #48 succeeded at 4904 (offset 16 lines).
+Hunk #49 succeeded at 5220 (offset 20 lines).
+Hunk #50 succeeded at 6040 (offset 20 lines).
+Hunk #51 succeeded at 6851 (offset 31 lines).
+Hunk #52 succeeded at 7203 (offset 23 lines).
+8 out of 52 hunks failed--saving rejects to loop.c.rej
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/loop.h gcc-i2.5.8/loop.h
+|*** gcc-2.5.8/loop.h	Fri Mar 19 19:10:47 1993
+|--- gcc-i2.5.8/loop.h	Sun May 30 10:49:48 1993
+--------------------------
+Patching file loop.h using Plan A...
+Hunk #1 succeeded at 84.
+Hunk #2 succeeded at 129.
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/reg-stack.c gcc-i2.5.8/reg-stack.c
+|*** gcc-2.5.8/reg-stack.c	Mon Oct  4 23:45:12 1993
+|--- gcc-i2.5.8/reg-stack.c	Mon Jun 20 06:08:32 1994
+--------------------------
+Patching file reg-stack.c using Plan A...
+Hunk #1 failed at 226.
+Hunk #2 succeeded at 2024 (offset 87 lines).
+Hunk #3 succeeded at 2918 (offset 2 lines).
+1 out of 3 hunks failed--saving rejects to reg-stack.c.rej
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/reload.c gcc-i2.5.8/reload.c
+|*** gcc-2.5.8/reload.c	Sun Jan 23 18:12:42 1994
+|--- gcc-i2.5.8/reload.c	Mon Jun 20 08:28:48 1994
+--------------------------
+Patching file reload.c using Plan A...
+Hunk #1 succeeded at 4021 (offset 22 lines).
+Hunk #2 succeeded at 4268 (offset -1 lines).
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/reload.h gcc-i2.5.8/reload.h
+|*** gcc-2.5.8/reload.h	Sat May  8 23:08:22 1993
+|--- gcc-i2.5.8/reload.h	Wed Jun  2 09:48:15 1993
+--------------------------
+Patching file reload.h using Plan A...
+Hunk #1 succeeded at 231 (offset -11 lines).
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|Only in gcc-i2.5.8: reload.hnew
+|diff -r -C6 -d gcc-2.5.8/reload1.c gcc-i2.5.8/reload1.c
+|*** gcc-2.5.8/reload1.c	Tue Nov  9 17:28:32 1993
+|--- gcc-i2.5.8/reload1.c	Mon Jun 20 08:19:33 1994
+--------------------------
+Patching file reload1.c using Plan A...
+Hunk #1 succeeded at 72.
+Hunk #2 succeeded at 260.
+Hunk #3 succeeded at 303.
+Hunk #4 succeeded at 376 (offset 2 lines).
+Hunk #5 succeeded at 472 (offset 2 lines).
+Hunk #6 succeeded at 1968 (offset -35 lines).
+Hunk #7 succeeded at 2102 (offset 2 lines).
+Hunk #8 succeeded at 2374 (offset -37 lines).
+Hunk #9 succeeded at 2435 (offset 2 lines).
+Hunk #10 succeeded at 2426 (offset -37 lines).
+Hunk #11 succeeded at 2484 (offset 2 lines).
+Hunk #12 succeeded at 2473 (offset -37 lines).
+Hunk #13 succeeded at 2753 (offset 2 lines).
+Hunk #14 succeeded at 2765 (offset -37 lines).
+Hunk #15 succeeded at 3218 (offset 40 lines).
+Hunk #16 succeeded at 3339 (offset 12 lines).
+Hunk #17 failed at 3799.
+Hunk #18 succeeded at 3891 (offset 73 lines).
+Hunk #19 succeeded at 3984 (offset 12 lines).
+Hunk #20 succeeded at 5754 with fuzz 1 (offset 212 lines).
+Hunk #21 failed at 6153.
+Hunk #22 failed at 6578.
+Hunk #23 succeeded at 6645 with fuzz 1 (offset -27 lines).
+Hunk #24 failed at 6778.
+Hunk #25 succeeded at 7369 (offset 233 lines).
+4 out of 25 hunks failed--saving rejects to reload1.c.rej
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/rtl.c gcc-i2.5.8/rtl.c
+|*** gcc-2.5.8/rtl.c	Thu Oct  7 15:05:00 1993
+|--- gcc-i2.5.8/rtl.c	Mon Jun 20 06:08:36 1994
+--------------------------
+Patching file rtl.c using Plan A...
+Hunk #1 succeeded at 170.
+Hunk #2 succeeded at 299.
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/rtl.def gcc-i2.5.8/rtl.def
+|*** gcc-2.5.8/rtl.def	Wed Jul 14 20:21:42 1993
+|--- gcc-i2.5.8/rtl.def	Mon Jun 20 06:08:36 1994
+--------------------------
+Patching file rtl.def using Plan A...
+Hunk #1 succeeded at 343.
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/rtl.h gcc-i2.5.8/rtl.h
+|*** gcc-2.5.8/rtl.h	Wed Sep 29 16:34:24 1993
+|--- gcc-i2.5.8/rtl.h	Mon Jun 20 06:08:37 1994
+--------------------------
+Patching file rtl.h using Plan A...
+Hunk #1 succeeded at 136 (offset 4 lines).
+Hunk #2 succeeded at 206 (offset 20 lines).
+Hunk #3 succeeded at 242 (offset 4 lines).
+Hunk #4 succeeded at 352 (offset 20 lines).
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/sched.c gcc-i2.5.8/sched.c
+|*** gcc-2.5.8/sched.c	Tue Oct  5 17:20:33 1993
+|--- gcc-i2.5.8/sched.c	Mon Jun 20 09:15:45 1994
+--------------------------
+Patching file sched.c using Plan A...
+Hunk #1 succeeded at 121.
+Hunk #2 failed at 161.
+Hunk #3 succeeded at 321 (offset 2 lines).
+Hunk #4 succeeded at 659 (offset 13 lines).
+Hunk #5 succeeded at 1176 (offset 2 lines).
+Hunk #6 succeeded at 1229 (offset 13 lines).
+Hunk #7 succeeded at 1479 (offset -1 lines).
+Hunk #8 succeeded at 1995 with fuzz 1 (offset 7 lines).
+Hunk #9 succeeded at 2121 (offset 7 lines).
+Hunk #10 succeeded at 2206 (offset 7 lines).
+Hunk #11 failed at 2382.
+Hunk #12 failed at 2453.
+Hunk #13 succeeded at 2896 (offset 120 lines).
+Hunk #14 failed at 3509.
+Hunk #15 succeeded at 3550 (offset 36 lines).
+Hunk #16 succeeded at 3655 (offset 120 lines).
+Hunk #17 succeeded at 4074 (offset 35 lines).
+Hunk #18 succeeded at 4411 (offset 138 lines).
+Hunk #19 failed at 5190.
+Hunk #20 succeeded at 5319 (offset 35 lines).
+Hunk #21 succeeded at 5446 (offset 138 lines).
+Hunk #22 succeeded at 5390 (offset 35 lines).
+Hunk #23 succeeded at 5578 (offset 138 lines).
+5 out of 23 hunks failed--saving rejects to sched.c.rej
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/toplev.c gcc-i2.5.8/toplev.c
+|*** gcc-2.5.8/toplev.c	Fri Dec 10 17:59:54 1993
+|--- gcc-i2.5.8/toplev.c	Mon Jun 20 08:27:48 1994
+--------------------------
+Patching file toplev.c using Plan A...
+Hunk #1 succeeded at 192 (offset 20 lines).
+Hunk #2 succeeded at 343 (offset 6 lines).
+Hunk #3 succeeded at 582 (offset 20 lines).
+Hunk #4 succeeded at 871 (offset 41 lines).
+Hunk #5 succeeded at 872 (offset 20 lines).
+Hunk #6 succeeded at 1043 (offset 42 lines).
+Hunk #7 succeeded at 2083 (offset 409 lines).
+Hunk #8 failed at 2251.
+Hunk #9 succeeded at 2248 (offset -6 lines).
+Hunk #10 succeeded at 2697 (offset 409 lines).
+Hunk #11 succeeded at 2737 (offset 8 lines).
+Hunk #12 succeeded at 3172 (offset 409 lines).
+Hunk #13 succeeded at 2863 (offset 8 lines).
+Hunk #14 succeeded at 3283 (offset 409 lines).
+Hunk #15 succeeded at 2977 (offset 8 lines).
+Hunk #16 succeeded at 3445 (offset 414 lines).
+Hunk #17 succeeded at 3308 (offset 17 lines).
+Hunk #18 succeeded at 3732 (offset 414 lines).
+Hunk #19 succeeded at 3759 (offset 35 lines).
+1 out of 19 hunks failed--saving rejects to toplev.c.rej
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/unroll.c gcc-i2.5.8/unroll.c
+|*** gcc-2.5.8/unroll.c	Wed Nov 10 17:46:37 1993
+|--- gcc-i2.5.8/unroll.c	Mon Jun 20 08:19:36 1994
+--------------------------
+Patching file unroll.c using Plan A...
+Hunk #1 succeeded at 152.
+Hunk #2 succeeded at 1688 (offset -7 lines).
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/varasm.c gcc-i2.5.8/varasm.c
+|*** gcc-2.5.8/varasm.c	Mon Jan 10 17:17:55 1994
+|--- gcc-i2.5.8/varasm.c	Mon Jun 20 08:28:49 1994
+--------------------------
+Patching file varasm.c using Plan A...
+Hunk #1 succeeded at 72 with fuzz 1 (offset 1 line).
+Hunk #2 succeeded at 1079 (offset 47 lines).
+Hunk #3 succeeded at 1065 (offset 1 line).
+Hunk #4 succeeded at 1269 (offset 66 lines).
+Hunk #5 succeeded at 3029 with fuzz 2 (offset 28 lines).
+Hmm...  The next patch looks like a new-style context diff to me...
+The text leading up to this was:
+--------------------------
+|diff -r -C6 -d gcc-2.5.8/version.c gcc-i2.5.8/version.c
+|*** gcc-2.5.8/version.c	Sat Jan  1 04:26:51 1994
+|--- gcc-i2.5.8/version.c	Mon Jun 20 08:29:54 1994
+--------------------------
+Patching file version.c using Plan A...
+Hunk #1 failed at 1.
+1 out of 1 hunks failed--saving rejects to version.c.rej
+done
diff -r -u -H -N gcc-2.6.3/jump.c gcc-i2.6.3/jump.c
--- gcc-2.6.3/jump.c	Sat Oct  1 20:34:13 1994
+++ gcc-i2.6.3/jump.c	Wed Feb 15 22:47:07 1995
@@ -1827,7 +1827,16 @@
 
 	      /* First, cross jumping of conditional jumps:  */
 
-	      if (cross_jump && condjump_p (insn))
+	      if (cross_jump && condjump_p (insn)
+	      /* intel1 */
+#ifdef NO_CROSS_JUMP_ON_LOOP_ENTRY
+                  && !(GET_CODE (NEXT_INSN(insn)) == NOTE
+	               && 
+	               (NOTE_LINE_NUMBER (NEXT_INSN(insn)) == NOTE_INSN_LOOP_BEG 
+	                || NOTE_LINE_NUMBER (NEXT_INSN(insn)) == NOTE_INSN_LOOP_END)
+	              )
+#endif
+	         )
 		{
 		  rtx newjpos, newlpos;
 		  rtx x = prev_real_insn (JUMP_LABEL (insn));
diff -r -u -H -N gcc-2.6.3/loop.c gcc-i2.6.3/loop.c
--- gcc-2.6.3/loop.c	Wed Nov 16 19:29:26 1994
+++ gcc-i2.6.3/loop.c	Thu Feb 16 12:59:32 1995
@@ -38,6 +38,7 @@
 #include "rtl.h"
 #include "obstack.h"
 #include "expr.h"
+#include "basic-block.h" /* intel1 */
 #include "insn-config.h"
 #include "insn-flags.h"
 #include "regs.h"
@@ -45,6 +46,7 @@
 #include "recog.h"
 #include "flags.h"
 #include "real.h"
+#include "reload.h" /* intel1 */
 #include "loop.h"
 
 /* Vector mapping INSN_UIDs to luids.
@@ -185,6 +187,9 @@
 
 static struct obstack temp_obstack;
 
+/* intel1 */
+extern struct obstack momentary_obstack;
+
 /* This is where the pointer to the obstack being used for RTL is stored.  */
 
 extern struct obstack *rtl_obstack;
@@ -280,6 +285,64 @@
 static int last_use_this_basic_block ();
 static void record_initial ();
 static void update_reg_last_use ();
+/* intel1 */
+static int compare_elimination ();
+static attempt_new_rtx ();
+static rtx make_new_use ();
+static int possible_compare_elimination ();
+static void find_regs_mentioned ();
+static void use_regs_source ();
+static rtx replace_mems ();
+static void replace_reg  ();
+static int two_to_power ();
+static int jumps_back_in_loop ();
+static loop_copy_propogate ();
+static do_replace ();
+static rtx subst_cands ();
+static try_unroll_propogation ();
+static rtx unroll_subst_cands ();
+static unroll_consistancy_maintained ();
+static int do_reduce_index ();
+static loop_spl ();
+void loop_after_global ();
+static int spill_invariant_p ();
+static void move_spills_out ();
+static void move_spill_movables ();
+static rtx subst_stack_slot ();
+static int check_if_jumps_out_of_loop ();
+static void mark_regs_alive_at_exit ();
+static void verify_spill_candidates ();
+static void mark_spill_candidates ();
+static void spill_handle_regs_mentioned ();
+static int is_updated_by_const ();
+static int is_updated_by_const_or_reg ();
+static void peep_init_info ();
+static void spill_peep_insn ();
+void update_stack_offset ();
+static void replace_spill_slots ();
+static rtx replace_linked_regs ();
+static void mark_regs_live_outside ();
+static void mark_regs_mentioned ();
+static int loop_contains_loop ();
+static void push_load_into_loop ();
+static int spill_slot_unused_between ();
+static int spill_slot_mentioned ();
+void init_undo_buf ();
+void subst_in_insn ();
+static void inner_subst_in_insn ();
+void loop_undo_all ();
+static void update_last_reloads ();
+static void sign_extension_reduction ();
+static void validate_all_references ();
+static void lift_stores ();
+static void mark_mem_refs ();
+static void insert_mem_ref ();
+static void opt_reg_use_copy ();
+int doing_spl = 0;
+int doing_loop_after_global = 0;
+static char * reg_live_outside_loop;
+static int cur_stack_offset = 0;
+
 
 /* Relative gain of eliminating various kinds of operations.  */
 int add_cost;
@@ -287,6 +350,10 @@
 int shift_cost;
 int mult_cost;
 #endif
+/* intel1 maximum # of insns in loop for which compare elimination */
+#ifndef MAX_CMP_ELIM
+#define MAX_CMP_ELIM 100
+#endif
 
 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
    copy the value of the strength reduced giv to its original register.  */
@@ -335,6 +402,12 @@
 
   max_reg_before_loop = max_reg_num ();
 
+  /* intel1 */
+#ifdef SAVE_ON_REGS
+  if (!flag_all_mem_givs && flag_opt_reg_use)
+    reg_live_outside_loop = (char *) alloca(max_reg_before_loop);
+#endif
+
   moved_once = (char *) alloca (max_reg_before_loop);
   bzero (moved_once, max_reg_before_loop);
 
@@ -352,7 +425,17 @@
 
   /* Don't waste time if no loops.  */
   if (max_loop_num == 0)
-    return;
+    {
+      /* intel1 */
+#ifdef SAVE_ON_REGS
+      if (!doing_loop_after_global && flag_opt_reg_use)
+        {
+          use_regs_source (f, NULL, 0);
+          opt_reg_use_copy (f);
+        }
+#endif
+      return;
+    }
 
   /* Get size to use for tables indexed by uids.
      Leave some space for labels allocated by find_and_verify_loops.  */
@@ -379,7 +462,8 @@
   /* Now find all register lifetimes.  This must be done after
      find_and_verify_loops, because it might reorder the insns in the
      function.  */
-  reg_scan (f, max_reg_num (), 1);
+  /* intel1  Last paramater of reg_scan used to be 1.  */
+  reg_scan (f, max_reg_num (), !doing_loop_after_global);
 
   /* See if we went too far.  */
   if (get_max_uid () > max_uid_for_loop)
@@ -430,6 +514,43 @@
       scan_loop (loop_number_loop_starts[i], loop_number_loop_ends[i],
 		 max_reg_num ());
 
+  /* intel1 */
+  if (flag_strength_reduce && flag_copy_prop)
+    {  
+      for (i = max_loop_num-1; i >= 0; i--)
+        {
+          if (! loop_invalid[i] && loop_number_loop_ends[i])
+            loop_copy_propogate (loop_number_loop_starts[i], loop_number_loop_ends[i]);
+        }
+    }
+  /* intel1 */
+  if ((flag_lift_stores || flag_runtime_lift_stores) 
+      && !doing_loop_after_global)
+    {  
+      for (i = max_loop_num-1; i >= 0; i--)
+        {
+          if (! loop_invalid[i] && loop_number_loop_ends[i])
+               lift_stores (loop_number_loop_starts[i], loop_number_loop_ends[i]);
+        }
+    }
+
+#ifdef SAVE_ON_REGS
+  if (!doing_loop_after_global && flag_opt_reg_use)
+    {
+      use_regs_source (f, NULL, 0); 
+      opt_reg_use_copy (f);
+    }
+#endif
+  /* intel1 */
+#ifdef STORE_NOT_SET_CC0
+#ifdef STACK_REGS
+  if (flag_sftwr_pipe && !doing_loop_after_global)
+      for (i = max_loop_num-1; i >= 0; i--)
+        {
+          loop_spl (loop_number_loop_starts[i], loop_number_loop_ends[i], i, 0);
+        }
+#endif
+#endif
   /* If debugging and unrolling loops, we must replicate the tree nodes
      corresponding to the blocks inside the loop, so that the original one
      to one mapping will remain.  */
@@ -486,9 +607,29 @@
      if it was used exactly once; contains const0_rtx if it was used more
      than once.  */
   rtx *reg_single_usage = 0;
+  
   /* Nonzero if we are scanning instructions in a sub-loop.  */
   int loop_depth = 0;
 
+  /* intel1 */
+  if (doing_loop_after_global
+     && !(GET_CODE (PREV_INSN (end)) == JUMP_INSN
+     &&   GET_CODE (NEXT_INSN (loop_start)) == CODE_LABEL
+     &&   JUMP_LABEL (PREV_INSN (end)) == NEXT_INSN (loop_start)
+      )
+    )
+  {
+    return;
+  }
+#ifdef SAVE_ON_REGS
+  if (!flag_all_mem_givs && !doing_loop_after_global
+     && !loop_contains_loop (loop_start, end) && flag_opt_reg_use)
+    {
+      bzero (reg_live_outside_loop, max_reg_before_loop);
+      mark_regs_live_outside (loop_start, end);
+    }
+#endif
+
   n_times_set = (short *) alloca (nregs * sizeof (short));
   n_times_used = (short *) alloca (nregs * sizeof (short));
   may_not_optimize = (char *) alloca (nregs);
@@ -584,7 +725,8 @@
 
   count_loop_regs_set (loop_top ? loop_top : loop_start, end,
 		       may_not_optimize, reg_single_usage, &insn_count, nregs);
-
+  /* intel1 added if but not body */
+  if (!doing_loop_after_global)
   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
     may_not_optimize[i] = 1, n_times_set[i] = 1;
   bcopy ((char *) n_times_set, (char *) n_times_used, nregs * sizeof (short));
@@ -637,6 +779,8 @@
 	in_libcall = 0;
 
       if (GET_CODE (p) == INSN
+          /* intel1 */
+      && (!doing_loop_after_global || GET_CODE(PATTERN(p)) == SET)
 	  && (set = single_set (p))
 	  && GET_CODE (SET_DEST (set)) == REG
 	  && ! may_not_optimize[REGNO (SET_DEST (set))])
@@ -688,11 +832,19 @@
 	  else if (! ((! maybe_never
 		       && ! loop_reg_used_before_p (set, p, loop_start,
 						    scan_start, end))
-		      || (! REG_USERVAR_P (SET_DEST (set))
-			  && ! REG_LOOP_TEST_P (SET_DEST (set)))
+		      ||  (!doing_loop_after_global 
+		           && /* intel1 */!REG_USERVAR_P (SET_DEST (set))
+		           && ! REG_LOOP_TEST_P (SET_DEST (set)))
 		      || reg_in_basic_block_p (p, SET_DEST (set))))
 	    ;
-	  else if ((tem = invariant_p (src))
+	  else if (((tem = invariant_p (src))
+	             /* intel1 */ || (doing_loop_after_global 
+	             && RTX_IS_SPILL_P (p) == 1 && spill_invariant_p (src))
+	           )
+	           /* intel1 */
+                    && !(doing_loop_after_global 
+	            && call_used_regs[REGNO (SET_DEST (set))]
+	            && loop_has_call)
 		   && (dependencies == 0
 		       || (tem2 = invariant_p (dependencies)) != 0)
 		   && (n_times_set[REGNO (SET_DEST (set))] == 1
@@ -742,6 +894,7 @@
 		     might span a call.  */
 		  && ! modified_between_p (SET_SRC (set), p,
 					   reg_single_usage[regno])
+          && !doing_loop_after_global /* intel1 */
 		  && no_labels_between_p (p, reg_single_usage[regno])
 		  && validate_replace_rtx (SET_DEST (set), SET_SRC (set),
 					   reg_single_usage[regno]))
@@ -957,12 +1110,25 @@
   move_movables (movables, threshold,
 		 insn_count, loop_start, end, nregs);
 
+  /* intel1 */
+  if (doing_loop_after_global && !loop_has_call)
+    {
+      move_spills_out(loop_start, end, nregs);
+    }
   /* Now candidates that still are negative are those not moved.
      Change n_times_set to indicate that those are not actually invariant.  */
   for (i = 0; i < nregs; i++)
     if (n_times_set[i] < 0)
       n_times_set[i] = n_times_used[i];
 
+  /*intel1 */
+#ifdef SAVE_ON_REGS
+   if (!doing_loop_after_global && flag_opt_reg_use)
+   {
+     use_regs_source(loop_start, end, 1); 
+   }
+#endif
+
   if (flag_strength_reduce)
     strength_reduce (scan_start, end, loop_top,
 		     insn_count, loop_start, end);
@@ -1248,7 +1414,7 @@
 	      /* A reg used for zero-extending mustn't be eliminated.  */
 	      && !m1->partial
 	      && (matched_regs[m1->regno]
-		  ||
+		  || 
 		  (
 		   /* Can combine regs with different modes loaded from the
 		      same constant only if the modes are the same or
@@ -1525,6 +1691,13 @@
      rtx end;
      int nregs;
 {
+/* intel1 */
+#ifdef SAVE_ON_REGS
+  rtx sinsn,last_sym;
+  int num_sym_adds;
+#endif
+  /* intel1 */
+  int *insns_deleted;
   rtx new_start = 0;
   register struct movable *m;
   register rtx p;
@@ -1539,6 +1712,46 @@
 
   num_movables = 0;
 
+  /* intel1 */
+  num_movables = 0;
+
+/* intel1 Any insn moved out of loop must be deleted from the log_links
+          of all other insns in the loop.
+*/
+  if (doing_loop_after_global)
+    {
+        insns_deleted = (int *) alloca ((max_uid_for_loop+1) * sizeof (int));
+        bzero(insns_deleted,(max_uid_for_loop+1) * sizeof (int));
+    }
+/* intel1 */
+#ifdef SAVE_ON_REGS
+  num_sym_adds=0;
+  last_sym = NULL;
+  for (sinsn=loop_start;flag_opt_reg_use && (sinsn!=end && num_sym_adds < 2);
+        sinsn=NEXT_INSN (sinsn))
+     {
+        if (GET_CODE (sinsn) == INSN
+           && GET_CODE (PATTERN (sinsn)) == SET
+           && GET_CODE (SET_DEST (PATTERN (sinsn))) == REG
+           && GET_CODE (SET_SRC (PATTERN (sinsn))) == PLUS
+           && GET_CODE (XEXP (SET_SRC (PATTERN (sinsn)), 0)) == REG
+           && GET_CODE (XEXP (SET_SRC (PATTERN (sinsn)), 1)) == SYMBOL_REF)
+      {
+        if (last_sym)
+      {
+        if (!rtx_equal_p (XEXP (SET_SRC (PATTERN (sinsn)), 1),
+                        last_sym))
+          {
+            num_sym_adds++;
+          }
+      }
+        else
+      {
+        last_sym = XEXP (SET_SRC (PATTERN (sinsn)), 1);
+      }
+      }
+    }
+#endif /* SAVE_ON_REGS */
   for (m = movables; m; m = m->next)
     {
       /* Describe this movable insn.  */
@@ -1617,7 +1830,30 @@
 
 	  /* It is also desirable to move if it can be moved at no
 	     extra cost because something else was already moved.  */
-
+#ifdef SAVE_ON_REGS
+  	  /* intel1 if the insn is regx <- regy + symbol_ref then don't move
+  	     if there is more than one.  
+  	  */
+  	  if (flag_opt_reg_use
+  	     && num_sym_adds > 1 
+  	     && GET_CODE (PATTERN (m->insn)) == SET 
+  	     && GET_CODE (SET_DEST (PATTERN (m->insn))) == REG 
+  	     && GET_CODE (SET_SRC (PATTERN (m->insn))) == PLUS 
+  	     && GET_CODE (XEXP (SET_SRC (PATTERN (m->insn)), 0)) == REG 
+  	     && GET_CODE (XEXP (SET_SRC (PATTERN (m->insn)), 1)) == SYMBOL_REF)
+	    {
+	      savings = 0;
+	    } 
+#endif  	     
+/* intel1 */
+#ifdef STACK_REGS
+#ifdef IS_STACK_MODE
+          if (IS_STACK_MODE (DFmode)
+             && GET_CODE (PATTERN (m->insn)) == SET 
+             && GET_CODE (SET_SRC (PATTERN (m->insn))) == CONST_DOUBLE)
+            savings = 0; /* not worthwhile */
+#endif
+#endif
 	  if (already_moved[regno]
 	      || (threshold * savings * m->lifetime) >= insn_count
 	      || (m->forces && m->forces->done
@@ -1650,11 +1886,24 @@
 		  regs_may_share = gen_rtx (EXPR_LIST, VOIDmode, r1,
 					    gen_rtx (EXPR_LIST, VOIDmode, r2,
 						     regs_may_share));
+                  /* intel1 */
+                  if (doing_loop_after_global 
+                     && INSN_UID (m->insn) <= max_uid_for_loop)
+                    {
+                      insns_deleted[INSN_UID (m->insn)] = 1;
+                    }
 		  delete_insn (m->insn);
 
 		  if (new_start == 0)
 		    new_start = i1;
 
+                  /* intel1 */
+                  if (doing_loop_after_global)
+                    {
+                      RTX_IS_SPILL_P (i1) = RTX_IS_SPILL_P (m->insn);
+                      SPILL_PSEUDO (i1) = SPILL_PSEUDO (m->insn);
+                    }
+                    
 		  if (loop_dump_stream)
 		    fprintf (loop_dump_stream, " moved to %d", INSN_UID (i1));
 		}
@@ -1681,8 +1930,22 @@
 			{
 			  temp = XEXP (temp, 0);
 			  while (temp != p)
-			    temp = delete_insn (temp);
+              {
+                  /* intel1 */
+                  if (doing_loop_after_global
+                      && INSN_UID( temp) <= max_uid_for_loop)
+                  {
+                       insns_deleted[INSN_UID( temp)] = 1;
+                  }
+                temp = delete_insn (temp);
+              }
 			}
+               /* intel1 */
+             if (doing_loop_after_global
+                && INSN_UID( p) <= max_uid_for_loop)
+             {
+                 insns_deleted[INSN_UID( p)] = 1;
+              }
 
 		      p = delete_insn (p);
 		      while (p && GET_CODE (p) == NOTE)
@@ -1703,6 +1966,13 @@
 				 m->is_equiv ? REG_EQUIV : REG_EQUAL,
 				 m->set_src, REG_NOTES (i1));
 
+                  /* intel1 */
+                  if (doing_loop_after_global)
+                    {
+                      RTX_IS_SPILL_P (i1) = RTX_IS_SPILL_P (m->insn);
+                      SPILL_PSEUDO (i1) = SPILL_PSEUDO (m->insn);
+                    }
+
 		  if (loop_dump_stream)
 		    fprintf (loop_dump_stream, " moved to %d", INSN_UID (i1));
 
@@ -1804,6 +2074,12 @@
 			      if (temp == fn_address_insn)
 				fn_address_insn = i1;
 			      REG_NOTES (i1) = REG_NOTES (temp);
+                              /* intel1 */
+                              if (doing_loop_after_global 
+                                 && INSN_UID (temp) <= max_uid_for_loop)
+                                {
+                                  insns_deleted[INSN_UID (temp)] = 1;
+                                }
 			      delete_insn (temp);
 			    }
 			}
@@ -1859,6 +2135,13 @@
 		      if (new_start == 0)
 			new_start = i1;
 
+                      /* intel1 */
+                      if (doing_loop_after_global)
+                        {
+                          RTX_IS_SPILL_P (i1) = RTX_IS_SPILL_P (m->insn);
+                          SPILL_PSEUDO (i1) = SPILL_PSEUDO (m->insn);
+                        }
+                        
 		      if (loop_dump_stream)
 			fprintf (loop_dump_stream, " moved to %d",
 				 INSN_UID (i1));
@@ -1886,6 +2169,12 @@
 			  XEXP (temp, 0) = i1;
 			}
 
+                      /* intel1 */
+                      if (doing_loop_after_global 
+                         && INSN_UID (p) <= max_uid_for_loop)
+                        {
+                          insns_deleted[INSN_UID (p)] = 1;
+                        }
 		      delete_insn (p);
 		      do p = NEXT_INSN (p);
 		      while (p && GET_CODE (p) == NOTE);
@@ -1950,8 +2239,22 @@
 			{
 			  for (temp = XEXP (temp, 0); temp != m1->insn;
 			       temp = NEXT_INSN (temp))
-			    delete_insn (temp);
+			    {
+                              /* intel1 */
+                              if (doing_loop_after_global 
+                                 && INSN_UID (temp) <= max_uid_for_loop)
+                                {
+                                  insns_deleted[INSN_UID (temp)] = 1;
+                                }
+			      delete_insn (temp);
+			    }
 			}
+                      /* intel1 */
+                      if (doing_loop_after_global 
+                         && INSN_UID (m1->insn) <= max_uid_for_loop)
+                        {
+                          insns_deleted[INSN_UID (m1->insn)] = 1;
+                        }
 		      delete_insn (m1->insn);
 
 		      /* Any other movable that loads the same register
@@ -1987,6 +2290,34 @@
 	replace_regs (REG_NOTES (p), reg_map, nregs, 0);
 	INSN_CODE (p) = -1;
       }
+  /* intel1 */
+  /* remove all deleted insns from the log_links of any insn in which
+     they appear */
+  if (doing_loop_after_global)
+    {
+        int i;
+        rtx rn,prev,link;
+
+        for (rn=loop_start; rn!=end; rn=NEXT_INSN (rn))
+          {
+              if ((GET_CODE (rn) == INSN || GET_CODE (rn) == JUMP_INSN
+	               || GET_CODE (rn) == CALL_INSN) && LOG_LINKS(rn))
+                {
+                    for (prev = 0, link = LOG_LINKS (rn); link;
+                         prev = link, link = XEXP (link, 1))
+                      {
+                          if (insns_deleted[INSN_UID(XEXP (link, 0))])
+	                    {
+	                      if (prev)
+	                        XEXP (prev, 1) = XEXP (link, 1);
+	                      else
+	                        LOG_LINKS (rn) = XEXP (link, 1);
+	                    }
+                      }
+
+                }
+          }
+    }
 }
 
 #if 0
@@ -2268,6 +2599,9 @@
       uid_loop_num[INSN_UID (insn)] = current_loop;
     }
 
+		    /* This loop will be continued with NEXT_INSN (insn).  */
+		    insn = PREV_INSN (insn);
+
   /* Any loop containing a label used in an initializer must be invalidated,
      because it can be jumped into from anywhere.  */
 
@@ -2281,6 +2615,17 @@
 	loop_invalid[loop_num] = 1;
     }
 
+
+#if HAVE_movstricthi
+  if (flag_sign_extension_elim)
+    {
+      int i;
+      for (i = max_loop_num-1; i >= 0; i--)
+        if (! loop_invalid[i] && loop_number_loop_ends[i])
+          sign_extension_reduction (loop_number_loop_starts[i],
+                                    loop_number_loop_ends [i]);
+    }
+#endif
   /* Now scan all insn's in the function.  If any JUMP_INSN branches into a
      loop that it is not contained within, that loop is marked invalid.
      If any INSN or CALL_INSN uses a label's address, then the loop containing
@@ -2294,11 +2639,12 @@
      label in our loop and will simplify processing by both us and a
      possible second cse pass.  */
 
+
   for (insn = f; insn; insn = NEXT_INSN (insn))
     if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
       {
 	int this_loop_num = uid_loop_num[INSN_UID (insn)];
-
+        
 	if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
 	  {
 	    rtx note = find_reg_note (insn, REG_LABEL, NULL_RTX);
@@ -2339,6 +2685,32 @@
 		 p = PREV_INSN (p))
 	      ;
 
+	      /* intel1 */
+            if (flag_opt_jumps_out)
+              {
+                /* Retarget a jump around a sequence that contains jumps out 
+                   of loop to jump out of the loop rather than jump around.  */
+                while (!(GET_CODE (p) == JUMP_INSN
+		        && JUMP_LABEL (p) != 0
+		        && condjump_p (p)
+		        && ! simplejump_p (p)
+		        && next_real_insn (JUMP_LABEL (p)) == our_next
+		       ) &&
+		      !(GET_CODE (p) == JUMP_INSN 
+		        && (JUMP_LABEL (p) == 0 
+		         || (uid_loop_num[INSN_UID (JUMP_LABEL (p))]
+			    == this_loop_num))
+		       ) 
+		      && GET_CODE (p) != CODE_LABEL 
+		      && !(GET_CODE (p) == NOTE
+		           && NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG) 
+		      && !(GET_CODE (p) == NOTE
+		           && NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)
+		     )
+                  {
+                    p = PREV_INSN (p);
+                  }
+              }
 	    /* If we stopped on a JUMP_INSN to the next insn after INSN,
 	       we have a block of code to try to move.
 
@@ -2373,7 +2745,15 @@
 			&& uid_loop_num[INSN_UID (loc)] == target_loop_num)
 		      break;
 
-		if (loc)
+		if (loc 
+		     ||
+		    /* intel1 Enable the optimization even if no barier
+		              is found.  This requires adding a jump
+		              around the section of code moved out - but
+		              this can win if jumps NOT taken are preferred.  
+		    */
+		    (flag_opt_jumps_out 
+		         && LABEL_NUSES (JUMP_LABEL (p)) == 1))
 		  {
 		    rtx cond_label = JUMP_LABEL (p);
 		    rtx new_label = get_label_after (p);
@@ -2390,7 +2770,12 @@
 		       /* Include the BARRIER after INSN and copy the
 			  block after LOC.  */
 		       new_label = squeeze_notes (new_label, NEXT_INSN (insn));
-		       reorder_insns (new_label, NEXT_INSN (insn), loc);
+		       /* intel1 */
+		       if (loc)
+		         reorder_insns (new_label, NEXT_INSN (insn), loc);
+		       else
+		         reorder_insns (new_label, NEXT_INSN (insn), 
+		                      PREV_INSN (target));
 
 		       /* All those insns are now in TARGET_LOOP_NUM.  */
 		       for (q = new_label; q != NEXT_INSN (NEXT_INSN (insn));
@@ -2427,14 +2812,24 @@
 			  in loop_number_exit_labels, and marked as such.
 			  The easiest way to do this is to just call
 			  mark_loop_jump again for P.  */
+        
 		       mark_loop_jump (PATTERN (p), this_loop_num);
-
-		       /* If INSN now jumps to the insn after it,
-			  delete INSN.  */
-		       if (JUMP_LABEL (insn) != 0
-			   && (next_real_insn (JUMP_LABEL (insn))
-			       == next_real_insn (insn)))
-			 delete_insn (insn);
+                       /* intel1 */
+                       if (loc)
+                         {
+		           /* If INSN now jumps to the insn after it,
+			      delete INSN.  */
+		           if (JUMP_LABEL (insn) != 0
+			       && (next_real_insn (JUMP_LABEL (insn))
+			           == next_real_insn (insn)))
+			     delete_insn (insn);
+			 }
+		       else
+		         {
+		           /* move the jump insn to just before the new_label */
+		           reorder_insns (insn, NEXT_INSN (insn),
+		                          PREV_INSN (new_label));
+		         }
 		     }
 
 		    /* Continue the loop after where the conditional
@@ -2443,11 +2838,16 @@
 		       branch and hence needs no processing.  */
 		    insn = NEXT_INSN (cond_label);
 
-		    if (--LABEL_NUSES (cond_label) == 0)
-		      delete_insn (cond_label);
-
-		    /* This loop will be continued with NEXT_INSN (insn).  */
-		    insn = PREV_INSN (insn);
+                       /* intel1 */
+                    if (loc)
+                      {
+		        if (--LABEL_NUSES (cond_label) == 0)
+		          delete_insn (cond_label);
+		       }
+		     else
+		       {
+		          delete_insn (cond_label);
+		       }
 		  }
 	      }
 	  }
@@ -2535,7 +2935,16 @@
 		     "\nLoop at %d ignored due to multiple entry points.\n",
 		     INSN_UID (loop_number_loop_starts[dest_loop]));
 	  
+	  /* intel1
+	     If doing loop_spl we don't care if there are multiple jumps
+	     to the loop entry label.  */
+	  if (!doing_spl 
+	      || NEXT_INSN (loop_number_loop_starts[dest_loop]) 
+	           != XEXP (x, 0))
+	  {
+	    
 	  loop_invalid[dest_loop] = 1;
+	  }
 	}
       return;
 
@@ -2755,7 +3164,6 @@
   return 1 + conditional;
 }
 
-
 /* Return nonzero if all the insns in the loop that set REG
    are INSN and the immediately following insns,
    and if each of those insns sets REG in an invariant way
@@ -2984,6 +3392,22 @@
 		    may_not_move[regno] = 1;
 		  if (n_times_set[regno] < 127)
 		    ++n_times_set[regno];
+		  /* intel1 */
+		  if (doing_loop_after_global 
+		     && HARD_REGNO_NREGS (regno, GET_MODE (dest)) > 1)
+		    { /* Count each hard reg in the group.  */
+		        register int i,next_regno;
+
+		        i = HARD_REGNO_NREGS (regno, GET_MODE (dest));
+		        next_regno = regno + 1;
+		        while (i!=1)
+		          {
+		              if (n_times_set[next_regno] < 127)
+		                ++n_times_set[next_regno];
+		              next_regno++;
+		              i--;
+		          }
+		    }
 		  last_set[regno] = insn;
 		}
 	    }
@@ -3181,6 +3605,9 @@
   int call_seen;
   rtx test;
   rtx end_insert_before;
+  int try_compare_elimination, done_compare_elimination; /* intel1 */
+  rtx compare_insn, jump_insn, tinsn; /* intel1 */
+  int *times_reg_used; /* intel1 */
   int loop_depth = 0;
 
   reg_iv_type = (enum iv_mode *) alloca (max_reg_before_loop
@@ -3310,7 +3737,10 @@
 	     will be executed if the loop is executed.  */
 	  && ! (GET_CODE (p) == JUMP_INSN && JUMP_LABEL (p) == loop_top
 		&& ((NEXT_INSN (NEXT_INSN (p)) == loop_end && simplejump_p (p))
-		    || (NEXT_INSN (p) == loop_end && condjump_p (p)))))
+          || (NEXT_INSN (p) == loop_end && condjump_p (p))))
+     /*intel1*/  && !(GET_CODE (p) == JUMP_INSN
+                      && jumps_back_in_loop(p,loop_start,0,0))
+    )
 	not_every_iteration = 1;
 
       else if (GET_CODE (p) == NOTE)
@@ -3424,6 +3854,18 @@
 	}
     }
 
+  /* Now see if it is wothwhile to do compare elimination, remember it only
+     saves one instruction.  intel1
+  */
+  try_compare_elimination = 0;
+  if (flag_compare_elim 
+     && loop_number_exit_labels[uid_loop_num[INSN_UID (loop_start)]] == NULL)
+  {
+    possible_compare_elimination(loop_start, loop_end, &compare_insn, 
+                                 &jump_insn, &try_compare_elimination);
+    done_compare_elimination = 0;
+  }
+
   /* Look at the each biv and see if we can say anything better about its
      initial value from any initializing insns set up above.  (This is done
      in two passes to avoid missing SETs in a PARALLEL.)  */
@@ -3445,6 +3887,21 @@
 	   || GET_MODE (src) == VOIDmode)
 	  && valid_initial_value_p (src, bl->init_insn, call_seen, loop_start))
 	{
+	  /* intel1 */
+	  if (flag_compare_elim && !flag_unroll_loops 
+	     && try_compare_elimination && !done_compare_elimination 
+	     && bl->biv_count == 1 
+	     && bl->biv->mult_val == const1_rtx 
+	     && REGNO (XEXP (SET_SRC (PATTERN (compare_insn)), 0)) == bl->regno 
+	     &&  (done_compare_elimination 
+	     = compare_elimination (bl, loop_start, loop_end, 
+	                         compare_insn, jump_insn,0)))
+	    {
+    	      rtx tem = find_reg_note (bl->init_insn, REG_EQUAL, 0);
+	      if (tem)
+		XEXP (tem, 0) = SET_SRC (bl->init_set);
+	      src = SET_SRC (bl->init_set);
+	    }
 	  bl->initial_value = src;
 
 	  if (loop_dump_stream)
@@ -3588,7 +4045,10 @@
 	     will be executed if the loop is executed.  */
 	  && ! (GET_CODE (p) == JUMP_INSN && JUMP_LABEL (p) == loop_top
 		&& ((NEXT_INSN (NEXT_INSN (p)) == loop_end && simplejump_p (p))
-		    || (NEXT_INSN (p) == loop_end && condjump_p (p)))))
+          || (NEXT_INSN (p) == loop_end && condjump_p (p))))
+     /*intel1*/ && !(GET_CODE (p) == JUMP_INSN
+                     && jumps_back_in_loop(p,loop_start,0,0))
+    )
 	not_every_iteration = 1;
 
       else if (GET_CODE (p) == NOTE)
@@ -3654,6 +4114,12 @@
   for (bl = loop_iv_list; bl; bl = bl->next)
     {
       struct induction *v;
+      /* intel1 */
+#ifdef SAVE_ON_REGS
+      int num_add_vals_live_outside =0;
+      int no_mem_givs = 0;
+      int contains_loop =0;
+#endif
       int benefit;
       int all_reduced;
       rtx final_value = 0;
@@ -3711,6 +4177,97 @@
 	 We can't (currently) eliminate the biv unless this is so.  */
       all_reduced = 1;
 
+      /* intel1 */
+#ifdef SAVE_ON_REGS
+      /* Only reduce DEST_ADDR givs of this biv if they will not increase
+         register pressure.  
+      */
+      if (!flag_all_mem_givs && flag_opt_reg_use)
+        {
+          int num_mult_val_saved = 0;
+          int num_givs_to_update = 0;
+          num_add_vals_live_outside = 0;
+          no_mem_givs = 0;
+          contains_loop = loop_contains_loop (loop_start, end);
+        
+          for (v = bl->giv; v; v = v->next_iv)
+            {
+              if (v->giv_type == DEST_ADDR)
+                num_mult_val_saved++;
+              if (v->giv_type == DEST_ADDR && !v->same)
+                {
+                  num_givs_to_update++;
+                  if (v->add_val && GET_CODE (v->add_val) == REG 
+                     && REGNO (v->add_val) >= FIRST_PSEUDO_REGISTER 
+                     && (contains_loop 
+                         || REGNO (v->add_val)<max_reg_before_loop))
+                    {
+                      if (loop_dump_stream 
+                         && reg_live_outside_loop[REGNO (v->add_val)])
+                        {
+                          fprintf (loop_dump_stream, 
+                          "dest addr giv at %d has add_val live outside reg%d\n", 
+                          INSN_UID (v->insn), REGNO (v->add_val));
+                        }
+                      if (contains_loop)
+                        num_add_vals_live_outside += 2;
+                      else
+                        {
+                          num_add_vals_live_outside += 
+                            reg_live_outside_loop[REGNO (v->add_val)];
+                        }
+                    }
+                  else if (v->add_val && GET_CODE (v->add_val) == CONST_INT 
+                           && v->mult_val == const1_rtx)
+                    { /* Disable this reduction. */
+                      num_add_vals_live_outside = (1 << ((sizeof (int)*8)-4));
+                    }
+                }
+            }
+#ifdef MAX_DEST_ADDR_GIVS
+        if (num_givs_to_update > MAX_DEST_ADDR_GIVS)
+          {
+            no_mem_givs = 1;
+          }
+#endif
+        /* Heuristic here:
+           a) If the biv is eliminated that saves one register in the loop.  
+           b) Each giv_to_update must be updated at the end of the loop.  
+           c) Each add_val_live_outside may cause a spill somewhere.  
+        */
+        if (loop_dump_stream)
+          {
+            fprintf (loop_dump_stream,
+            "eliminable %d num_updates %d mults_saved %d adds_outside %d heu %d\n",
+            bl->eliminable, num_givs_to_update, num_mult_val_saved,
+            num_add_vals_live_outside,
+            (((int)(bl->eliminable) * -3) 
+             + (num_givs_to_update+((int)(bl->eliminable) * -1)) 
+             + (num_mult_val_saved*-1) +
+             + (num_add_vals_live_outside*3) 
+            ));
+          }
+        if (no_mem_givs 
+            ||  
+            (((int)(bl->eliminable) * -3) 
+             + (num_givs_to_update+((int)(bl->eliminable) * -1)) 
+             + (num_mult_val_saved*-1) +
+             + (num_add_vals_live_outside*3) > 0
+            )
+           )
+          {
+            all_reduced = 0;
+            for (v = bl->giv; v; v = v->next_iv)
+              {
+                if (v->giv_type == DEST_ADDR)
+                  {
+                    v->ignore = 1;
+                  }
+              }
+          }
+      }
+#endif /* SAVE_ON_REGS */
+
       /* Check each giv in this class to see if we will benefit by reducing
 	 it.  Skip giv's combined with others.  */
       for (v = bl->giv; v; v = v->next_iv)
@@ -3969,6 +4526,14 @@
 	 of the occurrences of the biv with a giv, but no harm was done in
 	 doing so in the rare cases where it can occur.  */
 
+      /* intel1 Retry compare elimination this time for loop trip test.  */
+      if (flag_compare_elim && !flag_unroll_loops 
+         && !done_compare_elimination && bl->retry_celim > 1 
+         && all_reduced == 1 && bl->eliminable)
+        {
+	  compare_elimination (bl, loop_start, loop_end, 
+                          compare_insn, jump_insn, 1);
+        } 
       if (all_reduced == 1 && bl->eliminable
 	  && maybe_eliminate_biv (bl, loop_start, end, 1,
 				  threshold, insn_count))
@@ -4020,6 +4585,19 @@
 	    fprintf (loop_dump_stream, "Reg %d: biv eliminated\n",
 		     bl->regno);
 	}
+      /* intel1 Retry compare elimination this time handling ashifhts. */
+      else if (flag_compare_elim && !flag_unroll_loops 
+               && !done_compare_elimination && bl->retry_celim == 1)
+        {
+	  if (compare_elimination (bl, loop_start, loop_end, 
+	                         compare_insn, jump_insn, 1))
+	    {
+    	      rtx tem = find_reg_note (bl->init_insn, REG_EQUAL, 0);
+	      if (tem)
+		XEXP (tem, 0) = SET_SRC (bl->init_set);
+ 	      bl->initial_value = SET_SRC (bl->init_set);;
+	    }
+        } 
     }
 
   /* Go through all the instructions in the loop, making all the
@@ -4101,6 +4679,8 @@
   register int i, j;
   register enum rtx_code code;
   register char *fmt;
+  /* intel1 */
+  rtx tx;
 
   if (x == 0)
     return;
@@ -4132,6 +4712,24 @@
 	benefit = general_induction_var (XEXP (x, 0),
 					 &src_reg, &add_val, &mult_val);
 
+	/* intel1
+	   For now lets strip off consty and try to recoginze the result
+	   as a possible mem_giv.  */
+#ifdef REWRITE_ADDRESS
+	if (flag_opt_reg_use
+	   && benefit == 0 && GET_CODE (XEXP (x, 0)) == PLUS 
+	   && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS 
+	   &&  (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 
+	    || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST 
+	    || GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF))
+	  {
+	    tx = x;
+	    x = XEXP (x, 0);
+	    benefit = general_induction_var (XEXP (x, 0),
+                                             &src_reg, &add_val, &mult_val);
+	  }
+#endif
+
 	/* Don't make a DEST_ADDR giv with mult_val == 1 && add_val == 0.
 	   Such a giv isn't useful.  */
 	if (benefit > 0 && (mult_val != const1_rtx || add_val != const0_rtx))
@@ -4140,6 +4738,25 @@
 	    struct induction *v
 	      = (struct induction *) oballoc (sizeof (struct induction));
 
+/* intel1 */
+#ifdef REDUCE_INDEX
+#ifdef REWRITE_ADDRESS
+#ifdef LEGITIMATE_INDEX_P
+	rtx * index_part;
+	/* try to eliminate index terms */		
+	if (REDUCE_INDEX && flag_reduce_index_givs
+	   && do_reduce_index (x, &add_val))
+	  { 
+	    index_part = &XEXP (XEXP (x, 0), 0);
+	    record_giv (v, insn, src_reg, addr_placeholder, mult_val,
+	               add_val, benefit, DEST_ADDR, not_every_iteration,
+	               index_part, loop_start, loop_end);
+	    v->is_index_induc = 1;
+	  }
+	else
+#endif
+#endif
+#endif
 	    record_giv (v, insn, src_reg, addr_placeholder, mult_val,
 			add_val, benefit, DEST_ADDR, not_every_iteration,
 			&XEXP (x, 0), loop_start, loop_end);
@@ -4227,6 +4844,8 @@
       bl->eliminable = 0;
       bl->nonneg = 0;
       bl->reversed = 0;
+      /* intel1 */
+      bl->retry_celim = 0;
       bl->total_benefit = 0;
 
       /* Add this class to loop_iv_list.  */
@@ -4310,6 +4929,10 @@
   v->ignore = 0;
   v->new_reg = 0;
   v->final_value = 0;
+  /* intel1 */
+#ifdef REDUCE_INDEX
+  v->is_index_induc = 0;
+#endif
 
   /* The v->always_computable field is used in update_giv_derive, to
      determine whether a giv can be used to derive another giv.  For a
@@ -4617,7 +5240,8 @@
 
 	      if (GET_CODE (p) == JUMP_INSN && JUMP_LABEL (p)
 		  && LABEL_NAME (JUMP_LABEL (p))
-		  && ((INSN_LUID (JUMP_LABEL (p)) < INSN_LUID (v->insn)
+		  && ( INSN_UID(v->insn)>=max_uid_for_loop /* intel1 */
+		      || (INSN_LUID (JUMP_LABEL (p)) < INSN_LUID (v->insn)
 		       && INSN_LUID (JUMP_LABEL (p)) > INSN_LUID (loop_start))
 		      || (INSN_LUID (JUMP_LABEL (p)) > INSN_LUID (last_giv_use)
 			  && INSN_LUID (JUMP_LABEL (p)) < INSN_LUID (loop_end))))
@@ -5440,9 +6064,26 @@
      the expression of G2 in terms of G1 can be used.  */
   if (g2->giv_type == DEST_ADDR
       && (tem = express_from (g1, g2)) != 0
+/* intel1 */
+#ifdef REDUCE_INDEX
+      && ((g2->is_index_induc && LEGITIMATE_INDEX_P(tem)) 
+           || (g2->is_index_induc == 0 && memory_address_p (g2->mem_mode, tem)
+           && ADDRESS_COST (tem) <= ADDRESS_COST (*g2->location))
+         )
+#else
       && memory_address_p (g2->mem_mode, tem)
-      && ADDRESS_COST (tem) <= ADDRESS_COST (*g2->location))
+      && ADDRESS_COST (tem) <= ADDRESS_COST (*g2->location)
+#endif
+     )
     {
+/* intel1 */
+#ifdef SAVE_ON_REGS
+      
+      if (flag_opt_reg_use && ADDRESS_COST (tem) != 1)
+      {
+        return(0);
+      }
+#endif
       g2->new_reg = tem;
       return 1;
     }
@@ -6234,6 +6875,15 @@
       for (v = bl->giv; v; v = v->next_iv)
 	if (v->giv_type == DEST_ADDR && v->location == &XEXP (x, 0))
 	  return 1;
+/* intel1 */
+#ifdef REDUCE_INDEX
+#ifdef LEGITIMATE_INDEX_P
+      for (v = bl->giv; v; v = v->next_iv)
+	if (REDUCE_INDEX && v->giv_type == DEST_ADDR && v->is_index_induc 
+	    && v->location == &XEXP (XEXP(x,0), 0))
+	  return 1;
+#endif
+#endif
       break;
     }
 
@@ -6588,4 +7238,6548 @@
 
   return gen_rtx (swap_condition (GET_CODE (comparison)), VOIDmode,
 		  XEXP (comparison, 1), XEXP (comparison, 0));
+}
+
+/* new code added by intel1 */
+struct new_rtx
+  {
+    rtx pat;
+    rtx insn;
+    rtx supplemental_pat;	/* Pattern that should be
+				   emited after this insn.  */
+    struct new_rtx *next;
+  };
+
+/* If bl is also the loop counter try to optimize out the
+   compare instruction by counting up to 0.  Return 1 if
+   successful.
+*/
+static
+int 
+compare_elimination (bl, loop_start, loop_end, compare_insn, jump_insn, second_time)
+     struct iv_class *bl;
+     rtx loop_start, loop_end, compare_insn, jump_insn;
+     int second_time;
+{
+  rtx insn, new_init_src, copy_of_jump, new_biv_set, loop_trip_reg;
+  int init_val, compare_val, i, adjust_val, desired_init_val;
+  int num_times_loop_execs, add_one, biv_init_to_const, biv_end_value;
+  int num_sups, compare_to_const;
+  struct new_rtx *new_rtx_element, *new_rtx_head, *new_rtx_tail;
+  char *storage;
+
+
+  if (GET_CODE (SET_DEST (bl->init_set)) != REG)
+    {
+      return (0);
+    }
+  if (!rtx_equal_p (SET_DEST (bl->init_set),
+		    XEXP (SET_SRC (PATTERN (compare_insn)), 0))
+    )
+    {
+      return (0);
+    }
+  copy_of_jump = copy_rtx (PATTERN (jump_insn));
+  PUT_CODE (XEXP (SET_SRC (copy_of_jump), 0), NE);
+  if (recog (copy_of_jump, jump_insn, 0) == -1)
+    {
+      return (0);
+    }
+  if (GET_CODE (XEXP (SET_SRC (PATTERN (compare_insn)), 1)) == CONST_INT)
+    {
+      if (bl->initial_test != NULL)
+	{
+	  return (0);
+	}
+      compare_val = INTVAL (XEXP (SET_SRC (PATTERN (compare_insn)), 1));
+      compare_to_const = 1;
+    }
+  else
+    {
+      compare_to_const = 0;
+      if (INTVAL (bl->biv->add_val) != 1)
+	{
+	  return (0);
+	}
+      else if (second_time == 0)
+	{
+	  bl->retry_celim = 2;	/* Signals that this is loop trip test
+	                           candidate.  */
+	  return (0);
+	}
+    }
+  if (GET_CODE (SET_SRC (bl->init_set)) != CONST_INT)
+    {
+      if (!compare_to_const)
+	{
+	  return (0);
+	}
+      else
+	{
+	  if (abs (INTVAL (bl->biv->add_val)) != 1)
+	    {
+	      return (0);
+	    }
+	  biv_init_to_const = 0;
+	  /* Just so checks on LE GE ... pass.  */
+	  init_val = compare_val - INTVAL (bl->biv->add_val);
+	}
+    }
+  else
+    {
+      init_val = INTVAL (SET_SRC (bl->init_set));
+      biv_init_to_const = 1;
+    }
+  insn = PREV_INSN (compare_insn);
+  while (GET_CODE (insn) == NOTE)
+    {
+      insn = PREV_INSN (insn);
+    }
+  if (!(GET_CODE (insn) == INSN 
+	&& rtx_equal_p (SET_DEST (PATTERN (insn)), SET_DEST (bl->init_set)) 
+	&& bl->biv->insn == insn))
+    {
+      return (0);
+    }
+  switch (GET_CODE (XEXP (SET_SRC (PATTERN (jump_insn)), 0)))
+    {
+    case LE:
+      if (compare_to_const 
+	  && (INTVAL (bl->biv->add_val) <= 0 || compare_val < init_val))
+	{
+	  return (0);
+	}
+      add_one = 1;
+      break;
+
+    case GE:
+      if (compare_to_const 
+	  && (INTVAL (bl->biv->add_val) >= 0 || compare_val > init_val))
+	{
+	  return (0);
+	}
+      add_one = 1;
+      break;
+
+    case LT:
+      if (compare_to_const 
+	  && (INTVAL (bl->biv->add_val) <= 0 || compare_val <= init_val))
+	{
+	  return (0);
+	}
+      add_one = 0;
+      break;
+
+    case GT:
+      if (compare_to_const 
+	  && (INTVAL (bl->biv->add_val) >= 0 || compare_val >= init_val))
+	{
+	  return (0);
+	}
+      add_one = 0;
+      break;
+
+    default:
+      return (0);
+    }
+  if (!compare_to_const)
+    { /* We are doing loop trip test.  */
+      if (n_times_set[REGNO (XEXP (SET_SRC (PATTERN (compare_insn)), 1))])
+	{
+	  return (0);
+	}
+      loop_trip_reg = gen_reg_rtx (GET_MODE (SET_DEST (bl->init_set)));
+      desired_init_val = (-1 * init_val) + add_one;
+      /* Emit insn to initialize loop trip reg.  */
+      if (desired_init_val)
+	{
+	  emit_insn_before (gen_rtx (SET, 0, loop_trip_reg,
+				     gen_rtx (PLUS, GET_MODE (loop_trip_reg),
+				 XEXP (SET_SRC (PATTERN (compare_insn)), 1),
+				 gen_rtx (CONST_INT, 0, desired_init_val))),
+			    loop_start);
+	}
+      else
+	{
+	  emit_insn_before (gen_rtx (SET, 0, loop_trip_reg,
+				XEXP (SET_SRC (PATTERN (compare_insn)), 1)),
+			    loop_start);
+	}
+      /* Emit insn to decrement loop trip reg.  */
+      emit_insn_before (gen_rtx (SET, 0, loop_trip_reg,
+				 gen_rtx (PLUS, GET_MODE (loop_trip_reg),
+					  loop_trip_reg,
+					  gen_rtx (CONST_INT, 0, -1))),
+			compare_insn);
+      /* Change comparison */
+      XEXP (SET_SRC (PATTERN (compare_insn)), 1) = const0_rtx;
+      XEXP (SET_SRC (PATTERN (compare_insn)), 0) = loop_trip_reg;
+      /* Change jump insn */
+      PUT_CODE (XEXP (SET_SRC (PATTERN (jump_insn)), 0), NE);
+      INSN_CODE (jump_insn) = recog (PATTERN (jump_insn), jump_insn, 0);
+      bl->retry_celim = 0;
+      return (1);
+    }
+  if (biv_init_to_const)
+    {
+      num_times_loop_execs
+	  = ((abs (compare_val - init_val) + add_one - 1) / abs (INTVAL (bl->biv->add_val))) + 1;
+      desired_init_val = -1 * num_times_loop_execs * INTVAL (bl->biv->add_val);
+      adjust_val = init_val - desired_init_val;
+      new_init_src = gen_rtx (CONST_INT, 0, desired_init_val);
+
+      biv_end_value = num_times_loop_execs * INTVAL (bl->biv->add_val) + init_val;
+
+    }
+  else
+    {/* biv is incremented by +-1 so the adjust_val is */
+      adjust_val 
+	  = (compare_val + (add_one * INTVAL (bl->biv->add_val)));
+      desired_init_val = -1 * adjust_val;
+      biv_end_value = compare_val + (add_one * INTVAL (bl->biv->add_val));
+      /* Make a check that we will be able to adjust the bivs init_val
+         by desired_init_val.  */
+      new_init_src = gen_rtx (PLUS, GET_MODE (SET_DEST (bl->init_set)),
+			      SET_SRC (bl->init_set),
+			      gen_rtx (CONST_INT, 0, desired_init_val));
+      new_biv_set = gen_rtx (SET, GET_MODE (SET_SRC (bl->init_set)),
+			     SET_DEST (bl->init_set), new_init_src);
+      if (recog (new_biv_set, bl->init_set, 0) == -1)
+	{
+	  return (0);
+	}
+    }
+  /* Now see if we can replace register bl->regno with
+     bl->regno+(adjust_val) in all insns from bl->init_insn to
+     loop_end.  
+     Signal that if we fail we should retry again at the end of
+     strength reduction.  */
+  if (second_time == 0)
+    {
+      bl->retry_celim = 1;
+    }
+  /* Mark our place on the obstack in case of failure.  */
+  storage = (char *) oballoc (0);
+  num_sups = 0;
+  new_rtx_head = new_rtx_tail = NULL;
+  insn = NEXT_INSN (bl->init_insn);
+  while (insn != compare_insn)
+    {
+      if (GET_CODE (insn) == INSN 
+	  && !rtx_equal_p (SET_DEST (PATTERN (insn)), SET_DEST (bl->init_set)))
+	{
+	  new_rtx_element = (struct new_rtx *) alloca (sizeof (struct new_rtx));
+	  new_rtx_element->insn = insn;
+	  new_rtx_element->supplemental_pat = NULL;
+	  if (!attempt_new_rtx (new_rtx_element, insn, bl, adjust_val, second_time))
+	    {
+	      obfree (storage);
+	      return (0);
+	    }
+	  else if (!rtx_equal_p (SET_SRC (insn), SET_SRC (new_rtx_element->pat)) 
+	    || !rtx_equal_p (SET_DEST (insn), SET_DEST (new_rtx_element->pat)))
+	    {
+	      if (new_rtx_head == NULL)
+		{
+		  new_rtx_head = new_rtx_element;
+		}
+	      else
+		{
+		  new_rtx_tail->next = new_rtx_element;
+		}
+	      new_rtx_tail = new_rtx_element;
+	      new_rtx_element->next = 0;
+	    }
+	  if (new_rtx_element->supplemental_pat)
+	    {
+	      num_sups++;
+	      if (num_sups > 3)
+		{ /* heuristic */
+		  obfree (storage);
+		  return (0);
+		}
+	    }
+	}
+      insn = NEXT_INSN (insn);
+    }
+  /* Replacement can be done now do it.  */
+  new_rtx_element = new_rtx_head;
+  while (new_rtx_element)
+    {
+      PATTERN (new_rtx_element->insn) = new_rtx_element->pat;
+      if (new_rtx_element->supplemental_pat)
+	{
+	  emit_insn_after (
+		gen_move_insn (SET_DEST (new_rtx_element->supplemental_pat),
+			       SET_SRC (new_rtx_element->supplemental_pat)),
+			    new_rtx_element->insn);
+	}
+      new_rtx_element = new_rtx_element->next;
+    }
+  /* Finally update the initialization and comparison of the biv.  */
+  PUT_CODE (XEXP (SET_SRC (PATTERN (jump_insn)), 0), NE);
+  INSN_CODE (jump_insn) = recog (PATTERN (jump_insn), jump_insn, 0);
+  XEXP (SET_SRC (PATTERN (compare_insn)), 1) = const0_rtx;
+  SET_SRC (bl->init_set) = new_init_src;
+  INSN_CODE (bl->init_insn) = recog ( PATTERN (bl->init_insn), bl->init_insn, 0);
+  emit_insn_after (gen_rtx (SET, GET_MODE (SET_DEST (bl->init_set)),
+			    SET_DEST (bl->init_set),
+			    gen_rtx (CONST_INT, 0, biv_end_value)),
+		   loop_end);
+  bl->retry_celim = 0;
+  return (1);
+
+}
+
+/* Try to rewrite insn replacing the biv with biv+biv_adjust_const.  if
+   the substitution is not immediately recognizable then try to
+   rewrite the insn to make it recognizable.  If try_supplemental is 1
+   then an additional insn may be generated to make the substitution
+   recognizable.  The generated pattern is pointed to by
+   new_rtx_element->pat.  
+*/
+static 
+attempt_new_rtx (new_rtx_element, insn, bl, biv_adjust_const, try_supplemental)
+     rtx insn;
+     struct new_rtx *new_rtx_element;
+     struct iv_class *bl;
+     int biv_adjust_const;
+     int try_supplemental;
+{
+  rtx new_src, new_dest, make_new_use (), try_to_make_good ();
+
+  new_src 
+     = make_new_use (SET_SRC (PATTERN (insn)), SET_DEST (bl->init_set),
+		  biv_adjust_const, insn);
+  new_dest 
+    = make_new_use (SET_DEST (PATTERN (insn)), SET_DEST (bl->init_set),
+		  biv_adjust_const, insn);
+  new_rtx_element->pat = gen_rtx (SET, 0, new_dest, new_src);
+  if (recog (new_rtx_element->pat, insn, 0) < 0)
+    {
+      try_to_make_good (SET_SRC (new_rtx_element->pat));
+      try_to_make_good (SET_DEST (new_rtx_element->pat));
+    }
+  if (recog (new_rtx_element->pat, insn, 0) < 0)
+    {
+      if (!try_supplemental)
+	{
+	  return (0);
+	}
+      if (GET_CODE (SET_DEST (new_rtx_element->pat)) == REG 
+	  && GET_CODE (SET_SRC (new_rtx_element->pat)) == ASHIFT 
+	  && GET_CODE (XEXP (SET_SRC (new_rtx_element->pat), 0)) == PLUS 
+	  && GET_CODE (XEXP (SET_SRC (new_rtx_element->pat), 1)) == CONST_INT 
+          && GET_CODE (XEXP (XEXP (SET_SRC (new_rtx_element->pat), 0), 0)) == REG 
+	  && GET_CODE (XEXP (XEXP (SET_SRC (new_rtx_element->pat), 0), 1)) == CONST_INT
+	)
+	{
+	  /* try to rewrite:
+           (set (reg:SI x)
+              (ashift:SI (plus:SI (reg/v:SI y)
+                                  (const_int a))
+                         (const_int b)))
+
+           into two patterns:
+           (set (reg:SI x)
+              (ashift:SI (reg/v:SI y)
+                         (const_int b)))
+
+           (set (reg:SI x)
+              (plus:SI (reg/v:SI x)
+                       (const_int a*(2**b))))
+        */
+	  int add_val;
+	  add_val 
+	    = two_to_power (INTVAL (XEXP (SET_SRC (new_rtx_element->pat), 1))) 
+	      * INTVAL (XEXP (XEXP (SET_SRC (new_rtx_element->pat), 0), 1));
+	  new_rtx_element->pat = PATTERN (new_rtx_element->insn);
+	  new_rtx_element->supplemental_pat 
+	    = gen_rtx (SET, GET_MODE (SET_DEST (new_rtx_element->pat)),
+		     SET_DEST (new_rtx_element->pat),
+	  gen_rtx (PLUS, GET_MODE (XEXP (SET_SRC (new_rtx_element->pat), 0)),
+		   SET_DEST (new_rtx_element->pat),
+		   gen_rtx (CONST_INT, 0, add_val)));
+	}
+      else if (GET_CODE (SET_DEST (new_rtx_element->pat)) == REG 
+	       && GET_CODE (SET_SRC (new_rtx_element->pat)) == PLUS 
+	       && GET_CODE (XEXP (SET_SRC (new_rtx_element->pat), 0)) == REG 
+	       && GET_CODE (XEXP (SET_SRC (new_rtx_element->pat), 1)) == PLUS 
+	       && GET_CODE (XEXP (XEXP (SET_SRC (new_rtx_element->pat), 1), 0)) == REG 
+	       && GET_CODE (XEXP (XEXP (SET_SRC (new_rtx_element->pat), 1), 1)) == CONST_INT
+	)
+	{
+	  /* try to rewrite:
+           (set (reg:SI x)
+                (plus:SI (reg:SI y)
+                          (plus:SI   (reg:SI z)
+                                     (const_int a))))
+
+           into two patterns:
+           (set (reg:SI x)
+              (plus:SI (reg/v:SI y)
+                       (reg/v:SI z)))
+
+           (set (reg:SI x)
+              (plus:SI (reg/v:SI x)
+                       (const_int a)))
+        */
+	  new_rtx_element->supplemental_pat 
+	    = gen_rtx (SET, GET_MODE (SET_DEST (new_rtx_element->pat)),
+		     SET_DEST (new_rtx_element->pat),
+	  gen_rtx (PLUS, GET_MODE (XEXP (SET_SRC (new_rtx_element->pat), 0)),
+		   SET_DEST (new_rtx_element->pat),
+		   XEXP (XEXP (SET_SRC (new_rtx_element->pat), 1), 1)));
+	  new_rtx_element->pat = PATTERN (new_rtx_element->insn);
+	}
+      else
+	{
+	  return (0);
+	}
+      if (recog (new_rtx_element->supplemental_pat, insn, 0) < 0)
+	{
+	  return (0);
+	}
+    }
+  return (1);
+}
+
+
+/* Generate a new rtx which is a copy of orig with each occurence of
+   biv_reg replaced by biv_reg+biv_adjust_const.  
+*/
+static rtx
+make_new_use (orig, biv_reg, biv_adjust_const, insn)
+     register rtx orig, biv_reg;
+     rtx insn;
+     int biv_adjust_const;
+{
+  register rtx copy;
+  rtx non_biv_operand, ret_rtx;
+  register int i, j;
+  register RTX_CODE code;
+  register char *format_ptr;
+
+  code = GET_CODE (orig);
+
+  switch (code)
+    {
+    case REG:
+      if (rtx_equal_p (orig, biv_reg))
+	{
+	  ret_rtx 
+	    = gen_rtx (PLUS, GET_MODE (orig), orig,
+		     gen_rtx (CONST_INT, 0, biv_adjust_const));
+	  return (ret_rtx);
+	}
+      else
+	{
+	  return (orig);
+	}
+      break;
+
+    case PLUS:
+    case MINUS:
+      if (GET_CODE (XEXP (orig, 0)) == REG && GET_CODE (XEXP (orig, 1)) == CONST_INT 
+	  && rtx_equal_p (XEXP (orig, 0), biv_reg))
+	{ /* Ajdust the const_int part by biv_adjust_const.  */
+	  if (GET_CODE (orig) == PLUS)
+	    {
+	      non_biv_operand 
+		   = gen_rtx (CONST_INT, 0,
+			 INTVAL (XEXP (orig, 1)) + biv_adjust_const);
+	    }
+	  else
+	    {
+	      non_biv_operand 
+		= gen_rtx (CONST_INT, 0,
+			 INTVAL (XEXP (orig, 1)) - biv_adjust_const);
+	    }
+	  ret_rtx = gen_rtx (code, GET_MODE (orig), XEXP (orig, 0), non_biv_operand);
+	  return (ret_rtx);
+	}
+      else
+	/* commutativity */ 
+	if (GET_CODE (XEXP (orig, 1)) == REG && GET_CODE (XEXP (orig, 0)) == CONST_INT 
+	    && rtx_equal_p (XEXP (orig, 1), biv_reg))
+	{/* Ajdust the const_int part by biv_adjust_const.  */
+	  if (GET_CODE (orig) == PLUS)
+	    {
+	      non_biv_operand 
+		= gen_rtx (CONST_INT, 0,
+			 INTVAL (XEXP (orig, 0)) + biv_adjust_const);
+	    }
+	  else
+	    {
+	      non_biv_operand 
+		= gen_rtx (CONST_INT, 0,
+			 INTVAL (XEXP (orig, 0)) - biv_adjust_const);
+	    }
+	  ret_rtx = gen_rtx (code, GET_MODE (orig), non_biv_operand, XEXP (orig, 1));
+	  return (ret_rtx);
+	}
+      break;
+
+    case QUEUED:
+    case CONST_INT:
+    case CONST_DOUBLE:
+    case SYMBOL_REF:
+    case CODE_LABEL:
+    case PC:
+    case CC0:
+      return orig;
+    }
+
+  copy = rtx_alloc (code);
+  PUT_MODE (copy, GET_MODE (orig));
+  copy->in_struct = orig->in_struct;
+  copy->volatil = orig->volatil;
+  copy->unchanging = orig->unchanging;
+  copy->integrated = orig->integrated;
+
+  format_ptr = GET_RTX_FORMAT (GET_CODE (copy));
+
+  for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++)
+    {
+      switch (*format_ptr++)
+	{
+	case 'e':
+	  XEXP (copy, i) = XEXP (orig, i);
+	  if (XEXP (orig, i) != NULL)
+	    XEXP (copy, i) 
+	      = make_new_use (XEXP (orig, i), biv_reg,
+			    biv_adjust_const, insn);
+	  break;
+
+	case 'E':
+	case 'V':
+	  XVEC (copy, i) = XVEC (orig, i);
+	  if (XVEC (orig, i) != NULL)
+	    {
+	      XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i));
+	      for (j = 0; j < XVECLEN (copy, i); j++)
+		XVECEXP (copy, i, j) 
+		  = make_new_use (XVECEXP (orig, i, j), biv_reg,
+				biv_adjust_const, insn);
+	    }
+	  break;
+
+	default:
+	  XINT (copy, i) = XINT (orig, i);
+	  break;
+	}
+    }
+  return copy;
+}
+
+/* Try to put orig into a form that is recognizable using rewrite_address
+   on the relevant portion of orig.  
+*/
+rtx
+try_to_make_good (orig)
+     register rtx orig;
+{
+  void rewrite_address ();
+  register int i, j;
+  register RTX_CODE code;
+  register char *fmt;
+
+  code = GET_CODE (orig);
+
+  switch (code)
+    {
+    case REG:
+    case QUEUED:
+    case CONST_INT:
+    case CONST_DOUBLE:
+    case SYMBOL_REF:
+    case CODE_LABEL:
+    case PC:
+    case CC0:
+      return orig;
+
+    case MEM:
+      GO_IF_LEGITIMATE_ADDRESS (GET_MODE (orig), orig, memok);
+#ifdef REWRITE_ADDRESS
+      REWRITE_ADDRESS (orig);
+#endif
+    memok:
+      return (orig);
+    }
+
+
+  fmt = GET_RTX_FORMAT (code);
+
+  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+    if (fmt[i] == 'e')
+      XEXP (orig, i) = try_to_make_good (XEXP (orig, i));
+    else if (fmt[i] == 'E' || fmt[i] == 'V')
+      {
+	for (j = 0; j < XVECLEN (orig, i); j++)
+	  XVECEXP (orig, i, j) 
+	    = try_to_make_good (XVECEXP (orig, i, j));
+      }
+  return orig;
+}
+
+
+/* Check to see if compare elimination is possible for this loop.  
+   Return 1 if yes and set up *compare_insn to point to the compare
+   at the end of the loop and *jump_insn to point to the jump back
+   to the beginning of the loop.  
+*/
+static int
+possible_compare_elimination (loop_start, loop_end, compare_insn, jump_insn, try_compare_elimination)
+     rtx loop_end, loop_start, *compare_insn, *jump_insn;
+     int *try_compare_elimination;
+{
+  rtx insn;
+  int i;
+  insn = loop_start;
+  i = 0;
+  *try_compare_elimination = 0;
+  while (insn && insn != loop_end)
+    {
+      if (GET_CODE (insn) == CALL_INSN)
+	{
+	  insn = NULL;
+	}
+      else if (GET_CODE (insn) == INSN)
+	{
+	  i++;
+	  if (i > MAX_CMP_ELIM)
+	    {
+	      insn = NULL;
+	    }
+	  else if (GET_CODE (PATTERN (insn)) != SET)
+	    {
+	      insn = NULL;
+	    }
+	}
+      if (insn)
+	insn = NEXT_INSN (insn);
+    }
+  if (insn != NULL)
+    {
+      *try_compare_elimination = 1;
+    }
+  /* Look for compare jcc on this biv at the end of the loop.  */
+  insn = PREV_INSN (loop_end);
+  if (!(GET_CODE (insn) == JUMP_INSN 
+	&& GET_CODE (PATTERN (insn)) == SET 
+	&& SET_DEST (PATTERN (insn)) == pc_rtx 
+	&& GET_CODE (SET_SRC (PATTERN (insn))) == IF_THEN_ELSE 
+	&& XEXP (XEXP (SET_SRC (PATTERN (insn)), 0), 0) == cc0_rtx 
+	&& XEXP (XEXP (SET_SRC (PATTERN (insn)), 0), 1) == const0_rtx))
+    {
+      *try_compare_elimination = 0;
+    }
+  *jump_insn = insn;
+  insn = PREV_INSN (insn);
+  if (!(GET_CODE (insn) == INSN 
+	&& GET_CODE (PATTERN (insn)) == SET 
+	&& SET_DEST (PATTERN (insn)) == cc0_rtx 
+	&& GET_CODE (SET_SRC (PATTERN (insn))) == COMPARE 
+	&& (GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == CONST_INT 
+	    || GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == REG) 
+	&& GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == REG))
+    {
+      *try_compare_elimination = 0;
+    }
+  *compare_insn = insn;
+}
+
+struct regs_mentioned
+  {
+    rtx reg;				/* The register.  */
+    int in_mem;				/* Is 1 if register is part of
+    					   a MEM_REF.  */
+    struct regs_mentioned *next;
+  };
+   
+static struct regs_mentioned *giv_reg_header = NULL, *use_reg_header = NULL;
+
+/* Build a linked list of (struct regs_mentioned) describing the
+   registers used in the pattern pat.  The head of the linked list
+   to place them on is a_header.  If in_mem is 1 this means that
+   pat is subexpression of a MEM_REF.  
+*/
+static void
+find_regs_mentioned (pat, a_header, in_mem)
+     rtx pat;
+     struct regs_mentioned **a_header;
+     int in_mem;
+{
+  register char *fmt;
+  register int i;
+  register enum rtx_code code;
+  struct regs_mentioned *one_reg;
+
+  code = GET_CODE (pat);
+
+  switch (code)
+    {
+    case REG:
+      if (REGNO (pat) < FIRST_PSEUDO_REGISTER)
+	{
+	  return;
+	}
+      one_reg = (struct regs_mentioned *)
+	obstack_alloc (&momentary_obstack, sizeof (struct regs_mentioned));
+      one_reg->reg = pat;
+      one_reg->in_mem = in_mem;
+      one_reg->next = *a_header;
+      *a_header = one_reg;
+      return;
+
+      /* These codes have no constituent expressions
+	 and are unique.  */
+    case SCRATCH:
+    case CC0:
+    case PC:
+    case QUEUED:
+    case CONST_INT:
+    case CONST_DOUBLE:
+    case SYMBOL_REF:
+    case CODE_LABEL:
+      return;
+
+    case MEM:
+      in_mem = 1;
+      break;
+
+    }
+
+
+  fmt = GET_RTX_FORMAT (code);
+
+  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+    {
+      if (fmt[i] == 'E')
+	{
+	  register int j;
+	  for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
+	    find_regs_mentioned (XVECEXP (pat, i, j), a_header, in_mem);
+	}
+      else if (fmt[i] == 'e')
+	find_regs_mentioned (XEXP (pat, i), a_header, in_mem);
+    }
+}
+
+#ifdef REDUCE_INDEX
+/* Create givs which are only index terms of memory addresses.  */
+static int
+do_reduce_index (x, add_val)
+     rtx x, *add_val;
+{
+  rtx mem_address, sym_part, constint_part, save_add_val;
+  save_add_val = *add_val;
+  mem_address = XEXP (x, 0);
+  if (GET_CODE (mem_address) != PLUS)
+    {
+      return (0);
+    }
+  if (GET_CODE (XEXP (mem_address, 0)) == MULT)
+    {
+      if (!LEGITIMATE_INDEX_P (XEXP (mem_address, 0)) 
+	  || GET_CODE (XEXP (mem_address, 1)) == REG	
+	)
+	{ /* Will have index term anyway.  */
+	  return (0);
+	}
+    }
+  else
+    {
+      return (0);
+    }
+  /* Strip from *(add_val) the non index part.  */
+  if (rtx_equal_p (*(add_val), XEXP (mem_address, 1)))
+    {
+      *(add_val) = const0_rtx;
+    }
+  else if (GET_CODE (*(add_val)) == CONST_INT)
+    {
+      if (GET_CODE (XEXP (mem_address, 1)) != CONST_INT)
+	{
+	  return (0);
+	}
+      else
+	{
+	  *(add_val) 
+	    = gen_rtx (CONST_INT, 0,
+		      INTVAL (*(add_val)) - INTVAL (XEXP (mem_address, 1)));
+	}
+    }
+  else if (GET_CODE (*(add_val)) == CONST)
+    {
+      if (!(GET_CODE (XEXP (*(add_val), 0)) == PLUS 
+	    && GET_CODE (XEXP (XEXP (*(add_val), 0), 0)) == SYMBOL_REF 
+	    && GET_CODE (XEXP (XEXP (*(add_val), 0), 1)) == CONST_INT)
+	)
+	{
+	  return (0);
+	}
+      *(add_val) = XEXP (*(add_val), 0);
+      mem_address = XEXP (mem_address, 1);
+      if (GET_CODE (mem_address) == CONST)
+	{
+	  mem_address = XEXP (mem_address, 0);
+	}
+      if (GET_CODE (mem_address) == PLUS)
+	{
+	  sym_part = XEXP (mem_address, 0);
+	  constint_part = XEXP (mem_address, 1);
+	}
+      else
+	{
+	  sym_part = mem_address;
+	  constint_part = const0_rtx;
+	}
+      if (!rtx_equal_p (XEXP (*(add_val), 0), sym_part))
+	{
+	  *(add_val) = save_add_val;
+	  return (0);
+	}
+      else
+	{
+	  *(add_val) = XEXP (*(add_val), 1);
+	  *(add_val) 
+	    = gen_rtx (CONST_INT, 0, INTVAL (*(add_val)) - INTVAL (constint_part));
+	}
+    }
+  else
+    {
+      return (0);
+    }
+  return (1);
+}
+
+#endif
+
+struct regopt_info
+{
+  rtx insn_set;		/* The insn that loads the current value in the register */
+  rtx corresp_mem;	/* The memory that contains the same value as the register */
+  rtx reg; 		/* The register */
+  char replace_reg;	/* If 1 replace reg with corresp_mem (for stack regs)
+			   otherwise replace corresp_mem with reg */
+  char do_replace;	/* If 1 then this is a stack reg that has already
+			   been used in this extended basic block -
+			   try to replace susequent uses with this regs
+			   corresponding mem */
+};
+static struct regopt_info *rinfo;
+struct undo
+{
+  rtx *where;
+  rtx old_contents;
+  int is_int;
+};
+
+#define MAX_UNDO 50
+
+struct undobuf
+{
+  int num_undo;
+  char *storage;
+  struct undo undo[MAX_UNDO];
+  rtx other_insn;
+};
+
+static struct undobuf undobuf;
+#define LOOP_SUBST(WHERE, NEWVAL)  \
+ do { if (undobuf.num_undo < MAX_UNDO)					\
+	{								\
+	  undobuf.undo[undobuf.num_undo].where = WHERE;			\
+	  undobuf.undo[undobuf.num_undo].old_contents = *WHERE;		\
+	  undobuf.undo[undobuf.num_undo].is_int = 0;			\
+	  *WHERE = NEWVAL;						\
+	  undobuf.num_undo++;						\
+	}								\
+    } while (0)
+
+
+static int mem_max_reg_num;
+#define SYMREF_PLUS_REG(insn)						\
+     (GET_CODE (SET_SRC (PATTERN (insn))) == PLUS &&			\
+     GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == REG && 		\
+     GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == SYMBOL_REF)
+
+/*  Try to replace a register use with the value that sets that the
+    register.  This is done for the following cases:
+    1) regx <- regy ashift const_int
+    2) regx <- symbol_ref + regy
+    3) regx <- (regy * const_int) + const_int
+
+    If only_symref_plus_reg==1 then regx is replaced only if it
+    used as a base or index register and is of type 2)
+    otherwise it is always replaced.  
+
+    Calling use_regs_source with only_symref_plus_reg==0 on a loop
+    before strength reduction causes strength reduction to better handle
+    mem givs.  
+
+    Calling use_regs_source with only_symref_plus_reg==1 at the end of
+    loop optimization will do the replacement even if combine would not.  
+
+    also if only_symref_plus_reg==1 and if we have
+    1) mem1 <- regx
+    then attempt to replace susequent uses of mem1 with regx
+
+
+*/
+
+static
+void 
+use_regs_source (start, end, only_symref_plus_reg)
+     rtx start, end;
+     int only_symref_plus_reg;
+{
+  rtx insn, src, new_src, dest, tinsn, tmp_rtx;
+  struct regs_mentioned *header, *a_reg_used;
+  int recog_ok, i, insn_code_num, nested;
+  char *storage1, *storage2;
+  int cur_max_reg = max_reg_num () + 1;
+  mem_max_reg_num = cur_max_reg;
+
+  undobuf.num_undo = 0;
+  rinfo 
+    = (struct regopt_info *) alloca (cur_max_reg * sizeof (struct regopt_info));
+  bzero (rinfo, cur_max_reg * sizeof (struct regopt_info));
+
+  nested = 0;
+  insn = NEXT_INSN (start);
+  while (insn != end)
+    {
+      switch (GET_CODE (insn))
+	{
+
+	case NOTE:
+	  if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG 
+	      && only_symref_plus_reg)
+	    {
+	      nested++;
+	      bzero (rinfo, cur_max_reg * sizeof (struct regopt_info));
+	    }
+	  if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END 
+	      && only_symref_plus_reg)
+	    {
+	      nested--;
+	      bzero (rinfo, cur_max_reg * sizeof (struct regopt_info));
+	    }
+	  break;
+
+	case JUMP_INSN:
+	  if (nested == 0 || !only_symref_plus_reg)
+	    {
+	      if (SET_DEST (PATTERN (insn)) == pc_rtx
+		  && GET_CODE (SET_SRC (PATTERN (insn))) == LABEL_REF)
+		{
+		  bzero (rinfo, cur_max_reg * sizeof (struct regopt_info));
+		}
+	      else if (!only_symref_plus_reg)
+		{
+		  for (i = 0; i < cur_max_reg; i++)
+		    {
+		      rinfo[i].corresp_mem = NULL;
+		    }
+		}
+	    }
+	  break;
+
+	case CALL_INSN:
+	  if (nested == 0 || !only_symref_plus_reg)
+	    {
+	      bzero (rinfo, cur_max_reg * sizeof (struct regopt_info));
+	    }
+	  break;
+
+	case CODE_LABEL:
+	case BARRIER:
+	  if (nested == 0 || !only_symref_plus_reg)
+	    {
+	      /* Forget everything */
+	      bzero (rinfo, cur_max_reg * sizeof (struct regopt_info));
+	    }
+	  break;
+
+	case INSN:
+	  if (!(nested == 0 || !only_symref_plus_reg))
+	    break;
+          if (GET_CODE (PATTERN (insn)) == CLOBBER)
+            {
+              dest = SET_DEST (PATTERN (insn));
+	      if (GET_CODE (dest) == REG)
+		{
+		  rinfo[ REGNO (dest)].insn_set = NULL;
+		  for (i = 0; i < cur_max_reg; i++)
+		    {
+		      if (rinfo[i].insn_set
+			  && reg_overlap_mentioned_p (dest, 
+			        SET_SRC (PATTERN (rinfo[i].insn_set)))
+			)
+			{ /* current value of reg dest overwritten */
+			  rinfo[i].insn_set = NULL;
+		          if (rinfo[i].corresp_mem 
+		              && reg_overlap_mentioned_p (dest, 
+		                   rinfo[i].corresp_mem))
+			    { /* Not the same memory address anymore.  */
+			      rinfo[i].corresp_mem = NULL;
+			    }
+			}
+		    }
+		}
+	      else if (GET_CODE (dest) == MEM && !only_symref_plus_reg 
+		       && flag_replace_mem)
+		{
+		  for (i = 0; i < cur_max_reg; i++)
+		    {
+		      if (rinfo[i].corresp_mem 
+			  && true_dependence (dest, rinfo[i].corresp_mem))
+			{ /* Memory address maybe overwritten.  */
+			  rinfo[i].corresp_mem = NULL;
+			}
+		    }
+		}
+            }
+	  else if (GET_CODE (PATTERN (insn)) == PARALLEL)
+	    {
+	      for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
+		{
+		  rtx cur_rtx;
+		  cur_rtx = XVECEXP (PATTERN (insn), 0, i);
+		  if ((GET_CODE (cur_rtx) == SET || GET_CODE (cur_rtx) == CLOBBER)
+		      && GET_CODE (SET_DEST (cur_rtx)) == REG)
+		    {
+		      rinfo[ REGNO (SET_DEST (cur_rtx))].insn_set = NULL;
+		      for (i = 0; i < cur_max_reg; i++)
+		        {
+		          if (rinfo[i].insn_set
+			      && reg_overlap_mentioned_p (SET_DEST (cur_rtx), 
+			             SET_SRC (PATTERN (rinfo[i].insn_set)))
+			    )
+			    { /* Current value of reg dest overwritten */
+			      rinfo[i].insn_set = NULL;
+			    }
+		          if (rinfo[i].corresp_mem 
+		              && reg_overlap_mentioned_p (SET_DEST (cur_rtx), 
+		                   rinfo[i].corresp_mem))
+			    { /* Not the same memory address anymore.  */
+			      rinfo[i].corresp_mem = NULL;
+			    }
+		        }
+		    }
+	          else if ((GET_CODE (cur_rtx) == SET || GET_CODE (cur_rtx) == CLOBBER)
+		          && GET_CODE (SET_DEST (cur_rtx)) == MEM
+	                  && GET_CODE (dest) == MEM && !only_symref_plus_reg 
+		          && flag_replace_mem)
+		    {
+		      dest = SET_DEST (cur_rtx);
+		      for (i = 0; i < cur_max_reg; i++)
+		        {
+		          if (rinfo[i].corresp_mem 
+			      && true_dependence (dest, rinfo[i].corresp_mem))
+			    { /* Memory address maybe overwritten.  */
+			      rinfo[i].corresp_mem = NULL;
+			    }
+		        }
+		    }
+		  else if (!(GET_CODE (cur_rtx) == SET  
+		       || GET_CODE (cur_rtx) == CLOBBER
+		       || GET_CODE (cur_rtx) == USE))
+	            bzero (rinfo, cur_max_reg * sizeof (struct regopt_info));
+		}
+	    }
+	  else if (GET_CODE (PATTERN (insn)) == SET)
+	    {
+	      dest = SET_DEST (PATTERN (insn));
+	      if (GET_CODE (SET_SRC (PATTERN (insn))) != REG)
+		{
+		  header = NULL;
+		  storage2 = (char *) obstack_alloc (&momentary_obstack, 0);
+		  find_regs_mentioned (SET_SRC (PATTERN (insn)), &header, 0);
+		  a_reg_used = header;
+		  while (a_reg_used)
+		    {
+		      undobuf.num_undo = 0;
+		      undobuf.storage = (char *) oballoc (0);
+		      if (((a_reg_used->in_mem || !only_symref_plus_reg) 
+			   && rinfo[REGNO (a_reg_used->reg)].insn_set 
+			   && rinfo[REGNO (a_reg_used->reg)].replace_reg == 0 
+			   && (!only_symref_plus_reg 
+			       || SYMREF_PLUS_REG (rinfo[REGNO (a_reg_used->reg)].insn_set))) 
+			  || (rinfo[REGNO (a_reg_used->reg)].corresp_mem 
+			   && rinfo[REGNO (a_reg_used->reg)].insn_set 
+			   && rinfo[REGNO (a_reg_used->reg)].replace_reg == 1 
+			   && rinfo[REGNO (a_reg_used->reg)].do_replace == 1 
+#ifdef STACK_REGS
+#ifdef IS_STACK_MODE
+			  && !((GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT_EXTEND 
+		      || GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT_TRUNCATE)
+		      && (IS_STACK_MODE (SFmode) || IS_STACK_MODE (DFmode)))
+			   
+#endif
+#endif
+			   && !only_symref_plus_reg && flag_replace_stack_mem)
+			)
+			{ /* Try to replace the register with it's current
+		              value.  */
+			  replace_reg (SET_SRC (PATTERN (insn)),
+				       &SET_SRC (PATTERN (insn)),
+				       a_reg_used->reg,
+				       &(rinfo[REGNO (a_reg_used->reg)]));
+			  if ((insn_code_num = recog (PATTERN (insn), insn, 0)) < 0)
+			    {
+			      recog_ok = 0;
+			      try_to_make_good (SET_SRC (PATTERN (insn)));
+			    }
+			  else
+			    {
+			      recog_ok = 1;
+			    }
+			  if (recog_ok 
+			      || (insn_code_num = recog (PATTERN (insn), insn, 0)) >= 0)
+			    {
+			      INSN_CODE (insn) = insn_code_num;
+			      /* canonicalize */
+			      if (GET_CODE (SET_SRC (PATTERN (insn))) == PLUS 
+				  && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == MULT 
+				  && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == REG)
+				{
+				  tmp_rtx = XEXP (SET_SRC (PATTERN (insn)), 0);
+				  XEXP (SET_SRC (PATTERN (insn)), 0) 
+				    = XEXP (SET_SRC (PATTERN (insn)), 1);
+				  XEXP (SET_SRC (PATTERN (insn)), 1) = tmp_rtx;
+				}
+			    }
+			  else
+			    {
+			      loop_undo_all ();
+			    }
+			}
+#ifdef STACK_REGS
+#ifdef IS_STACK_MODE
+		      if (IS_STACK_MODE (GET_MODE (a_reg_used->reg)))
+			{
+			  rinfo[REGNO (a_reg_used->reg)].do_replace = 1;
+			}
+#endif
+#endif
+		      a_reg_used = a_reg_used->next;
+		    }
+		  if (header != NULL)
+		    {
+		      obstack_free (&momentary_obstack, storage2);
+		    }
+		  if (!only_symref_plus_reg && flag_replace_mem)
+		    replace_mems (insn, SET_SRC (PATTERN (insn)));
+		}
+	      src = SET_SRC (PATTERN (insn));
+	      if (GET_CODE (dest) != REG)
+		{
+		  header = NULL;
+		  storage2 = (char *) obstack_alloc (&momentary_obstack, 0);
+		  find_regs_mentioned (SET_DEST (PATTERN (insn)), &header, 0);
+		  a_reg_used = header;
+		  while (a_reg_used)
+		    {
+		      undobuf.num_undo = 0;
+		      undobuf.storage = (char *) oballoc (0);
+		      if (a_reg_used->in_mem 
+			  && rinfo[REGNO (a_reg_used->reg)].insn_set 
+			  && (!only_symref_plus_reg 
+			   || SYMREF_PLUS_REG (rinfo[REGNO (a_reg_used->reg)].insn_set))
+			)
+			{ /* Try to replace the register with it's current
+		             value.  */
+			  replace_reg (SET_DEST (PATTERN (insn)),
+				       &SET_DEST (PATTERN (insn)),
+				       a_reg_used->reg,
+				       &(rinfo[REGNO (a_reg_used->reg)]));
+
+			  if (recog (PATTERN (insn), insn, 0) < 0)
+			    {
+			      recog_ok = 0;
+			      try_to_make_good (SET_DEST (PATTERN (insn)));
+			    }
+			  else
+			    {
+			      recog_ok = 1;
+			    }
+			  if (recog_ok 
+			      || recog (PATTERN (insn), insn, 0) >= 0)
+			    {
+			      ;
+			    }
+			  else
+			    {
+			      loop_undo_all ();
+			    }
+			}
+		      a_reg_used = a_reg_used->next;
+		    }
+		  if (header != NULL)
+		    {
+		      obstack_free (&momentary_obstack, storage2);
+		    }
+		  if (!only_symref_plus_reg 
+		      && GET_CODE (src) == REG && GET_CODE (dest) == MEM 
+		      && !MEM_VOLATILE_P (dest) 
+		      && GET_CODE (XEXP (dest, 0)) != PRE_DEC 
+		      && GET_CODE (XEXP (dest, 0)) != PRE_INC
+#ifdef STACK_REGS
+#ifdef IS_STACK_MODE
+		      && !(IS_STACK_MODE (GET_MODE (src)))
+#endif
+#endif
+		    )
+		    {
+		      rinfo[REGNO (src)].corresp_mem = dest;
+		      rinfo[REGNO (src)].reg = src;
+		      rinfo[REGNO (src)].replace_reg = 0;
+		    }
+		}
+	      if (GET_CODE (dest) == MEM && !only_symref_plus_reg 
+		  && flag_replace_mem)
+		{
+		  for (i = 0; i < cur_max_reg; i++)
+		    {
+		      if (rinfo[i].corresp_mem && !(GET_CODE (src) == REG && i == REGNO (src)) 
+			  && true_dependence (dest, rinfo[i].corresp_mem))
+			{ /* Memory address maybe overwritten.  */
+			  rinfo[i].corresp_mem = NULL;
+			}
+		    }
+		}
+	      if (GET_CODE (dest) == REG)
+		{
+		  for (i = 0; i < cur_max_reg; i++)
+		    {
+		      if (rinfo[i].insn_set 
+			  && reg_overlap_mentioned_p (dest, SET_SRC (PATTERN (rinfo[i].insn_set)))
+			)
+			{ /* Current value of reg dest overwritten.  */
+			  rinfo[i].insn_set = NULL;
+			}
+		      if (rinfo[i].corresp_mem 
+		          && reg_overlap_mentioned_p (dest, rinfo[i].corresp_mem))
+			{ /* Not the same memory address anymore.  */
+			  rinfo[i].corresp_mem = NULL;
+			}
+		    }
+		  rinfo[REGNO (dest)].corresp_mem = NULL;
+		  if (reg_overlap_mentioned_p (dest, SET_SRC (PATTERN (insn))))
+		    {
+		      rinfo[REGNO (dest)].insn_set = NULL;
+		    }
+		  else
+		    {
+		      if ((GET_CODE (SET_SRC (PATTERN (insn))) == ASHIFT 
+		           && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == REG 
+			   && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == CONST_INT) 
+			   || (GET_CODE (SET_SRC (PATTERN (insn))) == PLUS 
+		               && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == REG 
+			       && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == SYMBOL_REF) 
+			   || (GET_CODE (SET_SRC (PATTERN (insn))) == PLUS 
+			       && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == MULT 
+			       && GET_CODE (XEXP (XEXP (SET_SRC (PATTERN (insn)), 0), 0)) == REG 
+			       && GET_CODE (XEXP (XEXP (SET_SRC (PATTERN (insn)), 0), 1)) == CONST_INT 
+			       && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == CONST_INT)
+			)
+			{ /* These are the patterns of interest.  */
+			  rinfo[REGNO (dest)].insn_set = insn;
+			}
+		      else
+			{
+			  rinfo[REGNO (dest)].insn_set = NULL;
+			}
+#ifdef STACK_REGS
+#ifdef IS_STACK_MODE
+		      if (IS_STACK_MODE (GET_MODE (dest)) 
+			      && ((GET_CODE (src) == MEM 
+			           && !MEM_VOLATILE_P (src)) 
+		               || ((IS_STACK_MODE (SFmode) || IS_STACK_MODE (DFmode)) 
+		                    && (GET_CODE (src) == FLOAT_EXTEND 
+			                    || GET_CODE (src) == FLOAT_TRUNCATE) 
+		          && GET_CODE (XEXP (src, 0)) == MEM 
+		          && !MEM_VOLATILE_P (XEXP (src, 0))))
+		          && flag_replace_stack_mem)
+			{
+			  rinfo[REGNO (dest)].corresp_mem = src;
+			  rinfo[REGNO (dest)].reg = dest;
+			  rinfo[REGNO (dest)].insn_set = insn;
+			  rinfo[REGNO (dest)].replace_reg = 1;
+			  rinfo[REGNO (dest)].do_replace = 0;
+			}
+#endif
+#endif
+		    }
+		}
+	    }
+	  else if (GET_CODE (PATTERN (insn)) != USE)
+	    {
+	      bzero (rinfo, cur_max_reg * sizeof (struct regopt_info));
+	    }
+	  break;
+
+	default:
+	  bzero (rinfo, cur_max_reg * sizeof (struct regopt_info));
+	  break;
+	}
+      insn = NEXT_INSN (insn);
+    }
+}
+
+void
+loop_undo_all ()
+{
+  register int i;
+  if (undobuf.num_undo > MAX_UNDO)
+    undobuf.num_undo = MAX_UNDO;
+  for (i = undobuf.num_undo - 1; i >= 0; i--)
+    *undobuf.undo[i].where = undobuf.undo[i].old_contents;
+
+  obfree (undobuf.storage);
+  undobuf.num_undo = 0;
+}
+
+/* Replace in pat of insn each MEM with a corresponding reg if one exists.  */
+static
+rtx 
+replace_mems (insn, pat)
+     rtx insn, pat;
+{
+  register RTX_CODE code = GET_CODE (pat);
+  register int i, j;
+  register char *fmt;
+
+  switch (code)
+    {
+    case HIGH:
+    case CONST_INT:
+    case CONST:
+    case CONST_DOUBLE:
+    case SYMBOL_REF:
+    case LABEL_REF:
+    case PC:
+    case CC0:
+    case REG:
+      return pat;
+
+
+    }
+
+  if (GET_CODE (pat) == MEM)
+    {
+      for (i = 0; i < mem_max_reg_num; i++)
+	{
+	  if (rinfo[i].corresp_mem && rinfo[i].replace_reg == 0 
+	      && rtx_equal_p (rinfo[i].corresp_mem, pat))
+	    {
+	      return (rinfo[i].reg);
+	    }
+	}
+    }
+  fmt = GET_RTX_FORMAT (code);
+  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+    if (fmt[i] == 'e')
+      XEXP (pat, i) = replace_mems (insn, XEXP (pat, i));
+    else if (fmt[i] == 'E' || fmt[i] == 'V')
+      {
+	for (j = 0; j < XVECLEN (pat, i); j++)
+	  XVECEXP (pat, i, j) 
+	    = replace_mems (insn, XVECEXP (pat, i, j));
+      }
+  return pat;
+}
+
+
+/* Replace in orig each occurrence of reg_rplc with the value
+   described by *rptr.  The location in orig of reg_rplc is where.  
+*/
+static void
+replace_reg (orig, where, reg_rplc, rptr)
+     register rtx orig, reg_rplc;
+     rtx *where;
+     struct regopt_info *rptr;
+{
+  rtx non_biv_operand, ret_rtx;
+  register int i, j;
+  register RTX_CODE code;
+  register char *fmt;
+
+  code = GET_CODE (orig);
+
+  switch (code)
+    {
+    case REG:
+      if (rtx_equal_p (orig, reg_rplc))
+	{
+	  if (GET_CODE (SET_SRC (PATTERN (rptr->insn_set))) == ASHIFT 
+	      && GET_CODE (XEXP (SET_SRC (PATTERN (rptr->insn_set)), 1)) == CONST_INT
+	    )
+	    {
+	      LOOP_SUBST (where,
+	      (gen_rtx (MULT, GET_MODE (SET_SRC (PATTERN (rptr->insn_set))),
+			XEXP (SET_SRC (PATTERN (rptr->insn_set)), 0),
+			gen_rtx (CONST_INT, 0,
+				 two_to_power (INTVAL (XEXP (SET_SRC (PATTERN (rptr->insn_set)), 1)))))));
+	    }
+	  else
+	    {
+	      LOOP_SUBST (where, (SET_SRC (PATTERN (rptr->insn_set))));
+	    }
+	}
+      break;
+
+    case QUEUED:
+    case CONST_INT:
+    case CONST_DOUBLE:
+    case SYMBOL_REF:
+    case CODE_LABEL:
+    case PC:
+    case CC0:
+      return;
+    }
+
+
+  fmt = GET_RTX_FORMAT (code);
+
+  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+    if (fmt[i] == 'e')
+      replace_reg (XEXP (orig, i), &XEXP (orig, i), reg_rplc, rptr);
+    else if (fmt[i] == 'E' || fmt[i] == 'V')
+      {
+	for (j = 0; j < XVECLEN (orig, i); j++)
+	  replace_reg (XVECEXP (orig, i, j), &XVECEXP (orig, i, j), reg_rplc, rptr);
+      }
+}
+
+
+static int
+two_to_power (x)
+     int x;
+{
+  int retval, i;
+
+  retval = 1;
+  for (i = 0; i < x; i++)
+    retval *= 2;
+  return (retval);
+}
+
+
+/* Return 1 iff insn p jumps backward to a label that is located
+   between loop_start and p,
+   if strict==1 we also require that any jumps between the target label and
+   p jump to labels that are between the target label and p.  */
+static int
+jumps_back_in_loop (p, loop_start, use1, strict)
+     rtx p, loop_start;
+     int use1;		/* If 1 then we require each label within to be accessed only once */
+     int strict;
+{
+  rtx insn, target, last_jump_found;
+  int jumps_found, labels_found;
+
+  if (!flag_jump_back)
+    return (0);
+  target = JUMP_LABEL (p);
+  insn = PREV_INSN (p);
+  jumps_found = 0;
+  labels_found = 0;
+  while (insn != target && insn != loop_start)
+    {
+      if (GET_CODE (insn) == JUMP_INSN)
+	{
+	  jumps_found++;
+	}
+      else if (GET_CODE (insn) == CODE_LABEL)
+	{
+	  if (use1 && LABEL_NUSES (insn) != 1)
+	    {
+	      return (0);
+	    }
+	  labels_found++;
+	}
+
+      insn = PREV_INSN (insn);
+    }
+  if (insn != target)
+    {
+      return (0);
+    }
+  else
+    {
+      if (use1 && jumps_found != labels_found)
+	{
+	  return (0);
+	}
+      if (jumps_found == 0 || strict == 0)
+	{
+	  return (1);
+	}
+      else
+	{ /* Must check each jump to see that it jumps to label
+	     between target and p.  */
+	  last_jump_found = target;
+	  while (jumps_found)
+	    {
+	      /* Find the next jump.  */
+	      insn = NEXT_INSN (last_jump_found);
+	      while (GET_CODE (insn) != JUMP_INSN)
+		{
+		  insn = NEXT_INSN (insn);
+		}
+	      last_jump_found = insn;
+	      /* Now find the target. */
+	      while (insn != p && insn != JUMP_LABEL (last_jump_found))
+		{ /* Search forward.  */
+		  insn = NEXT_INSN (insn);
+		}
+	      if (insn == JUMP_LABEL (last_jump_found) 
+		  && (!use1 || LABEL_NUSES (JUMP_LABEL (last_jump_found)) == 1)
+		)
+		{
+		  jumps_found--;
+		}
+	      else
+		{
+		  while (insn != loop_start && insn != JUMP_LABEL (last_jump_found))
+		    { /* Search backwards. */
+		      insn = PREV_INSN (insn);
+		    }
+		  if (insn == JUMP_LABEL (last_jump_found) 
+		      && (!use1 || LABEL_NUSES (JUMP_LABEL (last_jump_found)) == 1)
+		    )
+		    {
+		      jumps_found--;
+		    }
+		  else
+		    {
+		      break;
+		    }
+		}
+	    }
+	  return (jumps_found == 0);
+	}
+    }
+}
+
+
+struct propogate_cand
+{
+  rtx srcpat;
+  rtx add_reg0;
+  rtx add_reg1;
+  rtx mul_reg;
+  rtx reg;
+  int mul_val;
+  char cand_type;
+};
+
+struct unroll_combine_cand
+{
+  rtx reg;
+  struct unroll_combine_cand *next;
+};
+
+#define COPY 1
+#define GIV 2
+
+/* Try to propogate copies into loop as follows:
+   If before the loop we have
+   regx <- regy
+   and in the loop regx is only used, then replace each use of regx
+   in the loop with regy
+*/
+static
+loop_copy_propogate (loop_start, loop_end)
+     rtx loop_start, loop_end;
+{
+  struct propogate_cand *copy_candidates, *possible_giv_candidate;
+  char *regs_set, dummyc;
+  rtx insn, loop_label, loop_jump, dest, src, *split_giv_src;
+  int num_copy_candidates, num_giv_candidates,
+    stop_looking, cur_max_regnum, i, dummyi, num_unroll_candidates;
+  struct unroll_combine_cand **unroll_cands, *an_unroll_cand;
+
+  cur_max_regnum = max_reg_num () + 1;
+  if (loop_dump_stream)
+    {
+      fprintf (loop_dump_stream, "copy prop from %d to %d\n",
+	       INSN_UID (loop_start), INSN_UID (loop_end));
+    }
+  copy_candidates = (struct propogate_cand *)
+    alloca (cur_max_regnum * sizeof (struct propogate_cand));
+  bzero (copy_candidates, (cur_max_regnum * sizeof (struct propogate_cand)));
+  regs_set = (char *) alloca (cur_max_regnum);
+  bzero (regs_set, cur_max_regnum);
+  n_times_set = (short *) alloca (cur_max_regnum * sizeof (short));
+  bzero (n_times_set, cur_max_regnum * sizeof (short));
+  may_not_optimize = (char *) alloca (cur_max_regnum);	/* not used */
+  if (flag_unroll_loops)
+    {
+      unroll_cands 
+	= (struct unroll_combine_cand **)
+	alloca (cur_max_regnum * sizeof (struct unroll_combine_cand *));
+      bzero (unroll_cands, cur_max_regnum * sizeof (struct unroll_combine_cand *));
+      split_giv_src = (rtx *) alloca (cur_max_regnum * sizeof (rtx));
+      bzero (split_giv_src, cur_max_regnum * sizeof (rtx));
+    }
+  /* First check that the label that is the start of the loop
+     is only jumped to from within the loop - if not return
+  */
+  insn = loop_start;
+  while (insn && GET_CODE (insn) != CODE_LABEL)
+    {
+      insn = NEXT_INSN (insn);
+    }
+  loop_label = insn;
+  insn = loop_end;
+  while (insn && GET_CODE (insn) != JUMP_INSN)
+    {
+      insn = PREV_INSN (insn);
+    }
+  loop_jump = insn;
+  if (!loop_label || !loop_jump 
+      || (JUMP_LABEL (loop_jump) != loop_label) 
+      || (LABEL_NUSES (JUMP_LABEL (loop_jump)) != 1)
+    )
+    {
+      return;
+    }
+  /* Compute n_times_set */
+  count_loop_regs_set (loop_start, loop_end, may_not_optimize, NULL,
+		       &dummyi, cur_max_regnum);
+
+  /* Look backwards from loop_start until a label barier or
+     uncoditional jump is reached,
+     searching for insns of the form regx <- regy and regx
+     NOT set in loop  - these are candidates for copy propogation.  
+     Also search for registers that are set rega <- regb*C + regd
+     - rega is a candidate for inter loop giv combination.  
+  */
+  insn = loop_start;
+  num_copy_candidates = 0;
+  num_giv_candidates = 0;
+  num_unroll_candidates = 0;
+  stop_looking = 0;
+  possible_giv_candidate = NULL;
+  while (insn && !stop_looking)
+    {
+      switch (GET_CODE (insn))
+	{
+	case NOTE:
+	  break;
+
+	case JUMP_INSN:
+	  if (SET_DEST (PATTERN (insn)) == pc_rtx
+	      && GET_CODE (SET_SRC (PATTERN (insn))) == LABEL_REF)
+	    {
+	      stop_looking = 1;
+	    }
+	  break;
+
+	case CODE_LABEL:
+	case BARRIER:
+	  stop_looking = 1;
+	  break;
+
+	case INSN:
+	  if (GET_CODE (PATTERN (insn)) != SET)
+	    {
+	      stop_looking = 1;
+	    }
+	  else
+	    {
+	      dest = SET_DEST (PATTERN (insn));
+	      src = SET_SRC (PATTERN (insn));
+	      if (GET_CODE (dest) == REG)
+		{
+		  if (flag_unroll_loops && dest != cc0_rtx 
+		      && REGNO (dest) >= FIRST_PSEUDO_REGISTER 
+		      && dest != pc_rtx && regs_set[REGNO (dest)] == 0 
+		      && GET_CODE (src) == REG && regs_set[REGNO (src)] == 0
+		      && REGNO (src) >= FIRST_PSEUDO_REGISTER )
+		    { /* The dest may be a split giv which we want
+                         to combine */
+		      if (split_giv_src[REGNO (dest)] == NULL)
+			{
+			  split_giv_src[REGNO (dest)] = src;
+			  an_unroll_cand 
+			    = (struct unroll_combine_cand *)
+			    alloca (sizeof (struct unroll_combine_cand));
+			  an_unroll_cand->reg = dest;
+			  an_unroll_cand->next = unroll_cands[REGNO (src)];
+			  unroll_cands[REGNO (src)] = an_unroll_cand;
+			  num_unroll_candidates++;
+			}
+		      else
+			{
+			  split_giv_src[REGNO (dest)] = (rtx) - 1;
+			}
+		    }
+
+		  if (dest != cc0_rtx && dest != pc_rtx 
+		      && REGNO (dest) >= FIRST_PSEUDO_REGISTER 
+		      && regs_set[REGNO (dest)] == 0)
+		    {
+		      if (GET_CODE (src) == REG 
+			  && REGNO (src) >= FIRST_PSEUDO_REGISTER 
+			  && n_times_set[REGNO (src)] == 0 
+			  && regs_set[REGNO (src)] == 0)
+			{
+			  if (n_times_set[REGNO (dest)] == 0)
+			    {
+			      num_copy_candidates++;
+			      copy_candidates[REGNO (dest)].srcpat = src;
+			      copy_candidates[REGNO (dest)].cand_type = COPY;
+			    }
+			}
+		      else
+			{
+			  if (GET_CODE (src) == PLUS 
+			      && GET_CODE (XEXP (src, 0)) == REG 
+			      && REGNO (XEXP (src, 0)) >= FIRST_PSEUDO_REGISTER 
+			      && GET_CODE (XEXP (src, 1)) == REG 
+			      && REGNO (XEXP (src, 1)) >= FIRST_PSEUDO_REGISTER 
+			      && regs_set[REGNO (XEXP (src, 0))] == 0 
+			      && regs_set[REGNO (XEXP (src, 1))] == 0 
+			      && n_times_set[REGNO (XEXP (src, 1))] == 0 
+			      && copy_candidates[REGNO (dest)].srcpat == NULL 
+			      && copy_candidates[REGNO (dest)].add_reg0 == NULL)
+			    {
+			      copy_candidates[REGNO (dest)].add_reg0 
+				= XEXP (src, 0);
+			      copy_candidates[REGNO (dest)].add_reg1 
+				= XEXP (src, 1);
+			      possible_giv_candidate 
+				= &copy_candidates[REGNO (dest)];
+			      possible_giv_candidate->reg = dest;
+			    }
+			  else if (GET_CODE (src) == ASHIFT 
+				   && GET_CODE (XEXP (src, 0)) == REG 
+				   && GET_CODE (XEXP (src, 1)) == CONST_INT 
+				   && regs_set[REGNO (XEXP (src, 0))] == 0 
+				   && possible_giv_candidate 
+				   && possible_giv_candidate->mul_reg == NULL 
+				   && rtx_equal_p (dest, possible_giv_candidate->add_reg0)
+			    )
+			    {
+			      possible_giv_candidate->mul_reg = XEXP (src, 0);
+			      possible_giv_candidate->mul_val 
+				= two_to_power (INTVAL (XEXP (src, 1)));
+			      possible_giv_candidate->cand_type = GIV;
+			      num_giv_candidates++;
+			    }
+			}
+		    }
+		  regs_set[REGNO (dest)] = 1;
+		}
+	    }
+	  break;
+
+	default:
+	  stop_looking = 1;
+	  break;
+	}
+      insn = PREV_INSN (insn);
+    }
+  if (num_copy_candidates != 0)
+    {
+      /* Now for each candidate do the replacement */
+      do_replace (loop_start, loop_end, copy_candidates);
+    }
+  if (num_unroll_candidates != 0)
+    {
+      try_unroll_propogation (loop_start, loop_end, unroll_cands, split_giv_src);
+    }
+}
+
+/*
+  Each occurence of a copy_candidate in an insn between loop_start
+  and loop_end is replaced by the corresponding register.  
+*/
+static
+do_replace (loop_start, loop_end, copy_candidates)
+     rtx loop_start, loop_end;
+     struct propogate_cand *copy_candidates;
+{
+  rtx insn, subst_cands ();
+
+  for (insn = loop_start; insn != loop_end; insn = NEXT_INSN (insn))
+    {
+      if (GET_CODE (insn) == INSN)
+	{
+	  subst_cands (insn, PATTERN (insn), copy_candidates);
+	}
+    }
+}
+
+
+/* Each register in pat which is a copy_candidate of type COPY is replaced with
+   it's copy from outside the loop.  
+*/
+static
+rtx 
+subst_cands (insn, pat, copy_candidates)
+     rtx insn, pat;
+     struct propogate_cand *copy_candidates;
+{
+  register RTX_CODE code = GET_CODE (pat);
+  register int i, j;
+  register char *fmt;
+
+  switch (code)
+    {
+    case HIGH:
+    case CONST_INT:
+    case CONST:
+    case CONST_DOUBLE:
+    case SYMBOL_REF:
+    case LABEL_REF:
+    case PC:
+    case CC0:
+      return pat;
+
+    case REG:
+      {
+	register int regno = REGNO (pat);
+
+	if (copy_candidates[regno].srcpat 
+	    && copy_candidates[regno].cand_type == COPY)
+	  {
+	    if (loop_dump_stream)
+	      {
+		fprintf (loop_dump_stream, "replacing reg%d with reg%d in insn %d\n",
+			 regno, REGNO (copy_candidates[regno].srcpat), INSN_UID (insn));
+	      }
+	    return (copy_candidates[regno].srcpat);
+	  }
+      }
+      return pat;
+
+    }
+
+  fmt = GET_RTX_FORMAT (code);
+  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+    if (fmt[i] == 'e')
+      XEXP (pat, i) = subst_cands (insn, XEXP (pat, i), copy_candidates);
+    else if (fmt[i] == 'E' || fmt[i] == 'V')
+      {
+	for (j = 0; j < XVECLEN (pat, i); j++)
+	  XVECEXP (pat, i, j) 
+	    = subst_cands (insn, XVECEXP (pat, i, j), copy_candidates);
+      }
+  return pat;
+}
+
+struct reg_incs
+{
+  int inc_val;
+  char invalid;
+};
+
+/* Try to combine split givs from unrolling into one giv to decrease
+   register pressure and increase scheduling possiblities
+*/
+static
+try_unroll_propogation (loop_start, loop_end, unroll_cands, split_giv_src)
+     rtx loop_start, loop_end;
+     struct unroll_combine_cand **unroll_cands;
+     rtx *split_giv_src;
+{
+  rtx insn, src, dest, ninsn, nsrc, ndest, unroll_subst_cands ();
+  struct reg_incs *reg_inc;
+  int i, cur_max_regnum, found;
+
+  if (loop_dump_stream)
+    {
+      fprintf (loop_dump_stream, " unroll propogate from %d to %d\n",
+	       INSN_UID (loop_start), INSN_UID (loop_end));
+    }
+  cur_max_regnum = max_reg_num () + 1;
+  reg_inc 
+    = (struct reg_incs *) alloca (cur_max_regnum * (sizeof (struct reg_incs)));
+  bzero (reg_inc, cur_max_regnum * (sizeof (struct reg_incs)));
+  insn = NEXT_INSN (loop_start);
+  while (insn != loop_end)
+    {
+      switch (GET_CODE (insn))
+	{
+
+	case NOTE:
+	  break;
+
+	case JUMP_INSN:
+	case CODE_LABEL:
+	case BARRIER:
+	  unroll_consistancy_maintained (cur_max_regnum, unroll_cands,
+					 reg_inc, insn, split_giv_src);
+	  /* forget everything */
+	  bzero (reg_inc, cur_max_regnum * (sizeof (struct reg_incs)));
+	  break;
+
+	case INSN:
+	  if (GET_CODE (PATTERN (insn)) == PARALLEL)
+	    {
+	      return;
+	    }
+	  if (GET_CODE (PATTERN (insn)) != SET)
+	    {
+	      return;
+	    }
+	  dest = SET_DEST (PATTERN (insn));
+	  if (GET_CODE (dest) == REG)
+	    {
+	      if (GET_CODE (SET_SRC (PATTERN (insn))) == PLUS 
+		  && rtx_equal_p (XEXP (SET_SRC (PATTERN (insn)), 0), dest) 
+		  && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == CONST_INT)
+		{ /* reg incremented by constatnt */
+		  reg_inc[REGNO (dest)].inc_val 
+		    += INTVAL (XEXP (SET_SRC (PATTERN (insn)), 1));
+		}
+	      else
+		{
+		  reg_inc[REGNO (dest)].invalid = 1;
+		}
+	    }
+	  break;
+
+	default:
+	  return;
+	  break;
+	}
+      insn = NEXT_INSN (insn);
+    }
+  insn = NEXT_INSN (loop_start);
+  /* Combine each valid unroll candidate */
+  for (insn = loop_start; insn != loop_end; insn = NEXT_INSN (insn))
+    {
+      if (GET_CODE (insn) == INSN)
+	{
+	  unroll_subst_cands (insn, PATTERN (insn), unroll_cands, split_giv_src);
+	}
+    }
+}
+
+
+/* Try to combine split givs from unrolling into one giv to decrease
+   register pressure and increase scheduling possiblities
+*/
+static
+rtx 
+unroll_subst_cands (insn, pat, unroll_cands, split_giv_src)
+     rtx insn, pat;
+     struct unroll_combine_cand **unroll_cands;
+     rtx *split_giv_src;
+{
+  register RTX_CODE code = GET_CODE (pat);
+  register int i, j;
+  register char *fmt;
+
+  if (GET_CODE (pat) == REG && pat == SET_DEST (PATTERN (insn)))
+    {
+      return (pat);
+    }
+  switch (code)
+    {
+    case HIGH:
+    case CONST_INT:
+    case CONST:
+    case CONST_DOUBLE:
+    case SYMBOL_REF:
+    case LABEL_REF:
+    case PC:
+    case CC0:
+      return pat;
+
+    case REG:
+      {
+	register int regno = REGNO (pat);
+
+	if (split_giv_src[regno] && split_giv_src[regno] != (rtx) - 1 
+	    && unroll_cands[REGNO (split_giv_src[regno])])
+	  {
+	    if (loop_dump_stream)
+	      {
+		fprintf (loop_dump_stream, "   replacing reg%d with reg%d in insn %d\n",
+		      regno, REGNO (split_giv_src[regno]), INSN_UID (insn));
+	      }
+	    return (split_giv_src[regno]);
+	  }
+      }
+      return pat;
+
+    }
+
+  fmt = GET_RTX_FORMAT (code);
+  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+    if (fmt[i] == 'e')
+      XEXP (pat, i) 
+	= unroll_subst_cands (insn, XEXP (pat, i), unroll_cands, split_giv_src);
+    else if (fmt[i] == 'E' || fmt[i] == 'V')
+      {
+	for (j = 0; j < XVECLEN (pat, i); j++)
+	  XVECEXP (pat, i, j) 
+	    = unroll_subst_cands (insn, XVECEXP (pat, i, j), unroll_cands,
+			  split_giv_src);
+      }
+  return pat;
+}
+
+/* Check that spilt givs remain consistant */
+static
+unroll_consistancy_maintained (cur_max_regnum, unroll_cands, reg_inc, insn,
+			       split_giv_src)
+     int cur_max_regnum;
+     struct unroll_combine_cand **unroll_cands;
+     struct reg_incs *reg_inc;
+     rtx *split_giv_src;
+     rtx insn;
+{
+  int i;
+  struct unroll_combine_cand *an_unroll_cand;
+
+  for (i = 0; i < cur_max_regnum; i++)
+    {
+      if (unroll_cands[i])
+	{
+	  if (reg_inc[i].invalid)
+	    {
+	      unroll_cands[i] = NULL;
+	    }
+	  else
+	    { /* Check each candidate to see that it was incremented
+                 by same amount.  */
+	      an_unroll_cand = unroll_cands[i];
+	      while (an_unroll_cand)
+		{
+		  if (reg_inc[REGNO (an_unroll_cand->reg)].invalid 
+		      || reg_inc[REGNO (an_unroll_cand->reg)].inc_val !=
+		      reg_inc[i].inc_val)
+		    {
+		      split_giv_src[REGNO (an_unroll_cand->reg)] = (rtx) - 1;
+		    }
+		  an_unroll_cand = an_unroll_cand->next;
+		}
+	    }
+	}
+    }
+}
+
+
+#ifdef STORE_NOT_SET_CC0
+#ifdef STACK_REGS
+/* do_spl is called after reload because the reloader decides to spill
+   fp regs, for no appareant reason, if it is done before.
+*/
+void
+do_spl (f)
+     /* f is the first instruction of a chain of insns for one function */
+     rtx f;
+{
+  register rtx insn;
+  register int i;
+  rtx end;
+  rtx last_insn;
+
+#ifndef HAVE_cc0
+  return;
+#endif
+
+  /* Count the number of loops. */
+
+  max_loop_num = 0;
+  for (insn = f; insn; insn = NEXT_INSN (insn))
+    {
+      if (GET_CODE (insn) == NOTE
+	  && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
+	max_loop_num++;
+    }
+
+  /* Don't waste time if no loops.  */
+  if (max_loop_num == 0)
+    return;
+  doing_spl = 1;
+  /* Get size to use for tables indexed by uids.
+     Leave some space for labels allocated by find_and_verify_loops.  */
+  max_uid_for_loop = get_max_uid () + 1 + max_loop_num * 4;
+
+  uid_luid = (int *) alloca (max_uid_for_loop * sizeof (int));
+  uid_loop_num = (int *) alloca (max_uid_for_loop * sizeof (int));
+
+  bzero (uid_luid, max_uid_for_loop * sizeof (int));
+  bzero (uid_loop_num, max_uid_for_loop * sizeof (int));
+
+  /* Allocate tables for recording each loop.  We set each entry, so they need
+     not be zeroed.  */
+  loop_number_loop_starts = (rtx *) alloca (max_loop_num * sizeof (rtx));
+  loop_number_loop_ends = (rtx *) alloca (max_loop_num * sizeof (rtx));
+  loop_outer_loop = (int *) alloca (max_loop_num * sizeof (int));
+  loop_invalid = (char *) alloca (max_loop_num * sizeof (char));
+  loop_number_exit_labels = (rtx *) alloca (max_loop_num * sizeof (rtx));
+
+  /* Find and spl each loop.
+     First, find them, and record them in order of their beginnings.  */
+  find_and_verify_loops (f);
+  for (i = max_loop_num - 1; i >= 0; i--)
+    {
+      if (loop_number_loop_ends[i])
+	loop_spl (loop_number_loop_starts[i], loop_number_loop_ends[i], i, 1);
+    }
+  doing_spl = 0;
+}
+
+/*
+   A mini software pipelining - consists of two steps
+   1) try to get the floating point store to be the last instruction
+      executed before the jump at the end of loop.
+   2) try to get the jump to be executed before the floating point
+      store by retargeting it to the begining of loop and moving
+      the floating point store to there.  Note that the fall into the
+      loop will be replaced by a jump around this floating point store
+   If do_all is 0 then just do step 1
+*/
+static
+loop_spl (loop_start, loop_end, loop_num, do_all)
+     rtx loop_start, loop_end;
+     int loop_num, do_all;
+{
+  rtx insn, jump_insn, mem_addr, base_reg, index_reg, copy_pat, label_insn,
+    label, p, *index_where, *base_where, pinsn, cc0_insn, where_to_move;
+  struct reg_incs *reg_inc;
+  int cur_max_regnum, scale;
+  char *storage;
+
+  if (loop_dump_stream)
+    {
+      fprintf (loop_dump_stream, "loop_spl from %d to %d\n",
+	       INSN_UID (loop_start), INSN_UID (loop_end));
+    }
+  cur_max_regnum = max_reg_num () + 1;
+  reg_inc 
+    = (struct reg_incs *) alloca (cur_max_regnum * (sizeof (struct reg_incs)));
+  bzero (reg_inc, cur_max_regnum * (sizeof (struct reg_incs)));
+  insn = PREV_INSN (loop_end);
+  while (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET 
+	 && rtx_equal_p (SET_DEST (PATTERN (insn)), SET_SRC (PATTERN (insn))))
+    {
+      insn = PREV_INSN (insn);
+    }
+  if (GET_CODE (insn) != JUMP_INSN)
+    {
+      
+      return;
+    }
+  jump_insn = insn;
+  insn = PREV_INSN (jump_insn);
+  if (!(GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET 
+	&& SET_DEST (PATTERN (insn)) == cc0_rtx))
+    {
+      
+      return;
+    }
+  cc0_insn = insn;
+  base_reg = NULL;
+  index_reg = NULL;
+  scale = 1;
+  insn = prev_nonnote_insn (insn);
+  while (1)
+    {
+      if (GET_CODE (insn) != INSN)
+	{
+	  
+	  return;
+	}
+      if (GET_CODE (PATTERN (insn)) != SET)
+	{
+	  
+	  return;
+	}
+      if (GET_CODE (SET_DEST (PATTERN (insn))) == REG 
+	  && (GET_CODE (SET_SRC (PATTERN (insn))) == PLUS 
+	   || GET_CODE (SET_SRC (PATTERN (insn))) == MINUS) 
+	  && rtx_equal_p (SET_DEST (PATTERN (insn)),
+		       XEXP (SET_SRC (PATTERN (insn)), 0)) 
+	  && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == CONST_INT)
+	{
+	  reg_inc[REGNO (SET_DEST (PATTERN (insn)))].inc_val 
+	    += INTVAL (XEXP (SET_SRC (PATTERN (insn)), 1));
+	  if (GET_CODE (SET_SRC (PATTERN (insn))) == MINUS)
+	    {
+	      reg_inc[REGNO (SET_DEST (PATTERN (insn)))].inc_val *= -1;
+	    }
+	  insn = prev_nonnote_insn (insn);
+	}
+      else
+	{
+	  break;
+	}
+    }
+  if (!(GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET 
+	&& (GET_CODE (SET_SRC (PATTERN (insn))) == REG 
+	|| (GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT_TRUNCATE 
+	&& GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == REG) 
+	|| (GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT_EXTEND 
+	&& GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == REG))
+	&& GET_CODE (SET_DEST (PATTERN (insn))) == MEM 
+	&& (GET_MODE (SET_DEST (PATTERN (insn))) == SFmode 
+	|| GET_MODE (SET_DEST (PATTERN (insn))) == DFmode) 
+        && GET_MODE (SET_DEST (PATTERN (insn))) == 
+            GET_MODE (SET_SRC (PATTERN (insn)))
+      )
+    )
+    {
+      
+      return;
+    }
+  /* if previous fp instruction is fld - no gain */
+  pinsn = prev_nonnote_insn (insn);
+  if (INSN_UID (pinsn) < INSN_UID (loop_start))
+    {
+      
+      return;
+    }
+  while (pinsn != loop_start)
+    {
+      if (GET_CODE (pinsn) == JUMP_INSN || GET_CODE (pinsn) == CODE_LABEL 
+	  || (GET_CODE (pinsn) == INSN && GET_CODE (PATTERN (pinsn)) == SET 
+	   && (GET_MODE (SET_DEST (PATTERN (pinsn))) == SFmode 
+	    || GET_MODE (SET_DEST (PATTERN (pinsn))) == DFmode)
+	  )
+	)
+	{
+	  break;
+	}
+      pinsn = PREV_INSN (pinsn);
+    }
+  if (pinsn == loop_start || GET_CODE (pinsn) == JUMP_INSN 
+      || GET_CODE (pinsn) == CODE_LABEL)
+    {
+      
+      return;
+    }
+  if ((GET_CODE (SET_SRC (PATTERN (pinsn))) == MEM 
+	   || GET_CODE (SET_SRC (PATTERN (pinsn))) == CONST_DOUBLE 
+	   || GET_CODE (SET_SRC (PATTERN (pinsn))) == REG)
+    )
+    {
+      
+      return;
+    }
+  /* We have found the floating point store insn - now try to move it down */
+  /* Find the registers that are used as bases for the memory access in the
+     insn */
+  storage = (char *) oballoc (0);
+  copy_pat = copy_rtx (PATTERN (insn));
+  mem_addr = XEXP (SET_DEST (copy_pat), 0);
+  if (GET_CODE (mem_addr) == PLUS)
+    {
+      if (GET_CODE (XEXP (mem_addr, 0)) == MULT)
+	{
+	  if (GET_CODE (XEXP (XEXP (mem_addr, 0), 0)) == REG 
+	      && GET_CODE (XEXP (XEXP (mem_addr, 0), 1)) == CONST_INT)
+	    {
+	      index_where = &XEXP (XEXP (mem_addr, 0), 0);
+	      index_reg = XEXP (XEXP (mem_addr, 0), 0);
+	      scale = INTVAL (XEXP (XEXP (mem_addr, 0), 1));
+	    }
+	  else
+	    {
+	      
+	      return;
+	    }
+	  if (GET_CODE (XEXP (mem_addr, 1)) == REG)
+	    {
+	      base_where = &XEXP (mem_addr, 1);
+	      base_reg = XEXP (mem_addr, 1);
+	    }
+	  else if (GET_CODE (XEXP (mem_addr, 1)) == SYMBOL_REF 
+		   || GET_CODE (XEXP (mem_addr, 1)) == CONST)
+	    {
+	      ;
+	    }
+	  else
+	    {
+	      
+	      return;
+	    }
+	}
+      else if (GET_CODE (XEXP (mem_addr, 0)) == PLUS)
+	{
+	  /* Take care of non canonicalized expressions */
+	  rtx tmp;
+	  if (GET_CODE (XEXP (XEXP (mem_addr, 0), 0)) == REG 
+	      && GET_CODE (XEXP (XEXP (mem_addr, 0), 1)) == MULT)
+	    {
+	      tmp = XEXP (XEXP (mem_addr, 0), 0);
+	      XEXP (XEXP (mem_addr, 0), 0) = XEXP (XEXP (mem_addr, 0), 1);
+	      XEXP (XEXP (mem_addr, 0), 1) = tmp;
+	    }
+
+	  if (GET_CODE (XEXP (XEXP (mem_addr, 0), 0)) != MULT)
+	    {
+	      
+	      return;
+	    }
+	  if (GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0)) == REG 
+	      && GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1)) == CONST_INT)
+	    {
+	      index_where = &XEXP (XEXP (XEXP (mem_addr, 0), 0), 0);
+	      index_reg = XEXP (XEXP (XEXP (mem_addr, 0), 0), 0);
+	      scale = INTVAL (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1));
+	    }
+	  else
+	    {
+	      
+	      return;
+	    }
+	  if (GET_CODE (XEXP (XEXP (mem_addr, 0), 1)) != REG)
+	    {
+	      
+	      return;
+	    }
+	  base_where = &XEXP (XEXP (mem_addr, 0), 1);
+	  base_reg = XEXP (XEXP (mem_addr, 0), 1);
+	  if (GET_CODE (XEXP (mem_addr, 1)) == SYMBOL_REF 
+	      || GET_CODE (XEXP (mem_addr, 1)) == CONST 
+	      || GET_CODE (XEXP (mem_addr, 1)) == CONST_INT)
+	    {
+	      ;
+	    }
+	  else
+	    {
+	      
+	      return;
+	    }
+	}
+      else if (GET_CODE (XEXP (mem_addr, 0)) == REG)
+	{
+	  base_where = &XEXP (mem_addr, 0);
+	  base_reg = XEXP (mem_addr, 0);
+	  if (GET_CODE (XEXP (mem_addr, 1)) == REG)
+	    {
+	      index_where = &XEXP (mem_addr, 1);
+	      index_reg = XEXP (mem_addr, 1);
+	    }
+	}
+      else
+	{
+	  
+	  return;
+	}
+    }
+  else if (GET_CODE (mem_addr) == SYMBOL_REF || GET_CODE (mem_addr) == CONST)
+    {
+      ;
+    }
+  else if (GET_CODE (mem_addr) == REG)
+    {
+      base_reg = mem_addr;
+      base_where = &XEXP (SET_DEST (copy_pat), 0);
+    }
+  else
+    {
+      
+      return;
+    }
+  /* Now we know the base index and scale */
+  if (index_reg && reg_inc[REGNO (index_reg)].inc_val)
+    {
+      *index_where = gen_rtx (PLUS, GET_MODE (index_reg), index_reg,
+	   gen_rtx (CONST_INT, 0, reg_inc[REGNO (index_reg)].inc_val * -1));
+    }
+  if (base_reg && reg_inc[REGNO (base_reg)].inc_val)
+    {
+      *base_where = gen_rtx (PLUS, GET_MODE (base_reg), base_reg,
+	    gen_rtx (CONST_INT, 0, reg_inc[REGNO (base_reg)].inc_val * -1));
+    }
+#ifdef REWRITE_ADDRESS
+  if (recog (copy_pat, insn, 0) < 0)
+    {
+      try_to_make_good (SET_DEST (copy_pat));
+    }
+#endif
+  if (recog (copy_pat, insn, 0) < 0)
+    {
+      obfree (storage);
+      
+      return;
+    }
+  if (do_all == 0)
+    {
+      where_to_move = cc0_insn;
+    }
+  else
+    {
+      where_to_move = jump_insn;
+    }
+  /* Now move the store with it's new pattern */
+  PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
+  NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
+  NEXT_INSN (insn) = where_to_move;
+  PREV_INSN (insn) = PREV_INSN (where_to_move);
+  NEXT_INSN (PREV_INSN (where_to_move)) = insn;
+  PREV_INSN (where_to_move) = insn;
+  PATTERN (insn) = copy_pat;
+  if (loop_dump_stream)
+    {
+      fprintf (loop_dump_stream, " moved fp store down\n");
+    }
+  if (do_all == 0)
+    {
+      
+      return;
+    }
+  /* Now move the store again and add a new jump and label */
+  if (loop_invalid[loop_num])
+    {
+      emit_insn_before (gen_rtx (USE, 0, cc0_rtx), insn);
+      
+      return;
+    }
+  if (GET_CODE (NEXT_INSN (loop_start)) != CODE_LABEL)
+    {
+      emit_insn_before (gen_rtx (USE, 0, cc0_rtx), insn);
+      
+      return;
+    }
+  label_insn = NEXT_INSN (loop_start);
+  if (GET_CODE (SET_SRC (PATTERN (jump_insn))) != IF_THEN_ELSE)
+    {
+      emit_insn_before (gen_rtx (USE, 0, cc0_rtx), insn);
+      
+      return;
+    }
+#if 0
+  if (LABEL_NUSES (label_insn) != 1)
+    {
+      emit_insn_before (gen_rtx (USE, 0, cc0_rtx), insn);
+      
+      return;
+    }
+#endif
+  /* Make a jump to the old label just before the label*/
+  p = emit_jump_insn_after (gen_jump (label_insn), 
+                            PREV_INSN (label_insn));
+  JUMP_LABEL (p) = label_insn;
+  emit_barrier_after (p);
+  /* Add a new label just before the old one */
+  label = gen_label_rtx ();
+  label_insn = emit_label_after (label, PREV_INSN (label_insn));
+  /* Make the jump at the end of the loop jump to the new lable */
+  if (XEXP (SET_SRC (PATTERN (jump_insn)), 1) == pc_rtx)
+    {
+      XEXP (SET_SRC (PATTERN (jump_insn)), 2)
+        = gen_rtx (LABEL_REF, VOIDmode, label);
+    }
+  else
+    {
+      XEXP (SET_SRC (PATTERN (jump_insn)), 1)
+        = gen_rtx (LABEL_REF, VOIDmode, label);
+    }
+  ++LABEL_NUSES (label_insn);
+  JUMP_LABEL (jump_insn) = label_insn;
+  /* Move the store to just after the new label */
+  PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
+  NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
+  NEXT_INSN (insn) = NEXT_INSN (label_insn);
+  PREV_INSN (insn) = label_insn;
+  PREV_INSN (NEXT_INSN (label_insn)) = insn;
+  NEXT_INSN (label_insn) = insn;
+  /* Add the store after the jump at the end of the loop */
+  p = emit_insn_after (PATTERN (insn), jump_insn);
+  REG_NOTES (p) = REG_NOTES (insn);
+  if (loop_dump_stream)
+    {
+      fprintf (loop_dump_stream, " spl successful\n");
+    }
+}
+
+#endif
+#endif
+
+/* Element N is first insn in basic block N.
+   This info lasts until we finish compiling the function.  */
+
+extern rtx *basic_block_head;
+
+/* Element N is last insn in basic block N.
+   This info lasts until we finish compiling the function.  */
+
+extern rtx *basic_block_end;
+
+/* Number of basic blocks in the current function.  */
+
+extern int n_basic_blocks;
+
+extern regset *basic_block_live_at_start;
+
+/*        Move spills out of loops if possible i.e.
+          if can find a register in the loop that is
+          alway used to hold a certian spill slot then
+          1) load the spill slot into that register before the
+             loop.
+          2) replace all refernces to the spill slot int the loop with
+             refernces to that register
+          3) if the spill slot was updated in the loop and the pseudo
+             that corresponds to that spill slot is alive at the loop
+             fallout then write that register back to the spill slot
+             at the end of the loop.  NOTE that if the pseudo is
+             alive at any other of the loop exits (if there are any)
+             and the spill slot is updated in the loop then steps
+             1) and 2) are NOT done.  
+          NOTE
+          a) if the spill slot is only loaded into the register once
+             throughout the loop and the spill slot is not updated in
+             the loop then loop_optimize() called from here will
+             probably handle this.  I say probably because maybe_never
+             of scan_loop is rather over cautious since it is set
+             when a jump_insn is encountered but not reset when
+             the corresponding label is encountered.  
+
+
+          Other optimizations which are done here are trying
+          to push invariants that were spilled back into the loop
+          (see push_load_into_loop()).  
+
+          Also a straight line pass over the function is made
+          and whenever a spill slot is loaded into a register
+          if that spill slot is also valid in some register
+          then that spill slot is replaced with that register.  
+          (see peep_spills()).  
+
+*/
+void
+loop_after_global (f, dumpfile)
+     /* f is the first instruction of a chain of insns for one function */
+     rtx f;
+     FILE *dumpfile;
+{
+  rtx insn;
+  int i;
+  rtx nonlocal_label_list = nonlocal_label_rtx_list ();
+  register regset tem;
+
+  int sav_flag_copy_prop;
+  int sav_flag_jump_back;
+  int sav_flag_compare_elim;
+  int sav_flag_unroll_loops;
+  int sav_flag_strength_reduce;
+
+
+  sav_flag_copy_prop = flag_copy_prop;
+  sav_flag_jump_back = flag_jump_back;
+  sav_flag_compare_elim = flag_compare_elim;
+  sav_flag_unroll_loops = flag_unroll_loops;
+  sav_flag_strength_reduce = flag_strength_reduce;
+
+  flag_copy_prop = 0;
+  flag_jump_back = 0;
+  flag_compare_elim = 0;
+  flag_unroll_loops = 0;
+  flag_strength_reduce = 0;
+
+  cur_stack_offset = 0;
+  doing_loop_after_global = 1;
+  loop_optimize (f, dumpfile);
+  doing_loop_after_global = 0;
+  { /* Update basic block start and ends */
+    register RTX_CODE prev_code = JUMP_INSN;
+    register RTX_CODE code;
+    for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
+      {
+	code = GET_CODE (insn);
+	if (code == CODE_LABEL
+	    || (GET_RTX_CLASS (code) == 'i'
+		&& (prev_code == JUMP_INSN
+		    || (prev_code == CALL_INSN
+			&& nonlocal_label_list != 0)
+		    || prev_code == BARRIER)))
+	  i++;
+	if (code != NOTE)
+	  prev_code = code;
+      }
+    if (i > n_basic_blocks)
+      {
+        n_basic_blocks = i;
+        basic_block_head = (rtx *) oballoc (n_basic_blocks * sizeof (rtx));
+        basic_block_end = (rtx *) oballoc (n_basic_blocks * sizeof (rtx));
+      }
+    n_basic_blocks = i;
+    prev_code = JUMP_INSN;
+    for (insn = f, i = -1; insn; insn = NEXT_INSN (insn))
+      {
+	code = GET_CODE (insn);
+	/* A basic block starts at label, or after something that can jump.  */
+	if (code == CODE_LABEL
+	    || (GET_RTX_CLASS (code) == 'i'
+		&& (prev_code == JUMP_INSN
+		    || (prev_code == CALL_INSN
+			&& nonlocal_label_list != 0)
+		    || prev_code == BARRIER)))
+	  {
+	    basic_block_head[++i] = insn;
+	    if (i >= n_basic_blocks)
+	      {
+		abort ();
+	      }
+	    basic_block_end[i] = insn;
+	  }
+	else if (GET_RTX_CLASS (code) == 'i')
+	  {
+	    basic_block_end[i] = insn;
+	  }
+
+	if (code != NOTE
+	    && !(prev_code == CALL_INSN && code == INSN
+		 && GET_CODE (PATTERN (insn)) == CLOBBER))
+	  prev_code = code;
+      }
+  }
+  flag_copy_prop = sav_flag_copy_prop;
+  flag_jump_back = sav_flag_jump_back;
+  flag_compare_elim = sav_flag_compare_elim;
+  flag_unroll_loops = sav_flag_unroll_loops;
+  flag_strength_reduce = sav_flag_strength_reduce;
+
+}
+
+/* x is a spill slot and hence is unaliased
+*/
+
+static int
+spill_invariant_p (x)
+     register rtx x;
+{
+  register int i;
+  register enum rtx_code code;
+  register char *fmt;
+  int conditional = 0;
+
+  if (x == 0)
+    return 1;
+  code = GET_CODE (x);
+  switch (code)
+    {
+    case CONST_INT:
+    case CONST_DOUBLE:
+    case SYMBOL_REF:
+    case CONST:
+      return 1;
+
+    case LABEL_REF:
+      /* A LABEL_REF is normally invariant, however, if we are unrolling
+	 loops, and this label is inside the loop, then it isn't invariant.
+	 This is because each unrolled copy of the loop body will have
+	 a copy of this label.  If this was invariant, then an insn loading
+	 the address of this label into a register might get moved outside
+	 the loop, and then each loop body would end up using the same label.
+
+	 We don't know the loop bounds here though, so just fail for all
+	 labels.  */
+      if (flag_unroll_loops)
+	return 0;
+      else
+	return 1;
+
+    case PC:
+    case CC0:
+    case UNSPEC_VOLATILE:
+      return 0;
+
+    case REG:
+      /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
+	 since the reg might be set by initialization within the loop.  */
+      if (x == frame_pointer_rtx || x == arg_pointer_rtx)
+	return 1;
+      if (loop_has_call
+	  && REGNO (x) < FIRST_PSEUDO_REGISTER && call_used_regs[REGNO (x)])
+	return 0;
+      if (n_times_set[REGNO (x)] < 0)
+	return 2;
+      return n_times_set[REGNO (x)] == 0;
+
+    case MEM:
+      /* Read-only items (such as constants in a constant pool) are
+	 invariant if their address is.  */
+      if (RTX_UNCHANGING_P (x))
+	break;
+
+      /* If we filled the table (or had a subroutine call), any location
+	 in memory could have been clobbered.  */
+      if (unknown_address_altered
+      /* Don't mess with volatile memory references.  */
+	  || MEM_VOLATILE_P (x))
+	return 0;
+
+      /* See if there is any dependence between a store and this load.  */
+      for (i = loop_store_mems_idx - 1; i >= 0; i--)
+	if (rtx_equal_p (XEXP (loop_store_mems[i], 0), XEXP (x, 0)))
+	  {
+	    return 0;
+	  }
+
+      /* It's not invalidated by a store in memory
+	 but we must still verify the address is invariant.  */
+      break;
+
+    case ASM_OPERANDS:
+      /* Don't mess with insns declared volatile.  */
+      if (MEM_VOLATILE_P (x))
+	return 0;
+    }
+
+  fmt = GET_RTX_FORMAT (code);
+  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+    {
+      if (fmt[i] == 'e')
+	{
+	  int tem = invariant_p (XEXP (x, i));
+	  if (tem == 0)
+	    return 0;
+	  if (tem == 2)
+	    conditional = 1;
+	}
+      else if (fmt[i] == 'E')
+	{
+	  register int j;
+	  for (j = 0; j < XVECLEN (x, i); j++)
+	    {
+	      int tem = invariant_p (XVECEXP (x, i, j));
+	      if (tem == 0)
+		return 0;
+	      if (tem == 2)
+		conditional = 1;
+	    }
+
+	}
+    }
+
+  return 1 + conditional;
+}
+
+extern struct reload_slot_info reload_slots[];
+extern num_reload_stack_slots;
+extern char call_used_regs[];
+extern char **insn_name_ptr;
+
+
+static struct spill_candidates
+  {
+    /* The stack slot reloaded into this candidate */
+    rtx reload_slot;
+    /* The insn that does the reloading */
+    rtx reload_insn;
+    /* The rtx of the hard register that is reloaded into */
+    rtx hard_reg;
+    /* The mode of the reload slot */
+    enum machine_mode mode;
+    /* Number of times this candidate is set */
+    int num_times_set;
+    /* The pseduo register corresponding to the stack slot */
+    int pseudo_reg;
+    int cur_stack_offset;
+    int reload_indx;
+    /* A linked list of candidates on the same reload stack slot */
+    struct spill_candidates *link_cand;
+    struct spill_candidates *head_cand;
+    unsigned is_head:1;
+    unsigned has_link:1;
+    /* if 1 this candidate is invalid */
+    unsigned disregard:1;
+    /* if 1 the reload stack slot is stored into */
+    unsigned slot_updated_in_loop:1;
+    /* if 1 the pseduo register is live at the loop fall out */
+    unsigned live_at_fall_out:1;
+    /* if 1 the pseduo register is live at a loop jump out */
+    unsigned live_at_jump_out:1;
+    /* if 1 the value in the candidate hard register must be
+       updated into the reload stack slot */
+    unsigned must_update_reload:1;
+    /* if 1 then the candidate hard register was loaded with the
+       reload stack slot before it was used */
+    unsigned first_set_to_reload:1;
+    /* if 1 then the candidate's spill slot has been updated and
+       the candidate is out of synch with it's spill slot intel1a */
+    unsigned slot_updated:1;
+  }
+
+spill_candidate[FIRST_PSEUDO_REGISTER];
+
+static int all_candidates_invalid = 0;
+static int num_spill_candidates_found = 0;
+static int *insns_moved_out;
+static int have_flow_analysis = 0;
+
+/* Find all candidates for spill slot optimization over the loop and
+   move them out. Also try to push spilled invariants back into the
+   loop
+*/
+static
+void 
+move_spills_out (loop_start, loop_end)
+     rtx loop_start;
+     rtx loop_end;
+{
+  rtx insn;
+  int i, is_loop_exit, regno, indx;
+
+  insns_moved_out = (int *) alloca ((max_uid_for_loop + 1) * sizeof (int));
+  bzero (insns_moved_out, (max_uid_for_loop + 1) * sizeof (int));
+  num_reload_stack_slots = 0;
+  num_spill_candidates_found = 0;
+  bzero (spill_candidate, FIRST_PSEUDO_REGISTER * sizeof (spill_candidate[0]));
+  for (i=0; i<FIRST_PSEUDO_REGISTER; i++)
+    {
+      spill_candidate[i].reload_indx = -1;
+    }
+  insn = loop_start;
+  while (insn != PREV_INSN (loop_end))
+    {
+      if (GET_CODE (insn) == INSN && RTX_IS_SPILL_P (insn) 
+	  && GET_CODE (PATTERN (insn)) == SET 
+	  && GET_CODE (SET_DEST (PATTERN (insn))) == REG 
+	  && GET_CODE (SET_SRC (PATTERN (insn))) == MEM 
+	  && is_a_stack_slot (SET_SRC (PATTERN (insn)))
+	  && (regno = REGNO (SET_DEST (PATTERN (insn)))) < FIRST_PSEUDO_REGISTER
+	)
+	{
+	  indx = -1;
+	  if (!is_a_reload_stack_slot (SET_SRC (PATTERN (insn)), &indx, 0, 0))
+	    {
+	      if (num_reload_stack_slots >= MAX_RELOAD_STACK_SLOTS)
+	        {
+	          return;
+	        }
+	      reload_slots[num_reload_stack_slots].cur_stack_offset = 0;
+	      reload_slots[num_reload_stack_slots].reload_stack_mode = -1;
+	      reload_slots[num_reload_stack_slots].is_loaded_to_reg = -1;
+	      reload_slots[num_reload_stack_slots].reload_slot_updated = 0;
+	      reload_slots[num_reload_stack_slots].stack_slot_pseudo_reg 
+		= SPILL_PSEUDO (insn);
+	      reload_slots[num_reload_stack_slots].reload_insn = insn; 
+	      reload_slots[num_reload_stack_slots++].reload_stack_slot 
+		= SET_SRC (PATTERN (insn));
+	    }
+	  else
+	    { /* We have already encountered this reload slot - it
+                 must always be a reload slot of the same pseudo */
+	      if (reload_slots[indx].stack_slot_pseudo_reg !=
+		  SPILL_PSEUDO (insn))
+		{
+		  reload_slots[indx].reload_stack_mode == -2;
+		}
+	    }
+	  if (indx == -1) 
+	    {
+	      indx = num_reload_stack_slots - 1;
+	    }
+	  if (!(spill_candidate[regno].pseudo_reg == 0 
+		|| spill_candidate[regno].pseudo_reg == SPILL_PSEUDO (insn)))
+	    { /* Candidate can be for only one spilled pseudo reg */
+              reload_slots[indx].reload_stack_mode = -2;
+              if (spill_candidate[regno].reload_indx != -1)
+                {
+                  reload_slots[spill_candidate[regno].reload_indx].reload_stack_mode = -2;
+                }
+	    }
+          else if (spill_candidate[regno].reload_indx != -1
+                   && spill_candidate[regno].reload_indx != indx)
+            { /* Candidates can only be for one reload slot */
+              reload_slots[indx].reload_stack_mode = -2;
+              reload_slots[spill_candidate[regno].reload_indx].reload_stack_mode = -2;
+            }
+          else 
+	    {
+              spill_candidate[regno].pseudo_reg = SPILL_PSEUDO (insn);
+              spill_candidate[regno].reload_indx = indx;
+	    }
+	}
+      insn = NEXT_INSN (insn);
+    }
+
+  all_candidates_invalid = 0;
+  insn = loop_start;
+  while (insn != (loop_end))
+    {
+      if (GET_CODE (insn) == INSN)
+	{
+	  mark_spill_candidates (insn, PATTERN (insn));
+	  if (all_candidates_invalid)
+	    {
+	      return;
+	    }
+	}
+      else if (GET_CODE (insn) == JUMP_INSN)
+	{ /* Check if this is a loop exit */
+	  is_loop_exit = check_if_jumps_out_of_loop (PATTERN (insn), 1);
+	  /* Verify which spill candidates remian valid */
+	  if (num_spill_candidates_found)
+	    verify_spill_candidates (insn, is_loop_exit);
+	  if (all_candidates_invalid)
+	    {
+	      return;
+	    }
+	}
+      else if (GET_CODE (insn) == CODE_LABEL && num_spill_candidates_found)
+	{
+	  /* Verify which spill candidates remian valid */
+	  verify_spill_candidates (insn, 0);
+	}
+      insn = NEXT_INSN (insn);
+    }
+  if (num_spill_candidates_found && !all_candidates_invalid)
+    {
+      int i;
+      rtx rn, prev, link;
+      if (!simplejump_p (PREV_INSN (loop_end)))
+	mark_regs_alive_at_exit (NEXT_INSN (loop_end), 1);
+      if (!all_candidates_invalid)
+	{
+	  move_spill_movables (loop_start, loop_end);
+
+	  for (rn = loop_start; rn != loop_end; rn = NEXT_INSN (rn))
+	    {
+	      if ((GET_CODE (rn) == INSN || GET_CODE (rn) == JUMP_INSN
+		   || GET_CODE (rn) == CALL_INSN) && LOG_LINKS (rn))
+		{
+		  for (prev = 0, link = LOG_LINKS (rn); link;
+		       prev = link, link = XEXP (link, 1))
+		    {
+		      if (insns_moved_out[INSN_UID (XEXP (link, 0))])
+			{
+			  if (prev)
+			    XEXP (prev, 1) = XEXP (link, 1);
+			  else
+			    LOG_LINKS (rn) = XEXP (link, 1);
+			}
+		    }
+
+		}
+	    }
+	}
+    }
+  if (unknown_address_altered)
+    {
+      return;
+    }
+  for (i = 0; i < num_reload_stack_slots; i++)
+    {
+      if (flag_push_load_into_loop
+	  && reload_slots[i].reload_slot_updated == 0 
+	  /*&& reload_slots[i].reload_stack_mode != -2 
+	  && reload_slots[i].is_loaded_to_reg != -1 
+	  && !spill_candidate[reload_slots[i].is_loaded_to_reg].has_link 
+	  && spill_candidate[reload_slots[i].is_loaded_to_reg].disregard 
+	  && spill_candidate[reload_slots[i].is_loaded_to_reg].live_at_jump_out == 0 
+          && spill_candidate[reload_slots[i].is_loaded_to_reg].live_at_fall_out == 0
+          */
+	)
+	{
+	  /* This is a reload slot that was never updated in loop
+             but could not be lifted only because the register it is
+             loaded into was also set to something else in loop.
+             Lets see if the reload slot was set in the basic block
+             just prior to the loop by some inexpensive operation.
+             (particularly a move from memory into a register and
+             a move of that register onto stack). If so lets
+             replace each load of the reload slot in the loop with
+             a load of the memory and delete the code that loaded
+             and spilled it outside the loop.
+             This corrects the preloading of loop invariants that
+             could not be held in registers over the loop
+           */
+	  push_load_into_loop (loop_start, loop_end, i);
+	}
+    }
+}
+
+/* Move the valid spill slot candidates out of the loop and
+   replace the spill slot with the register throughout the loop.
+   Also update the spill slot after the loop if this is necessary */
+
+static
+void 
+move_spill_movables (loop_start, loop_end)
+     rtx loop_start, loop_end;
+{
+  rtx insn;
+  int i, indx, all_are_ok;
+  struct spill_candidates *link_cand;
+  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+    {
+      if (spill_candidate[i].disregard == 0 && spill_candidate[i].reload_insn 
+	  && spill_candidate[i].num_times_set == n_times_set[i])
+	{
+	  is_a_reload_stack_slot (spill_candidate[i].reload_slot, &indx, 0, 0);
+          /* Sanity check */
+          if (spill_candidate[i].reload_indx != indx)
+            {
+              abort ();
+            }
+	  if (reload_slots[indx].reload_stack_mode == -2)
+	    {/* The stack slot was used in some other mode than the
+                 load to the hard reg */
+              spill_candidate[i].disregard = 1;
+	      continue;
+	    }
+	  if (!spill_candidate[i].has_link)
+	    {
+	      all_are_ok = 1;
+	    }
+	  else if (spill_candidate[i].is_head)
+	    {
+	      /* This is a candidate that is the head of a chain of
+                 candidates that all contain the same reload slot.
+                 Go over the linked list to see if all are ok;
+              */
+	      all_are_ok = 1;
+	      link_cand = spill_candidate[i].link_cand;
+	      while (link_cand)
+		{
+		  all_are_ok = all_are_ok 
+		    && link_cand->disregard == 0 
+		    && link_cand->num_times_set == 1 
+		    && n_times_set[REGNO (link_cand->hard_reg)] == 1 
+		    && link_cand->reload_insn;
+		  /* So it won't be processed again */
+		  link_cand->disregard = 1;
+		  link_cand = link_cand->link_cand;
+		}
+	      if (spill_candidate[i].num_times_set != 1)
+		{
+		  all_are_ok = 0;
+		}
+	      if (all_are_ok == 0)
+	        {
+		  spill_candidate[i].disregard = 1;
+		}
+	    }
+	  else
+	    {
+	      all_are_ok = 0;
+	    }
+	  if (all_are_ok)
+	    {
+	      /* Move the reload insn to just before loop_start */
+	      if (loop_dump_stream)
+	        {
+	          fprintf (loop_dump_stream,
+	          "insn %d moved out of loop, stack slot held in reg %d over loop\n",
+	          INSN_UID (spill_candidate[i].reload_insn), i);
+	          if (spill_candidate[i].is_head)
+	            {
+		      fprintf (loop_dump_stream, " these regs also shadow the stack slot:");
+	              link_cand = spill_candidate[i].link_cand;
+	              while (link_cand)
+		        {
+		          fprintf (loop_dump_stream, " %d", REGNO (link_cand->hard_reg));
+		          link_cand = link_cand->link_cand;
+		        }
+		      fprintf (loop_dump_stream, "\n");
+	            }
+	        }
+	      insn = spill_candidate[i].reload_insn;
+	      NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
+	      PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
+	      NEXT_INSN (insn) = loop_start;
+	      PREV_INSN (insn) = PREV_INSN (loop_start);
+	      NEXT_INSN (PREV_INSN (loop_start)) = insn;
+	      PREV_INSN (loop_start) = insn;
+	      if (INSN_UID (insn) <= max_uid_for_loop)
+		{
+		  insns_moved_out[INSN_UID (insn)] = 1;
+		}
+	      if (spill_candidate[i].live_at_fall_out 
+		  && spill_candidate[i].slot_updated_in_loop)
+		{
+		  emit_insn_after (gen_rtx (SET, 0, spill_candidate[i].reload_slot,
+					    spill_candidate[i].hard_reg),
+				   loop_end);
+		}
+	    }
+	}
+      else
+	{
+	  spill_candidate[i].disregard = 1;
+	  if (spill_candidate[i].has_link && spill_candidate[i].is_head)
+	    {  /* invalidate the whole chain */
+	      link_cand = spill_candidate[i].link_cand;
+	      while (link_cand)
+		{
+		  link_cand->disregard = 1;
+		  link_cand = link_cand->link_cand;
+		}
+	    }
+	}
+    }
+  /* Where ever a reload_slot that is contained is a valid candidate
+     appears in the loop - replace it with that hard_reg */
+  insn = loop_start;
+  while (insn != loop_end)
+    {
+      if (GET_CODE (insn) == INSN)
+	{
+          undobuf.num_undo = 0;
+          undobuf.storage = (char *) oballoc (0);
+	  replace_spill_slots (insn, PATTERN (insn), &PATTERN (insn));
+	  replace_linked_regs (insn, PATTERN (insn));
+	}
+      insn = NEXT_INSN (insn);
+    }
+
+}
+
+
+/* If pat jumps out of the loop then mark all candidates that
+   correspond to pseudos that are alive at the target of the jump,
+   and return 1
+*/
+static
+int 
+check_if_jumps_out_of_loop (pat, do_mark)
+     rtx pat;
+     int do_mark;
+{
+  rtx target;
+  int ret_val = 0;
+  int i;
+
+  switch (GET_CODE (pat))
+    {
+    case PC:
+    case USE:
+    case CLOBBER:
+    case REG:
+    case MEM:
+    case CONST_INT:
+    case CONST_DOUBLE:
+    case RETURN:
+      return (ret_val);
+
+    case CONST:
+      /* There could be a label reference in here.  */
+      return (check_if_jumps_out_of_loop (XEXP (pat, 0), do_mark));
+
+    case PLUS:
+    case MINUS:
+    case MULT:
+    case LSHIFT:
+      ret_val = check_if_jumps_out_of_loop (XEXP (pat, 0), do_mark);
+      ret_val = ret_val | check_if_jumps_out_of_loop (XEXP (pat, 1), do_mark);
+      return (ret_val);
+
+    case SIGN_EXTEND:
+    case ZERO_EXTEND:
+      return (check_if_jumps_out_of_loop (XEXP (pat, 0), do_mark));
+
+    case LABEL_REF:
+      if (LABEL_OUTSIDE_LOOP_P (pat))
+	{ /* This is a jump to outside of loop */
+	  if (do_mark)
+	    {
+	      target = XEXP (pat, 0);
+	      /* Now mark all those pseudo regs not dead at entry
+	         to the target block */
+	      mark_regs_alive_at_exit (target, 0);
+	    }
+	  ret_val = 1;
+	}
+
+      return (ret_val);;
+
+    case SET:
+      /* If this is not setting pc, ignore.  */
+      if (SET_DEST (pat) == pc_rtx)
+	ret_val = check_if_jumps_out_of_loop (SET_SRC (pat), do_mark);
+      return (ret_val);
+
+    case IF_THEN_ELSE:
+      ret_val = check_if_jumps_out_of_loop (XEXP (pat, 1), do_mark);
+      ret_val = ret_val | check_if_jumps_out_of_loop (XEXP (pat, 2), do_mark);
+      return (ret_val);
+
+    case PARALLEL:
+    case ADDR_VEC:
+    case ADDR_DIFF_VEC:
+      all_candidates_invalid = 1;
+      return(1);
+
+    default:
+      /* Nothing else should occur in a JUMP_INSN.  */
+      abort ();
+    }
+}
+
+/*
+  block_head, or the first nonnote insn after block_head (if block_head
+  is a note insn), is the head of a block that is the target of a loop
+  exit. if is_loop_fallout is 1 then the loop exit is the normal end of
+  the loop where the loop falls out, otherwise the loop exit was a jump
+  out of the loop. Any candidates whose pseudos are alive at the
+  start of the block are marked (i.e. the stack slot which
+  corresponds to the pseudo must be updated at this loop exit)
+  if the loop exit is NOT the loop fallout then we mark this
+  candidate as not valid
+*/
+
+static
+void 
+mark_regs_alive_at_exit (block_head, is_loop_fallout)
+     rtx block_head;
+     int is_loop_fallout;
+{
+  int i, found, pseudo_regno, block_num, offset, bit;
+  rtx org_block_head = block_head;
+
+  i = 0;
+  found = 0;
+  /* Find which block block_head is the head of */
+  if (is_loop_fallout)
+    {
+      while (i < n_basic_blocks && !found)
+        {
+          if (basic_block_head[i] == block_head)
+	    {
+	      found = 1;
+	    }
+          else
+	    {
+	      i++;
+	    }
+        }
+    }
+  if (!found)
+    {
+      while (block_head && GET_CODE (block_head) != CODE_LABEL 
+	     && GET_RTX_CLASS (GET_CODE (block_head)) != 'i')
+        {
+          block_head = NEXT_INSN (block_head);
+        }
+      if (block_head == NULL)
+        {
+          if (!is_loop_fallout)
+	    { /* block_head must have been a label upon entry and hence
+                 should not be null now */
+	      abort ();
+	    }
+          return;
+        }
+      i = 0;
+      while (i < n_basic_blocks && !found)
+        {
+          if (basic_block_head[i] == block_head)
+	    {
+	      found = 1;
+	    }
+          else
+	    {
+	      i++;
+	    }
+        }
+    }
+  if (!found)
+    {
+      all_candidates_invalid = 1;
+      return;
+    }
+  block_num = i;
+  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+    {
+      if (spill_candidate[i].reload_slot == NULL)
+        { /* A jump out of the loop before it is known
+             if this slot will become a candidate - so
+             just mark it to never become a candidate.
+             Actually we could remember this jump and
+             mark the candidate accordingly in the future
+             but this seems like too much work */
+          spill_candidate[i].disregard = 1;
+        }
+      else
+      if (spill_candidate[i].disregard == 0 
+	  && spill_candidate[i].reload_slot)
+	{ /* This candidate is still valid */
+	  /* Find the pseudo reg that corresponds to this spill slot */
+	  pseudo_regno = spill_candidate[i].pseudo_reg;
+	  if (pseudo_regno < FIRST_PSEUDO_REGISTER)
+	    {
+	      abort ();
+	    }
+	  /* See if this pseudo reg is alive at the beginning of
+             the block that begins at block_head*/
+	  offset = pseudo_regno / REGSET_ELT_BITS;
+	  bit = 1 << (pseudo_regno % REGSET_ELT_BITS);
+	  if (basic_block_live_at_start[block_num][offset] & bit)
+	    {
+	      if (!is_loop_fallout)
+		{ /* Don't want to handle pseudo's that are alive
+                     at targets of jumps out of the loop */
+		  spill_candidate[i].disregard = 1;
+		  spill_candidate[i].live_at_jump_out = 1;
+		}
+	      else
+		{
+		  spill_candidate[i].live_at_fall_out = 1;
+		}
+	    }
+	}
+    }
+
+}
+
+
+/* 
+  Verfiy that all spill candidates are still valid
+*/
+static
+void 
+verify_spill_candidates (insn, is_loop_exit)
+     rtx insn;
+     int is_loop_exit;
+{
+  int i;
+  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+    {
+      /* intel1a */
+      spill_candidate[i].slot_updated = 0;
+      if (spill_candidate[i].must_update_reload)
+	{
+	  spill_candidate[i].disregard = 1;
+	}
+      if (GET_CODE (insn) == CODE_LABEL)
+	{
+	  spill_candidate[i].first_set_to_reload = 0;
+	}
+    }
+}
+
+#ifndef max
+#define max(a,b) ((a) < (b) ? (b) : (a))
+#endif
+
+/* Update the spill slot candidate info according to what body does */
+static
+void 
+mark_spill_candidates (insn, body)
+     rtx insn;
+     rtx body;
+{
+  int regno, i, dummy, indx, cand_num, j, n_regs;
+
+
+  if (GET_CODE (body) == SET)
+    {
+      if (GET_CODE (SET_DEST (body)) != REG
+          && GET_CODE (SET_DEST (body)) != SUBREG)
+	{
+	  spill_handle_regs_mentioned (SET_DEST (body));
+	}
+      spill_handle_regs_mentioned (SET_SRC (body));
+      if (GET_CODE (SET_DEST (body)) == SUBREG
+           && GET_CODE (SUBREG_REG (SET_DEST (body))) == REG 
+	   && REGNO (SUBREG_REG (SET_DEST (body))) < FIRST_PSEUDO_REGISTER)
+
+	{
+	  regno = REGNO (SUBREG_REG (SET_DEST (body)));
+	  n_regs 
+	    = max (HARD_REGNO_NREGS (regno, GET_MODE (SET_DEST (body))),
+	           HARD_REGNO_NREGS (regno, 
+	                             GET_MODE (SUBREG_REG (SET_DEST (body)))));
+	  for (j = 0; j < n_regs; j++)
+	    {
+	      spill_candidate[regno + j].disregard = 1;
+	      if (spill_candidate[regno + j].reload_indx != -1)
+	        {
+	          reload_slots[spill_candidate[regno + j].
+	              reload_indx].reload_stack_mode = -2;
+	        }
+	    }
+	}
+      else if (GET_CODE (SET_DEST (body)) == REG 
+	       && REGNO (SET_DEST (body)) < FIRST_PSEUDO_REGISTER)
+	{
+	  /* if body sets a hard register it is of interest */
+	  regno = REGNO (SET_DEST (body));
+          n_regs = HARD_REGNO_NREGS (regno, GET_MODE (SET_DEST (body)));
+          if (n_regs > 1)
+            {
+              for (j = 0; j < n_regs; j++)
+                {
+	          spill_candidate[regno + j].disregard = 1;
+                }
+            }
+	  spill_candidate[regno].num_times_set++;
+	  if (GET_CODE (SET_SRC (body)) == MEM 
+	      && is_a_reload_stack_slot (SET_SRC (body), &indx, 0, 0))
+	    { /* It sets it to the value in a reload stack slot 
+	         The stack slot must always be used in the same mode
+                 as it is used to reload the hard register
+              */
+              /* intel1a */
+	      spill_candidate[regno].slot_updated = 0;
+	      if (reload_slots[indx].reload_stack_mode == -1)
+		{
+		  reload_slots[indx].reload_stack_mode 
+		     = GET_MODE (SET_SRC (body));
+		}
+	      else if (reload_slots[indx].reload_stack_mode == -2 
+		       || reload_slots[indx].reload_stack_mode 
+		             != GET_MODE (SET_SRC (body)))
+		{
+		  /* reload slot not always used in same mode */
+		  reload_slots[indx].reload_stack_mode = -2;
+		  spill_candidate[regno].disregard = 1;
+		}
+	      if (!spill_candidate[regno].disregard)
+		{
+		  if (spill_candidate[regno].reload_indx != -1
+		      && spill_candidate[regno].reload_indx != indx)
+		    { /* Same reg loads more than one reload slot -
+                         disregard it */
+		      reload_slots[indx].reload_stack_mode = -2;
+		      reload_slots[spill_candidate[regno].reload_indx].reload_stack_mode = -2;
+		      spill_candidate[regno].disregard = 1;
+		    }
+		  else
+		    {
+			  num_spill_candidates_found++;
+			  spill_candidate[regno].first_set_to_reload = 1;
+			  spill_candidate[regno].reload_slot 
+			    = SET_SRC (body);
+			  spill_candidate[regno].hard_reg 
+			    = SET_DEST (body);
+			  spill_candidate[regno].reload_insn = insn;
+			  spill_candidate[regno].mode 
+			    = GET_MODE (SET_DEST (body));
+			  /* Sanity check */
+			  if (spill_candidate[regno].reload_indx != indx
+			      && spill_candidate[regno].reload_indx != -1)
+			    {
+			      abort ();
+			    }
+			  spill_candidate[regno].reload_indx = indx;
+			  if (spill_candidate[regno].slot_updated_in_loop == 0)
+			    {
+			      spill_candidate[regno].slot_updated_in_loop 
+				= reload_slots[indx].reload_slot_updated;
+			    }
+			  if (spill_candidate[regno].pseudo_reg == 0)
+			    {
+			      spill_candidate[regno].disregard = 1;
+			    }
+		    }
+		}
+	      if (reload_slots[indx].is_loaded_to_reg == -1)
+	        {
+	          if (reload_slots[indx].reload_stack_mode != -2
+	              && spill_candidate[regno].disregard == 0)
+	            {
+		      reload_slots[indx].is_loaded_to_reg = regno;
+		    }
+		}
+	      else if (regno != reload_slots[indx].is_loaded_to_reg)
+		{
+		  int loaded_reg;
+		  loaded_reg = reload_slots[indx].is_loaded_to_reg;
+		  /* Same spill slot already loaded to different hard reg */
+		  /* Create a linked list of candidates that load the
+                     same reload slot */
+		  if (spill_candidate[reload_slots[indx].is_loaded_to_reg].disregard == 0
+		      && GET_MODE (reload_slots[indx].reload_stack_slot) 
+		        == GET_MODE (SET_SRC (body)))
+		    {
+		      if (spill_candidate[regno].has_link == 0)
+			{
+			  spill_candidate[regno].has_link = 1;
+			  spill_candidate[loaded_reg].has_link = 1;
+			  spill_candidate[loaded_reg].is_head = 1;
+			  spill_candidate[regno].link_cand 
+			    = spill_candidate[loaded_reg].link_cand;
+			  spill_candidate[loaded_reg].link_cand 
+			    = &spill_candidate[regno];
+			  spill_candidate[regno].head_cand 
+			    = &spill_candidate[loaded_reg];
+			}
+		    }
+		  else
+		    {
+		      spill_candidate[loaded_reg].disregard = 1;
+		      spill_candidate[regno].disregard = 1;
+		      reload_slots[indx].reload_stack_mode = -2;
+		    }
+		}
+	    }
+	  else
+	    {
+	      /* reg regno is set to some other value than
+                 a spill stack slot */
+	      if (!is_updated_by_const (insn))
+		{
+		  spill_candidate[regno].disregard = 1;
+		  if (spill_candidate[regno].reload_indx != -1)
+		    {
+		      reload_slots[spill_candidate[regno].reload_indx].reload_stack_mode = -2;
+		    }
+		}
+	      /* It sets it to some other value - signal that by
+                 the end of this block that value must have been
+                 stored into the hard registers reload stack slot
+              */
+	      spill_candidate[regno].must_update_reload = 1;
+	    }
+	}
+      else if (is_a_reload_stack_slot (SET_DEST (body), &indx, 0, 0))
+	{ /* This is an update of a reload_stack_slot */
+	  if (GET_CODE (SET_DEST (body)) == SUBREG)
+	    {
+	      reload_slots[indx].reload_stack_mode = -2;
+	    }
+	  reload_slots[indx].reload_slot_updated = 1;
+	  cand_num = reload_slots[indx].is_loaded_to_reg;
+	  /* intel1a */
+	  if (cand_num != -1)
+	    {
+	      spill_candidate[cand_num].slot_updated = 1;
+	    }
+	  if (cand_num == -1)
+	    {
+	      if (!is_updated_by_const_or_reg (insn))
+		{
+		  /* An update before a load - must not
+                     become a candidate */
+		  reload_slots[indx].reload_stack_mode = -2;
+		}
+	    }
+	  else if (GET_CODE (SET_SRC (body)) == REG 
+		   && REGNO (SET_SRC (body)) < FIRST_PSEUDO_REGISTER 
+		   && GET_MODE (SET_SRC (body)) ==
+		   spill_candidate[REGNO (SET_SRC (body))].mode 
+		   && rtx_equal_p (
+	      XEXP (spill_candidate[REGNO (SET_SRC (body))].reload_slot, 0),
+				 XEXP (SET_DEST (body), 0))
+	    )
+	    {
+	      /* It is an update from the appropriate hard reg
+                 and was expected */
+	      spill_candidate[cand_num].must_update_reload = 0;
+	      spill_candidate[cand_num].slot_updated_in_loop = 1;
+	    }
+	  else if (spill_candidate[cand_num].must_update_reload != 0)
+	    { /* It was expected to be updated by the hard
+                 register but it wasn't - the hard register
+                 that has this as a reload stack slot is no
+                 longer to be considered a candidate */
+	      spill_candidate[cand_num].disregard = 1;
+	      if (spill_candidate[cand_num].reload_indx != -1)
+	        {
+		  reload_slots[spill_candidate[cand_num].reload_indx].reload_stack_mode = -2;
+		}
+	    }
+	  else if (!is_updated_by_const_or_reg (insn))
+	    {
+	      spill_candidate[cand_num].disregard = 1;
+	      if (spill_candidate[cand_num].reload_indx != -1)
+	        {
+		  reload_slots[spill_candidate[cand_num].reload_indx].reload_stack_mode = -2;
+		}
+	    }
+	  else
+	    {
+	      spill_candidate[cand_num].slot_updated_in_loop = 1;
+	    }
+	}
+    }
+  else if (GET_CODE (body) == CLOBBER)
+    {
+      if (GET_CODE (SET_DEST (body)) == REG 
+	  && REGNO (SET_DEST (body)) < FIRST_PSEUDO_REGISTER)
+	{
+	  regno = REGNO (SET_DEST (body));
+	  n_regs = HARD_REGNO_NREGS (regno, GET_MODE (SET_DEST (body)));
+	  for (j = 0; j < n_regs; j++)
+	    {
+	      spill_candidate[regno + j].disregard = 1;
+	      if (spill_candidate[regno + j].reload_indx != -1)
+	        {
+	          reload_slots[spill_candidate[regno + j].
+	              reload_indx].reload_stack_mode = -2;
+	        }
+	    }
+	}
+      else if (GET_CODE (SET_DEST (body)) == SUBREG
+               && GET_CODE (SUBREG_REG (SET_DEST (body))) == REG 
+	       && REGNO (SUBREG_REG (SET_DEST (body))) < FIRST_PSEUDO_REGISTER)
+
+	{
+	  regno = REGNO (SUBREG_REG (SET_DEST (body)));
+	  n_regs 
+	    = max (HARD_REGNO_NREGS (regno, GET_MODE (SET_DEST (body))),
+	           HARD_REGNO_NREGS (regno, 
+	                             GET_MODE (SUBREG_REG (SET_DEST (body)))));
+	  for (j = 0; j < n_regs; j++)
+	    {
+	      spill_candidate[regno + j].disregard = 1;
+	      if (spill_candidate[regno + j].reload_indx != -1)
+	        {
+	          reload_slots[spill_candidate[regno + j].
+	              reload_indx].reload_stack_mode = -2;
+	        }
+	    }
+	}
+    }
+  else if (GET_CODE (body) == PARALLEL)
+    {
+      for (i = 0; i < XVECLEN (body, 0); i++)
+	mark_spill_candidates (insn, XVECEXP (body, 0, i));
+    }
+  else
+    {
+      all_candidates_invalid = 1;
+    }
+}
+
+
+/*
+  Called to mark cnadidates that are invalid at this point */
+static
+void 
+spill_handle_regs_mentioned (pat)
+     rtx pat;
+{
+  register char *fmt;
+  register int i;
+  register enum rtx_code code;
+  int indx;
+
+  code = GET_CODE (pat);
+
+  switch (code)
+    {
+    case REG:
+      if (REGNO (pat) < FIRST_PSEUDO_REGISTER)
+	{
+	  /* intel1a */
+	  if (spill_candidate[REGNO (pat)].slot_updated)
+	    {
+	      spill_candidate[REGNO (pat)].disregard = 1;
+	      for (i=0; i < num_reload_stack_slots; i++)
+	        {
+	          if (reload_slots[i].is_loaded_to_reg == REGNO (pat))
+	            {
+	              reload_slots[i].reload_stack_mode = -2;
+	            }
+	        }
+	    }
+	  if (!spill_candidate[REGNO (pat)].first_set_to_reload)
+	    {
+	      spill_candidate[REGNO (pat)].disregard = 1;
+	      for (i=0; i < num_reload_stack_slots; i++)
+	        {
+	          if (reload_slots[i].is_loaded_to_reg == REGNO (pat))
+	            {
+	              reload_slots[i].reload_stack_mode = -2;
+	            }
+	        }
+	    }
+	}
+      return;
+
+      /* These codes have no constituent expressions
+	 and are unique.  */
+    case SCRATCH:
+    case CC0:
+    case PC:
+    case QUEUED:
+    case CONST_INT:
+    case CONST_DOUBLE:
+    case SYMBOL_REF:
+    case CODE_LABEL:
+      return;
+
+
+    }
+  /* The reload stack slot must always be accessed in the same mode */
+  if ((GET_CODE (pat) == MEM || GET_CODE (pat) == SUBREG)
+      && is_a_reload_stack_slot (pat, &indx, 0, 0))
+    {
+      if (GET_CODE (pat) == SUBREG)
+        {
+	  /* Signal invalid */
+	  reload_slots[indx].reload_stack_mode = -2;
+        }
+      else if (reload_slots[indx].reload_stack_mode == -1)
+	{
+	  reload_slots[indx].reload_stack_mode = GET_MODE (pat);
+	}
+      else if (reload_slots[indx].reload_stack_mode != GET_MODE (pat))
+	{
+	  /* Signal invalid */
+	  reload_slots[indx].reload_stack_mode = -2;
+	}
+    }
+  fmt = GET_RTX_FORMAT (code);
+
+  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+    {
+      if (fmt[i] == 'E')
+	{
+	  register int j;
+	  for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
+	    spill_handle_regs_mentioned (XVECEXP (pat, i, j));
+	}
+      else if (fmt[i] == 'e')
+	spill_handle_regs_mentioned (XEXP (pat, i));
+    }
+}
+
+
+/*
+  Return 1 if insn updates a value by a constant value */
+static
+int 
+is_updated_by_const (insn)
+     rtx insn;
+{
+  if (GET_CODE (PATTERN (insn)) != SET)
+    {
+      return (0);
+    }
+  if (GET_RTX_LENGTH (GET_CODE (SET_SRC (PATTERN (insn)))) != 2)
+    {
+      return (0);
+    }
+  if (!rtx_equal_p (XEXP (SET_SRC (PATTERN (insn)), 0),
+		    SET_DEST (PATTERN (insn))))
+    {
+      return (0);
+    }
+  if (GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 1)) != CONST_INT)
+    {
+      return (0);
+    }
+  return (1);
+}
+
+
+/*
+  Return 1 if insn updates a value by a constant value or register */
+static
+int 
+is_updated_by_const_or_reg (insn)
+     rtx insn;
+{
+  if (GET_CODE (PATTERN (insn)) != SET)
+    {
+      return (0);
+    }
+  if (GET_RTX_LENGTH (GET_CODE (SET_SRC (PATTERN (insn)))) != 2)
+    {
+      return (0);
+    }
+  if (!rtx_equal_p (XEXP (SET_SRC (PATTERN (insn)), 0),
+		    SET_DEST (PATTERN (insn))))
+    {
+      return (0);
+    }
+  if (GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 1)) != CONST_INT
+      && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 1)) != REG)
+    {
+      return (0);
+    }
+  return (1);
+}
+
+
+/* Go over the whole function and do
+
+   spill_slotA <- regY                     spill_slotA <- regY
+        .  sequence of code not                 .  sequence of code not
+        .  affecting regY or       =>           .  affecting regY or
+        .  spill_slotA                          .  spill_slotA
+   regX <- spill_slotA                     regX <- regY
+*/
+void 
+peep_spills (f, dumpfile)
+     rtx f;
+     FILE * dumpfile;
+{
+  rtx insn, next, note;
+  int i, indx, insn_code_number, success;
+
+  undobuf.num_undo = 0;
+  num_reload_stack_slots = 0;
+  cur_stack_offset = 0;
+  bzero (spill_candidate, FIRST_PSEUDO_REGISTER * sizeof (spill_candidate[0]));
+  loop_dump_stream = dumpfile;
+  if (loop_dump_stream)
+    {
+      fprintf (loop_dump_stream, "\n\nDoing peep spills\n\n");
+    }
+  insn = f;
+  while (insn)
+    {
+      if (GET_CODE (insn) == INSN && RTX_IS_SPILL_P (insn) 
+	  && GET_CODE (SET_SRC (PATTERN (insn))) == MEM 
+	  && is_a_stack_slot (SET_SRC (PATTERN (insn)))
+	  && !is_a_reload_stack_slot (SET_SRC (PATTERN (insn)), &indx,
+	                              cur_stack_offset, 0) )
+	{	
+	  if (num_reload_stack_slots >= MAX_RELOAD_STACK_SLOTS)
+	    {
+	      return;
+	    }
+	  if (loop_dump_stream)
+	    {
+	      fprintf (loop_dump_stream, "reload slot at insn %d offset %d %d %d\n",
+	      INSN_UID (insn), cur_stack_offset,
+	      RTX_IS_SPILL_P (SET_SRC (PATTERN (insn))),
+	      RTX_IS_SPILL_P (XEXP (SET_SRC (PATTERN (insn)), 0)));
+	    }
+	  reload_slots[num_reload_stack_slots].is_loaded_to_reg = -1;
+	  reload_slots[num_reload_stack_slots].last_store = NULL;
+	  reload_slots[num_reload_stack_slots].cur_stack_offset 
+	    = cur_stack_offset;
+	  reload_slots[num_reload_stack_slots].reload_stack_slot 
+	    = SET_SRC (PATTERN (insn));
+	  reload_slots[num_reload_stack_slots++].reload_insn = insn; 
+	}
+      else if (GET_CODE (insn) == INSN && RTX_IS_SPILL_P (insn) 
+	  && GET_CODE (SET_DEST (PATTERN (insn))) == MEM 
+	  && is_a_stack_slot (SET_DEST (PATTERN (insn)))
+	  && !is_a_reload_stack_slot (SET_DEST (PATTERN (insn)), &indx,
+	                              cur_stack_offset, 0) )
+	{	
+	  if (num_reload_stack_slots >= MAX_RELOAD_STACK_SLOTS)
+	    {
+	      return;
+	    }
+	  if (loop_dump_stream)
+	    {
+	      fprintf (loop_dump_stream, "reload slot at insn %d offset %d\n",
+	      INSN_UID (insn), cur_stack_offset);
+	    }
+	  reload_slots[num_reload_stack_slots].is_loaded_to_reg = -1;
+	  reload_slots[num_reload_stack_slots].last_store = NULL;
+	  reload_slots[num_reload_stack_slots].cur_stack_offset 
+	    = cur_stack_offset;
+	  reload_slots[num_reload_stack_slots].reload_stack_slot 
+	    = SET_DEST (PATTERN (insn));
+	  reload_slots[num_reload_stack_slots++].reload_insn = insn; 
+	}
+      if (GET_CODE (insn) == INSN)
+	{
+	  if (GET_CODE (PATTERN (insn)) == SET)
+	    update_stack_offset (PATTERN (insn), &cur_stack_offset);
+	  else if (GET_CODE (PATTERN (insn)) == PARALLEL)
+	    {
+	      for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
+		update_stack_offset (XVECEXP (PATTERN (insn), 0, i), 
+		                     &cur_stack_offset);
+	    }
+	}
+      insn = NEXT_INSN (insn);
+    }
+  cur_stack_offset = 0;
+  insn = f;
+  while (insn)
+    {
+      if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
+	{
+	  spill_peep_insn (insn, PATTERN (insn));
+	  if (have_flow_analysis 
+		&& GET_CODE (PATTERN (insn)) == SET
+		&& GET_CODE (SET_DEST (PATTERN (insn))) == REG
+		&& GET_CODE (SET_SRC (PATTERN (insn))) == REG
+		&& (next = next_nonnote_insn (insn))
+		&& GET_CODE (next) == INSN
+		&& GET_CODE (next) == INSN
+		&& (note = find_regno_note (next, 
+		                    REG_DEAD, 
+		                    REGNO (SET_DEST (PATTERN (insn)))))
+		&& rtx_equal_p (XEXP (note, 0), SET_DEST (PATTERN (insn)))
+	     )
+            { /* we have reg1 <- reg2 and reg1 dead in next insn
+              replace reg1 with reg2 in next insn and delete this
+              insn */
+              init_undo_buf ();
+              subst_in_insn (next,
+                             PATTERN (next),
+                             SET_DEST (PATTERN (insn)),
+                             SET_SRC (PATTERN (insn)),
+                             0,
+                             0);
+              if (reg_overlap_mentioned_p (XEXP (note, 0), PATTERN (next))
+                  || (insn_code_number = recog (PATTERN (next), next, 0)) < 0)
+                {
+                  loop_undo_all ();
+                  success = 0;
+                }
+              else
+                {
+                  success = 1;
+#ifdef REGISTER_CONSTRAINTS
+                  INSN_CODE (next) = insn_code_number;
+                  insn_extract (next);
+                  if (!constrain_operands (insn_code_number, 1))
+                    {
+                      loop_undo_all ();
+                      INSN_CODE (next) 
+                        = recog (PATTERN (next), 
+                                 next, 0);
+                      success = 0;
+                    }
+#endif
+                  if (success)
+                    {
+                      if (loop_dump_stream)
+                        {
+                          fprintf (loop_dump_stream,
+                          "replace reg %d with reg %d in insn %d, delete insn %d\n",
+                          REGNO (SET_DEST (PATTERN (insn))),
+                          REGNO (SET_SRC (PATTERN (insn))),
+                          INSN_UID (next), INSN_UID (insn));
+                        }
+		      PUT_CODE (insn, NOTE);
+		      NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
+		      NOTE_SOURCE_FILE (insn) = 0;
+		      remove_note (next, note);
+                    }
+                }
+            }
+        }
+      else if (GET_CODE (insn) == CODE_LABEL)
+	{
+	  peep_init_info ();
+	}
+      insn = NEXT_INSN (insn);
+    }
+  have_flow_analysis = 0;
+}
+
+static
+void 
+peep_init_info ()
+{
+  int i;
+  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+    {
+      spill_candidate[i].reload_slot = 0;
+      spill_candidate[i].disregard = 0;
+    }
+  for (i=0; i < num_reload_stack_slots; i++)
+    {
+      reload_slots[i].is_loaded_to_reg = -1;
+      reload_slots[i].last_store = NULL;
+    }
+}
+
+
+/*
+  In body of insn replace any reload stack slots with registers that
+  have the same value
+*/
+static
+void 
+spill_peep_insn (insn, body)
+     rtx insn;
+     rtx body;
+{
+  enum rtx_code code;
+  int i, j, indx, regno, cand_num, insn_code_number, cur_code_number, success,
+      n_regs;
+
+  undobuf.num_undo = 0;
+  code = GET_CODE (body);
+
+  if (code == SET)
+    {
+    
+      if (/*cur_stack_offset == 0*/ 1)
+	{
+	  if (GET_CODE (SET_SRC (body)) == MEM 
+	      && is_a_reload_stack_slot (SET_SRC (body), &indx, cur_stack_offset, 0))
+	    {
+	      cand_num = reload_slots[indx].is_loaded_to_reg;
+	      if (cand_num != -1 && spill_candidate[cand_num].disregard == 0 
+		  && spill_candidate[cand_num].reload_slot 
+		  && GET_MODE (spill_candidate[cand_num].reload_slot)
+		       == GET_MODE (SET_SRC (body))
+		  && are_same_reload_slots (spill_candidate[cand_num].reload_slot,
+		               spill_candidate[cand_num].cur_stack_offset,
+			       SET_SRC (body), cur_stack_offset))
+		{
+		  SET_SRC (body) = spill_candidate[cand_num].hard_reg;
+		  if ((insn_code_number = recog (PATTERN (insn), insn, 0)) < 0)
+		    {
+		      SET_SRC (body) = spill_candidate[cand_num].reload_slot;
+		    }
+		  else
+		    {
+		      success = 1;
+#ifdef REGISTER_CONSTRAINTS
+		      INSN_CODE (insn) = insn_code_number;
+		      insn_extract (insn);
+		      if (!constrain_operands (insn_code_number, 1))
+			{
+			  SET_SRC (body) 
+			    = spill_candidate[cand_num].reload_slot;
+			  INSN_CODE (insn) = recog (PATTERN (insn), insn, 0);
+			  success = 0;
+			}
+#endif
+		      if (success && loop_dump_stream)
+			{
+			  fprintf (loop_dump_stream,
+			     " replacing stack slot (src) with reg%d in insn %d\n",
+				   REGNO (spill_candidate[cand_num].hard_reg), INSN_UID (insn));
+			}
+		    }
+		}
+	    }
+	  else
+	    {
+              undobuf.storage = (char *) oballoc (0);
+	      replace_spill_slots (insn, SET_SRC (body), &SET_SRC (body));
+	      if (undobuf.num_undo)
+	        {
+		  if ((insn_code_number = recog (PATTERN (insn), insn, 0)) < 0)
+		    {
+		      loop_undo_all ();
+		      if (loop_dump_stream)
+			{
+			   fprintf (loop_dump_stream, "  replacment did not succeed %d\n", INSN_UID (insn));
+			}
+		    }
+#ifdef REGISTER_CONSTRAINTS
+		  else
+		    {
+		      INSN_CODE (insn) = insn_code_number;
+		      insn_extract (insn);
+		      if (!constrain_operands (insn_code_number, 1))
+			{
+			  loop_undo_all ();
+		          INSN_CODE (insn) = recog (PATTERN (insn), insn, 0);
+			  if (loop_dump_stream)
+			    {
+			      fprintf (loop_dump_stream, "  replacment did not succeed %d\n", INSN_UID (insn));
+			    }
+			}
+		    }
+#endif
+                  undobuf.num_undo = 0;
+                }
+	    }
+	}
+      if (GET_CODE (SET_DEST (body)) == REG
+	  && REGNO (SET_DEST (body)) < FIRST_PSEUDO_REGISTER)
+	{
+	  regno = REGNO (SET_DEST (body));
+	  if (HARD_REGNO_NREGS (regno, GET_MODE (SET_DEST (body))) > 1)
+	    {
+	      regno = REGNO (SET_DEST (body));
+	      n_regs = HARD_REGNO_NREGS (regno, GET_MODE (SET_DEST (body)));
+	      for (j = 0; j < n_regs; j++)
+	        {
+		      spill_candidate[regno + j].disregard = 1;
+	              spill_candidate[regno + j].reload_slot = NULL;
+	              for (i=0; i < num_reload_stack_slots; i++)
+	                {
+	                  if (reload_slots[i].is_loaded_to_reg == regno + i)
+	                    {
+	                      reload_slots[i].is_loaded_to_reg = -1;
+	                    }
+	                }
+	        }
+	    }
+	  if (GET_CODE (SET_SRC (body)) == MEM 
+	      && is_a_reload_stack_slot (SET_SRC (body), &indx, cur_stack_offset, 0) 
+	      && HARD_REGNO_NREGS (regno, GET_MODE (SET_DEST (body))) == 1)
+	    { /* It sets it to the value in a reload stack slot */
+	      spill_candidate[regno].reload_slot = SET_SRC (body);
+	      spill_candidate[regno].hard_reg = SET_DEST (body);
+	      spill_candidate[regno].disregard = 0;
+	      spill_candidate[regno].reload_insn = insn;
+	      spill_candidate[regno].cur_stack_offset = cur_stack_offset;
+              reload_slots[indx].last_store = NULL;
+	      reload_slots[indx].is_loaded_to_reg = regno;
+	    }
+	  else
+	    {
+	      spill_candidate[regno].disregard = 1;
+	      spill_candidate[regno].reload_slot = NULL;
+	      for (i=0; i < num_reload_stack_slots; i++)
+	        {
+	          if (reload_slots[i].is_loaded_to_reg == regno)
+	            {
+	              reload_slots[i].is_loaded_to_reg = -1;
+	            }
+	        }
+	    }
+	}
+      else if (GET_CODE (SET_DEST (body)) == SUBREG
+               && GET_CODE (SUBREG_REG (SET_DEST (body))) == REG
+	       && REGNO (SUBREG_REG (SET_DEST (body))) < FIRST_PSEUDO_REGISTER)
+	{ /* Simple handling of subregs - invalidate the subreg being set */
+	  regno = REGNO (SUBREG_REG (SET_DEST (body)));
+	  n_regs = HARD_REGNO_NREGS (regno, GET_MODE (SET_DEST (body)));
+	  for (j = 0; j < n_regs; j++)
+	    {
+		  spill_candidate[regno + j].disregard = 1;
+	          spill_candidate[regno + j].reload_slot = NULL;
+	          for (i=0; i < num_reload_stack_slots; i++)
+	            {
+	              if (reload_slots[i].is_loaded_to_reg == regno + i)
+	                {
+	                  reload_slots[i].is_loaded_to_reg = -1;
+	                }
+	            }
+	    }
+	}
+      else if (is_a_reload_stack_slot (SET_DEST (body), &indx, cur_stack_offset, 0))
+	{ /* This is an update of a reload_stack_slot */
+              /* Check if last write into this reload slot can be deleted */
+              if (reload_slots[indx].last_store
+                  && GET_CODE (SET_DEST (body)) != SUBREG
+                  /* && GET_CODE (SET_SRC (body)) == REG */
+		  && REGNO (SET_SRC (body)) < FIRST_PSEUDO_REGISTER
+ 	          && GET_MODE (SET_DEST ( PATTERN (reload_slots[indx].last_store)))
+	              == GET_MODE (SET_DEST (body))
+                  && spill_slot_unused_between (
+                      SET_DEST ( PATTERN (reload_slots[indx].last_store)),
+                      reload_slots[indx].last_store, insn))
+                {
+                  if (loop_dump_stream)
+                    {
+                      fprintf (loop_dump_stream, "delete redundant spill store at %d becuase of re-store at %d\n",
+                               INSN_UID (reload_slots[indx].last_store),
+                               INSN_UID (insn));
+                    }
+		  PUT_CODE (reload_slots[indx].last_store, NOTE);
+		  NOTE_LINE_NUMBER (reload_slots[indx].last_store) = NOTE_INSN_DELETED;
+		  NOTE_SOURCE_FILE (reload_slots[indx].last_store) = 0;
+		  reload_slots[indx].is_loaded_to_reg = -1;
+		  reload_slots[indx].last_store = NULL;
+                 }
+	      if (GET_CODE (SET_SRC (body)) == REG 
+                  && GET_CODE (SET_DEST (body)) != SUBREG
+	          &&HARD_REGNO_NREGS(REGNO(SET_SRC(body)),
+			  		GET_MODE(SET_DEST(body))) == 1
+		  && REGNO (SET_SRC (body)) < FIRST_PSEUDO_REGISTER)
+		{
+		  regno = REGNO (SET_SRC (body));
+		  spill_candidate[regno].reload_slot = SET_DEST (body);
+		  spill_candidate[regno].hard_reg = SET_SRC (body);
+		  spill_candidate[regno].disregard = 0;
+		  spill_candidate[regno].reload_insn = insn;
+        	  spill_candidate[regno].cur_stack_offset = cur_stack_offset;
+        	  reload_slots[indx].last_store = insn;
+		  reload_slots[indx].is_loaded_to_reg = regno;
+		}
+	      else
+	        {
+                  regno = reload_slots[indx].is_loaded_to_reg;
+                  if (regno != -1)
+                    { /* This candidate is now invalid */
+		       spill_candidate[regno].disregard = 1;
+		       spill_candidate[regno].reload_slot = NULL;
+                    }
+		  reload_slots[indx].is_loaded_to_reg = -1;
+		  reload_slots[indx].last_store = NULL;
+	        }
+	}
+      update_stack_offset (body, &cur_stack_offset);
+    }
+  else if (code == CLOBBER)
+    {
+      if (GET_CODE (SET_DEST (body)) == REG 
+	  && REGNO (SET_DEST (body)) < FIRST_PSEUDO_REGISTER)
+	{
+	  regno = REGNO (SET_DEST (body));
+	  n_regs = HARD_REGNO_NREGS (regno, GET_MODE (SET_DEST (body)));
+	  for (j = 0; j < n_regs; j++)
+	    {
+	      spill_candidate[regno + j].disregard = 1;
+	      for (i=0; i < num_reload_stack_slots; i++)
+	        {
+	          if (reload_slots[i].is_loaded_to_reg == (regno + j))
+	            {
+	              reload_slots[i].is_loaded_to_reg = -1;
+	            }
+	        }
+	    }
+	}
+      else if (GET_CODE (SET_DEST (body)) == SUBREG
+               && GET_CODE (SUBREG_REG (SET_DEST (body))) == REG 
+	       && REGNO (SUBREG_REG (SET_DEST (body))) < FIRST_PSEUDO_REGISTER)
+	{
+	  regno = REGNO (SUBREG_REG (SET_DEST (body)));
+	  n_regs 
+	    = max (HARD_REGNO_NREGS (regno, GET_MODE (SET_DEST (body))),
+	           HARD_REGNO_NREGS (regno, 
+	                             GET_MODE (SUBREG_REG (SET_DEST (body)))));
+	  for (j = 0; j < n_regs; j++)
+	    {
+	      spill_candidate[regno + j].disregard = 1;
+	      for (i=0; i < num_reload_stack_slots; i++)
+	        {
+	          if (reload_slots[i].is_loaded_to_reg == (regno + j))
+	            {
+	              reload_slots[i].is_loaded_to_reg = -1;
+	            }
+	        }
+	    }
+	}
+      else if (is_a_reload_stack_slot (SET_DEST (body), &indx, cur_stack_offset, 0))
+        {
+          regno = reload_slots[indx].is_loaded_to_reg;
+          if (regno != -1)
+            { /* This candidate is now invalid */
+		spill_candidate[regno].disregard = 1;
+		spill_candidate[regno].reload_slot = NULL;
+	    }
+          reload_slots[indx].is_loaded_to_reg = -1;
+	  reload_slots[indx].last_store = NULL;
+        }
+    }
+  if (code == PARALLEL)
+    {
+      for (i = 0; i < XVECLEN (body, 0); i++)
+	spill_peep_insn (insn, XVECEXP (body, 0, i));
+    }
+  if (GET_CODE (insn) == CALL_INSN)
+    { /* All call clobbered registers are no longer valid */
+      for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+	{
+	  if (call_used_regs[i])
+	    {
+	      spill_candidate[i].disregard = 1;
+	      for (j=0; j < num_reload_stack_slots; j++)
+	        {
+	          if (reload_slots[j].is_loaded_to_reg == i)
+	            {
+	              reload_slots[j].is_loaded_to_reg = -1;
+	            }
+	        }
+	    }
+	}
+    }
+}
+
+/*
+  Return 1 iff we are sure that the spill_slot  (or any subpart of it)
+  is not refernced between start and end.  Also there must be no 
+  CALL JUMP or LABELs in between them
+*/
+static
+int
+spill_slot_unused_between (spill_slot, start, end)
+  rtx spill_slot, start, end;
+{
+  rtx tinsn;
+  int mcur_stack_offset = 0;
+
+  for (tinsn = next_nonnote_insn (start);
+       tinsn && tinsn != end;
+       tinsn = next_nonnote_insn (tinsn))
+    {
+      if (GET_CODE (tinsn) == CALL_INSN || GET_CODE (tinsn) == JUMP_INSN 
+          || GET_CODE (tinsn) == CODE_LABEL)
+        {
+          return (0);
+        }
+      if (spill_slot_mentioned(spill_slot, PATTERN (tinsn), mcur_stack_offset))
+        {
+          return (0);
+        }
+      update_stack_offset (PATTERN (tinsn), &mcur_stack_offset);
+    }
+  return (1);
+}
+
+/*
+  Return 1 if spill_slot or any part of it is mentioned in pat.
+  relative_stack_offset is the offset of the stack pointer relative
+  to the point at which spill_slot was stored into.  
+*/
+
+static int
+spill_slot_mentioned (spill_slot, pat, relative_stack_offset)
+     rtx pat, spill_slot;
+     int relative_stack_offset;
+{
+  register char *fmt;
+  register int i;
+  register enum rtx_code code;
+
+  code = GET_CODE (pat);
+
+  switch (code)
+    {
+      /* These codes have no constituent expressions
+	 and are unique.  */
+    case REG:
+    case SCRATCH:
+    case CC0:
+    case PC:
+    case QUEUED:
+    case CONST_INT:
+    case CONST_DOUBLE:
+    case SYMBOL_REF:
+    case CODE_LABEL:
+      return (0);
+
+    case MEM:
+      if (is_a_stack_slot (pat)
+          && are_same_reload_slots (spill_slot, 0, pat, relative_stack_offset))
+        {
+          return (1);
+        }
+      return (0);
+
+    }
+
+
+  fmt = GET_RTX_FORMAT (code);
+
+  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+    {
+      if (fmt[i] == 'E')
+	{
+	  register int j;
+	  for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
+	    if (spill_slot_mentioned (spill_slot, XVECEXP (pat, i, j),
+	                              relative_stack_offset))
+	      {
+	        return (1);
+	      }
+	}
+      else if (fmt[i] == 'e')
+	if (spill_slot_mentioned (spill_slot, XEXP (pat, i),
+	                              relative_stack_offset))
+	  {
+	    return (1);
+	  }
+    }
+  return (0);
+}
+
+
+/*
+  Keep track of the depth of the stack
+*/
+/* static */
+void 
+update_stack_offset (pat, addr_stack_offset)
+     rtx pat;
+     int *addr_stack_offset;
+{
+  int i;
+  if (GET_CODE (pat) != SET)
+    {
+      return;
+    }
+  if (GET_CODE (SET_DEST (pat)) == REG
+      && XINT (SET_DEST (pat), 0) == STACK_POINTER_REGNUM
+      && GET_CODE (SET_SRC (pat)) == PLUS
+      && GET_CODE (XEXP (SET_SRC (pat), 0)) == REG
+      && XINT (XEXP (SET_SRC (pat), 0), 0) == STACK_POINTER_REGNUM)
+    {
+      *addr_stack_offset -= XINT (XEXP (SET_SRC (pat), 1), 0);
+    }
+  else if (GET_CODE (SET_DEST (pat)) == MEM 
+	   && GET_CODE (XEXP (SET_DEST (pat), 0)) == PRE_DEC
+	   && XEXP (XEXP (SET_DEST (pat), 0), 0) == stack_pointer_rtx)
+    {
+      spill_candidate[STACK_POINTER_REGNUM].disregard = 1;
+      for (i=0; i < num_reload_stack_slots; i++)
+	{
+	  if (reload_slots[i].is_loaded_to_reg == STACK_POINTER_REGNUM)
+	    {
+	      reload_slots[i].is_loaded_to_reg = -1;
+	    }
+	}
+      *addr_stack_offset += GET_MODE_SIZE (GET_MODE (SET_DEST (pat)));
+    }
+  else if (GET_CODE (SET_DEST (pat)) == MEM 
+	   && GET_CODE (XEXP (SET_DEST (pat), 0)) == PRE_INC
+	   && XEXP (XEXP (SET_DEST (pat), 0), 0) == stack_pointer_rtx)
+    {
+      spill_candidate[STACK_POINTER_REGNUM].disregard = 1;
+      for (i=0; i < num_reload_stack_slots; i++)
+	{
+	  if (reload_slots[i].is_loaded_to_reg == STACK_POINTER_REGNUM)
+	    {
+	      reload_slots[i].is_loaded_to_reg = -1;
+	    }
+	}
+      *addr_stack_offset -= GET_MODE_SIZE (GET_MODE (SET_DEST (pat)));
+    }
+}
+
+
+/*
+  Replace stack spill slots in pat of insn with the appropriate spill
+  candidate
+*/
+static
+void
+replace_spill_slots (insn, pat, where)
+     rtx insn;
+     rtx pat;
+     rtx *where;
+{
+  register RTX_CODE code = GET_CODE (pat);
+  register int i, j;
+  register char *fmt;
+  int cand_num, indx;
+  rtx note;
+
+  switch (code)
+    {
+    case HIGH:
+    case CONST_INT:
+    case CONST:
+    case CONST_DOUBLE:
+    case SYMBOL_REF:
+    case LABEL_REF:
+    case PC:
+    case CC0:
+    case REG:
+      return;
+
+    default:
+      break;
+    }
+  if (GET_CODE (pat) == MEM && is_a_reload_stack_slot (pat, &indx, cur_stack_offset, 0))
+    {
+      cand_num = reload_slots[indx].is_loaded_to_reg;
+      if (cand_num != -1 && spill_candidate[cand_num].disregard == 0 
+	  && spill_candidate[cand_num].reload_slot 
+	  && GET_MODE (spill_candidate[cand_num].reload_slot)
+	       == GET_MODE (pat)
+	  && are_same_reload_slots (spill_candidate[cand_num].reload_slot,
+	                            spill_candidate[cand_num].cur_stack_offset,
+	                            pat, cur_stack_offset))
+	{
+	  note = find_reg_note (spill_candidate[cand_num].reload_insn,
+				REG_DEAD,
+				spill_candidate[cand_num].hard_reg);
+	  if (note)
+	    {
+	      remove_note (spill_candidate[cand_num].reload_insn, note);
+	    }
+	  if (loop_dump_stream)
+	    {
+	      fprintf (loop_dump_stream, " replacing stack slot with reg%d in insn %d\n",
+	       REGNO (spill_candidate[cand_num].hard_reg), INSN_UID (insn));
+	    }
+	  LOOP_SUBST (where, spill_candidate[cand_num].hard_reg);
+	}
+    }
+
+  fmt = GET_RTX_FORMAT (code);
+  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+    if (fmt[i] == 'e')
+      replace_spill_slots (insn, XEXP (pat, i), &XEXP (pat, i));
+    else if (fmt[i] == 'E' || fmt[i] == 'V')
+      {
+	for (j = 0; j < XVECLEN (pat, i); j++)
+	  replace_spill_slots (insn, XVECEXP (pat, i, j), &XVECEXP (pat, i, j));
+      }
+}
+
+/*
+  Replace any hard registers in pat of insn, that are on a linked
+  list of spill candidates, with the head candidate of the list
+*/
+static
+rtx 
+replace_linked_regs (insn, pat)
+     rtx insn;
+     rtx pat;
+{
+  register RTX_CODE code = GET_CODE (pat);
+  register int i, j;
+  register char *fmt;
+  int cand_num, indx;
+  rtx note;
+
+  switch (code)
+    {
+    case HIGH:
+    case CONST_INT:
+    case CONST:
+    case CONST_DOUBLE:
+    case SYMBOL_REF:
+    case LABEL_REF:
+    case PC:
+    case CC0:
+      return pat;
+
+    case REG:
+      if (spill_candidate[REGNO (pat)].head_cand 
+	  && (spill_candidate[REGNO (pat)].head_cand)->disregard == 0)
+	{
+	  if (loop_dump_stream)
+	    {
+	      fprintf (loop_dump_stream, " replacing reg%d with reg%d in insn %d\n",
+		       REGNO (pat),
+		 REGNO ((spill_candidate[REGNO (pat)].head_cand)->hard_reg),
+		       INSN_UID (insn));
+	    }
+	  return ((spill_candidate[REGNO (pat)].head_cand)->hard_reg);
+	}
+      else
+	return pat;
+
+    default:
+      break;
+    }
+
+  fmt = GET_RTX_FORMAT (code);
+  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+    if (fmt[i] == 'e')
+      XEXP (pat, i) = replace_linked_regs (insn, XEXP (pat, i));
+    else if (fmt[i] == 'E' || fmt[i] == 'V')
+      {
+	for (j = 0; j < XVECLEN (pat, i); j++)
+	  XVECEXP (pat, i, j) 
+	    = replace_linked_regs (insn, XVECEXP (pat, i, j));
+      }
+  return pat;
+}
+
+
+/*
+  Mark all registers mentioned in insns between loop_start and loop_end
+  and that are also mentioned outside of the loop
+*/
+static void
+mark_regs_live_outside (loop_start, loop_end)
+     rtx loop_start;
+     rtx loop_end;
+{
+  rtx insn;
+  int in_loop = 0;
+
+  insn = get_insns ();
+  while (insn)
+    {
+      if (insn == loop_start)
+	{
+	  in_loop = 1;
+	}
+      else if (insn == loop_end)
+	{
+	  in_loop = 0;
+	}
+      else if (in_loop == 0 
+	       && (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN 
+		|| GET_CODE (insn) == JUMP_INSN))
+	{
+	  mark_regs_mentioned (PATTERN (insn), insn);
+	}
+      insn = NEXT_INSN (insn);
+    }
+}
+
+
+/*
+  Each register mentioned in pat, except for the destination register of
+  the insn, is marked as reg_live_outside_loop
+*/
+static void
+mark_regs_mentioned (pat, insn)
+     rtx pat, insn;
+{
+  register char *fmt;
+  register int i;
+  register enum rtx_code code;
+
+  if (GET_CODE (pat) == SET
+      && GET_CODE (SET_DEST (pat)) == REG && is_a_param_slot (SET_SRC (pat)))
+    {
+      return;
+    }
+    
+  code = GET_CODE (pat);
+
+  switch (code)
+    {
+    case REG:
+      if (REGNO (pat) < max_reg_before_loop)
+	{
+	  reg_live_outside_loop[REGNO (pat)] = 1;
+	}
+      return;
+
+      /* These codes have no constituent expressions
+	 and are unique.  */
+    case SCRATCH:
+    case CC0:
+    case PC:
+    case QUEUED:
+    case CONST_INT:
+    case CONST_DOUBLE:
+    case SYMBOL_REF:
+    case CODE_LABEL:
+      return;
+
+
+    }
+
+
+  fmt = GET_RTX_FORMAT (code);
+
+  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+    {
+      if (fmt[i] == 'E')
+	{
+	  register int j;
+	  for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
+	    mark_regs_mentioned (XVECEXP (pat, i, j), insn);
+	}
+      else if (fmt[i] == 'e')
+	mark_regs_mentioned (XEXP (pat, i), insn);
+    }
+}
+
+/* Return 1 iff there is a loop_begin note between loop_start and loop_end
+   otherwise return 0 */
+
+static int
+loop_contains_loop (loop_start, loop_end)
+     rtx loop_start;
+     rtx loop_end;
+{
+  rtx insn;
+
+  insn = NEXT_INSN (loop_start);
+  while (insn && insn != loop_end)
+    {
+      if (GET_CODE (insn) == NOTE
+	  && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
+	{
+	  return (1);
+	}
+      insn = NEXT_INSN (insn);
+    }
+  return (0);
+}
+
+
+/* reload_slots[indx] is a reload slot that was never updated in loop
+   but could not be lifted only because the register it is
+   loaded into was also set to something else in loop.
+   Lets see if the reload slot was set in the basic block
+   just prior to the loop by some inexpensive operation.
+   (particularly a move from memory into a register and
+   a move of that register onto stack). If so lets
+   replace each load of the reload slot in the loop with
+   a load of the memory and delete the code that loaded
+   and spilled it outside the loop.
+   This corrects the preloading of loop invariants that
+   could not be held in registers over the loop
+ */
+static
+void 
+push_load_into_loop (loop_start, loop_end, indx)
+     rtx loop_start;
+     rtx loop_end;
+     int indx;
+{
+  rtx insn, insn_sets_reload_slot, val_in_reload_slot, insns_deleted[2],
+    update_log_links_start, rn, prev, link;
+  int rindx, i, found_set, num_deleted;
+
+  if (loop_dump_stream)
+    {
+      fprintf (loop_dump_stream, "\nTry to push load of pseudo %d into loop\n",
+	       reload_slots[indx].stack_slot_pseudo_reg);
+    }
+  /* Look for insn before the loop that sets this reload slot */
+  insn = PREV_INSN (loop_start);
+  insn_sets_reload_slot = 0;
+  while (insn && !insn_sets_reload_slot)
+    {
+      if (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN 
+	  || GET_CODE (insn) == CODE_LABEL 
+	  || (GET_CODE (insn) == NOTE
+	       && (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG 
+	           || NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END
+	          )
+	     ) 
+	  || (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) != SET))
+	{
+	  break;
+	}
+      else if (GET_CODE (insn) == INSN 
+	       && rtx_equal_p (SET_DEST (PATTERN (insn)), reload_slots[indx].reload_stack_slot))
+	{
+	  insn_sets_reload_slot = insn;
+	}
+      insn = PREV_INSN (insn);
+    }
+  if (!insn_sets_reload_slot)
+    {
+      return;
+    }
+  /* Now see if the source is a register and that register is
+     set by the immediately preceeding insn - then source of
+     the immediately preceeding insn is the value in the reload
+     slot throughout the loop */
+  if (GET_CODE (SET_SRC (PATTERN (insn_sets_reload_slot))) == REG 
+      && GET_CODE (PREV_INSN (insn_sets_reload_slot)) == INSN 
+      && GET_CODE (PATTERN (PREV_INSN (insn_sets_reload_slot))) == SET 
+      && rtx_equal_p (SET_DEST (PATTERN (PREV_INSN (insn_sets_reload_slot))),
+		   SET_SRC (PATTERN (insn_sets_reload_slot))))
+    {
+      val_in_reload_slot = SET_SRC (PATTERN (PREV_INSN (insn_sets_reload_slot)));
+    }
+  else
+    {
+      return;
+    }
+  if (is_a_reload_stack_slot (val_in_reload_slot, &rindx, cur_stack_offset, 0))
+    { /* Don't want to handle these */
+      return;
+    }
+  /* Now make sure that this value is not changed in loop */
+  if (GET_CODE (val_in_reload_slot) != MEM || !invariant_p (val_in_reload_slot))
+    {
+      return;
+    }
+  for (i = loop_store_mems_idx - 1; i >= 0; i--)
+    {
+      if (true_dependence (loop_store_mems[i], val_in_reload_slot) 
+	  && !is_a_reload_stack_slot (loop_store_mems[i], &rindx, cur_stack_offset, 0)
+	)
+	{
+	  return;
+	}
+    }
+  /* Now we know that the value can be substituted and that the store into
+     the reload slot outside the loop (i.e. insn_sets_reload_slot)
+     can be deleted.
+     we also want to delete the load of the reload slot
+     (i.e PREV_INSN(insn_sets_reload_slot)). we can do this if the register
+     loaded (i.e. SET_DEST(PATTERN(PREV_INSN(insn_sets_reload_slot))) is
+     set before used after PREV_INSN(insn_sets_reload_slot))
+  */
+  insn = NEXT_INSN (insn_sets_reload_slot);
+  found_set = 0;
+  while (!found_set && insn && insn != loop_end)
+    {
+      if (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN 
+	  || (GET_CODE (insn) == CODE_LABEL && PREV_INSN (insn) != loop_start))
+	{
+	  break;
+	}
+      if (GET_CODE (insn) == INSN)
+	{
+	  if (reg_overlap_mentioned_p (
+		     SET_DEST (PATTERN (PREV_INSN (insn_sets_reload_slot))),
+					PATTERN (insn)))
+	    {
+	      break;
+	    }
+	  if (GET_CODE (PATTERN (insn)) == SET 
+	      && rtx_equal_p (SET_DEST (PATTERN (insn)),
+		    SET_DEST (PATTERN (PREV_INSN (insn_sets_reload_slot)))))
+	    {
+	      found_set = 1;
+	    }
+	}
+      insn = NEXT_INSN (insn);
+    }
+  /* Do the replacement throughout the loop */
+  if (loop_dump_stream)
+    {
+      fprintf (loop_dump_stream, "replacing reload slot %d with: throughout loop\n",
+	       indx);
+	  tdebug_rtx (val_in_reload_slot, loop_dump_stream);
+    }
+  insn = NEXT_INSN (insn_sets_reload_slot);
+  while (insn != loop_end)
+    {
+      if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN 
+	  || GET_CODE (insn) == JUMP_INSN)
+	{
+          init_undo_buf ();
+	  subst_in_insn (insn, PATTERN (insn),
+			 reload_slots[indx].reload_stack_slot,
+			 val_in_reload_slot, 1, 0);
+
+	}
+      insn = NEXT_INSN (insn);
+    }
+  insns_deleted[0] = NULL;
+  insns_deleted[1] = NULL;
+  num_deleted = 0;
+  update_log_links_start = PREV_INSN (insn_sets_reload_slot);
+  if (found_set)
+    {
+      if (loop_dump_stream)
+	{
+	  fprintf (loop_dump_stream, " delete insn %d\n",
+		   INSN_UID (PREV_INSN (insn_sets_reload_slot)));
+	}
+      insns_deleted[num_deleted++] = PREV_INSN (insn_sets_reload_slot);
+      delete_insn (PREV_INSN (insn_sets_reload_slot));
+    }
+  if (loop_dump_stream)
+    {
+      fprintf (loop_dump_stream, " delete insn %d\n",
+	       INSN_UID (insn_sets_reload_slot));
+    }
+  insns_deleted[num_deleted++] = insn_sets_reload_slot;
+  delete_insn (insn_sets_reload_slot);
+  /* Remove these deleted insns from any log links they are on */
+  for (rn = update_log_links_start; rn != loop_start; rn = NEXT_INSN (rn))
+    {
+      if ((GET_CODE (rn) == INSN || GET_CODE (rn) == JUMP_INSN
+	   || GET_CODE (rn) == CALL_INSN) && LOG_LINKS (rn))
+	{
+	  for (prev = 0, link = LOG_LINKS (rn); link;
+	       prev = link, link = XEXP (link, 1))
+	    {
+	      if (XEXP (link, 0) == insns_deleted[0] 
+		  || (num_deleted == 2 && XEXP (link, 0) == insns_deleted[1]))
+		{
+		  if (prev)
+		    XEXP (prev, 1) = XEXP (link, 1);
+		  else
+		    LOG_LINKS (rn) = XEXP (link, 1);
+		}
+	    }
+	}
+    }
+}
+
+void
+init_undo_buf ()
+{
+  undobuf.storage = (char *) oballoc (0);
+  undobuf.num_undo = 0;
+}
+
+/* In pat of insn replace org with new. If not_dest is 1 then
+   don't do the rplacement if org is ae destination of a SET
+*/
+void 
+subst_in_insn (insn, pat, org, new, not_dest, is_dest)
+     rtx insn, pat, org, new;
+     int not_dest;
+     int is_dest;
+{
+  inner_subst_in_insn (insn, pat, &pat, org, new, not_dest, is_dest);
+}
+
+/* In pat of insn replace org with new. If not_dest is 1 then
+   don't do the rplacement if org is ae destination of a SET
+*/
+static void 
+inner_subst_in_insn (insn, pat, where, org, new, not_dest, is_dest)
+     rtx insn, pat, org, new, *where;
+     int not_dest;
+     int is_dest;
+{
+  register RTX_CODE code = GET_CODE (pat);
+  register int i, j;
+  register char *fmt;
+
+  if (not_dest && is_dest)
+    {
+      return;
+    }
+  switch (code)
+    {
+    case HIGH:
+    case CONST_INT:
+    case CONST:
+    case CONST_DOUBLE:
+    case SYMBOL_REF:
+    case LABEL_REF:
+    case PC:
+    case CC0:
+      return ;
+
+
+    }
+
+  if (rtx_equal_p (pat, org))
+    {
+      LOOP_SUBST (where, new);
+      return;
+    }
+  fmt = GET_RTX_FORMAT (code);
+  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+    if (fmt[i] == 'e')
+      {
+        if (not_dest && code == SET && i == 0)
+          is_dest = 1;
+        else
+          is_dest = 0;
+        if( XEXP (pat, i))
+          inner_subst_in_insn (insn, XEXP (pat, i), &XEXP (pat, i), org, new, not_dest, is_dest);
+      }
+    else if (fmt[i] == 'E' || fmt[i] == 'V')
+      {
+	for (j = 0; j < XVECLEN (pat, i); j++)
+	  inner_subst_in_insn (insn, XVECEXP (pat, i, j), &XVECEXP (pat, i, j), org, new, not_dest, 0);
+      }
+}
+
+
+/* tsl - begin */
+
+/* Indexed by i, each entry indicates the last memory, register i was loaded
+   with, in the current loop (NULL if no reload until now) */
+   
+static rtx last_reloads[FIRST_PSEUDO_REGISTER];
+
+#define LAST_RELOAD(REGNO) last_reloads[(REGNO)]
+
+/* If entry > 0 then the higher it is the less recently used it is.  
+   If entry == 0 then that register number has not been used as reload
+   since last lable.  
+ */
+
+static int reload_priority[FIRST_PSEUDO_REGISTER];
+
+/* Set of registers that are free and ready to be used at this moment.  */
+
+extern HARD_REG_SET free_regs;
+
+extern void update_free_regs (rtx);
+extern int find_free_reg (enum machine_mode);
+static int find_last_reload (rtx);
+
+/* Replaces the reload registers of reload insns as follows:
+
+   for each insn which loads memory into a register,
+   if the reload register is loaded with a memory, which was previously
+   loaded, and the reload register dies in the next insn, we
+   replace the reload register, with that already loaded with the stack slot
+   (assuming that register is free - we use the same free register scanning
+   method of the memory_simplify() function). 
+   If the reload register was already used since the last label or call then
+   try to find a free register which was used less recently and replace the
+   reload register with the register found.  
+   */
+
+void
+replace_reload_registers (f, file)
+     rtx f;
+     FILE *file;
+{
+  HARD_REG_SET saved_free_regs; /* for testing find_free_regs_between () */
+
+  /* indicate wheter we are in a loop now */
+
+  int in_loop_f = 0;
+  int save_code;
+  int i;
+
+  /* make flow_analysis without changing the insns and saving the pseudo
+     registers information in basic_block_live_at_start */
+
+  hard_reg_flow_analysis (f, file, 1 /* save pseudo register information */);
+  have_flow_analysis = 1;
+  bzero (last_reloads, sizeof last_reloads);
+
+  if (n_basic_blocks > 0)
+    {
+      register int regno, block;
+
+      /* To determine which registers are live after any insn, start from
+	 the beginning of the basic block and scan insns, noting
+         which registers are set by each insn and which die there. */
+
+      for (block = 0; block < n_basic_blocks; block++)
+	{
+	  register rtx insn;
+	  int end_of_block_f;
+
+	  if (file)
+	    fprintf (file, "\nblock number: %d:\n", block);
+
+	  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
+	    /* at the beginning of a block, each non-live hard register is
+	       considered free. */
+	    {
+	      register int offset = regno / REGSET_ELT_BITS;
+	      register int bit = 1 << (regno % REGSET_ELT_BITS);
+	      if (basic_block_live_at_start[block][offset] & bit)
+		CLEAR_HARD_REG_BIT (free_regs, regno);
+	      else
+		SET_HARD_REG_BIT (free_regs, regno);
+	    }
+
+	  end_of_block_f = 0;	/* signals the end of block reached */
+
+	  /* Traverse the block, an insn by insn.  Maintain a history
+	     of free registers and registers used to load memory
+	     for use only in next insn (these are called reload_registers).  
+	     At CALLs and CODE_LABELs restart the history of reload_registers.
+	  */
+
+	  for (insn = basic_block_head[block];
+	       ! end_of_block_f;
+	       insn = NEXT_INSN (insn))
+	    {
+	      rtx note, next, pat;
+	      rtx loop_start; /* use to test find_free_regs_between () */
+	      int regno;
+
+	      if (GET_CODE (insn) == CALL_INSN)
+		{
+	          bzero (last_reloads, sizeof last_reloads);
+	          bzero (reload_priority, sizeof reload_priority);
+	        }
+	      if (GET_CODE (insn) == CODE_LABEL)
+		{
+	          bzero (last_reloads, sizeof last_reloads);
+	          bzero (reload_priority, sizeof reload_priority);
+	          loop_start = insn;
+	          if (GET_CODE (PREV_INSN (insn)) == NOTE
+	              && NOTE_LINE_NUMBER (PREV_INSN (insn)) 
+	                == NOTE_INSN_LOOP_BEG)
+	            {
+	              in_loop_f = 1;
+	              saved_free_regs = free_regs;
+	            }
+	        }
+	      if (GET_CODE (insn) == JUMP_INSN
+		  && GET_CODE (NEXT_INSN (insn)) == NOTE
+		  && NOTE_LINE_NUMBER (NEXT_INSN (insn)) == NOTE_INSN_LOOP_END)
+		{
+		  register int regno;
+#if 0
+	          if (in_loop_f)
+		    {
+		      find_free_regs_between (& saved_free_regs,
+		  			      loop_start,
+		  			      insn);
+		      if (file)
+		        {
+		          fprintf (file,
+		      	           "free regs found in loop (insns %d - %d): ",
+		      	           INSN_UID (loop_start), INSN_UID (insn));
+		          for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
+		            if (TEST_HARD_REG_BIT (saved_free_regs, regno))
+		              fprintf (file, "%d ", regno);
+		          fprintf (file, "\n");
+		        }
+		    }
+#endif
+		  in_loop_f = 0;
+		}
+	    
+	      if (/*in_loop_f*/ 1)
+	        {
+		  if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
+		      /*&& RTX_IS_SPILL_P (insn)*/
+		      && (pat = PATTERN (insn))
+	              && GET_CODE (pat) == SET
+	              && GET_CODE (SET_DEST (pat)) == REG
+	              && GET_CODE (SET_SRC (pat)) == MEM)
+	            {
+	              regno = REGNO (SET_DEST (pat));
+
+	              if ((next = next_nonnote_insn (insn))
+	                  && GET_CODE (next) == INSN
+	                  && (note = find_regno_note (next,
+						      REG_DEAD,
+						      regno)))
+			{
+			  /* look for new_regno to replace with */
+		          int new_regno = find_last_reload (SET_SRC (pat));
+		          enum machine_mode mode = GET_MODE (SET_DEST (pat));
+
+                          /* tevid */
+                          if (new_regno != FIRST_PSEUDO_REGISTER)
+                            { /* The mode must be ok */
+                              if (!HARD_REGNO_MODE_OK (new_regno, mode))
+                                new_regno = FIRST_PSEUDO_REGISTER;
+                            }
+		          if (new_regno == FIRST_PSEUDO_REGISTER
+			      || ! TEST_HARD_REG_BIT (free_regs, new_regno))
+			    if (/*LAST_RELOAD (regno)*/
+			        reload_priority[regno])
+			      /* if we already used regno for reload in this
+			         loop it is better to reload the new memory
+			         to another register (if we find free one) */
+			      {
+			        new_regno = find_free_reg (mode);
+			        if (reload_priority [new_regno] &&
+			            reload_priority [regno] >=
+			            reload_priority [new_regno])
+			          {
+			            new_regno = FIRST_PSEUDO_REGISTER;
+			          }
+			      }
+			    else
+			      /* this is the first time we're using this
+			         register for reload in the current loop -
+			         so we need no replacement */
+			      new_regno = FIRST_PSEUDO_REGISTER;
+
+
+
+
+
+			  if (new_regno != FIRST_PSEUDO_REGISTER
+			      /* if regno == new_regno no replcement needed */
+			      && new_regno != regno)
+	                    {
+	                      register int nregs, i;
+	                      int stop_replacement = 0;
+
+		              rtx new_reg = gen_rtx (REG, mode, new_regno);
+	                      rtx old_reg = XEXP (note, 0);
+
+		              /* replace this register in the next insn */
+                              init_undo_buf ();
+		              subst_in_insn (next,
+		    		             PATTERN (next),
+		    		             old_reg,
+		    		             new_reg,
+		    		             0,
+		    		             0);
+
+#ifdef REGISTER_CONSTRAINTS
+                              save_code = INSN_CODE (next);
+
+	                      if ((INSN_CODE (next) = recog (PATTERN (next),
+							     next,
+							     0)) != -1)
+		                insn_extract (next);
+
+		              if (INSN_CODE (next) == -1
+		                  || !constrain_operands (INSN_CODE (next), 1))
+		                {
+			          /* restore the previous situation */
+			          INSN_CODE (next) = save_code;
+			          loop_undo_all ();
+		                  /*subst_in_insn (next,
+		    		                 PATTERN (next),
+		    		                 new_reg,
+		    		                 old_reg,
+		    		                 0,
+		    		                 0);*/
+		                  stop_replacement = 1;
+ 		                }
+#endif
+ 		              if (! stop_replacement)
+ 		                {
+ 		                  rtx next_dest = SET_DEST (PATTERN (next));
+
+	                          /* replace this insn's register with regno */
+	                          SET_DEST (pat) = new_reg;
+#if 0
+                                  init_undo_buf ();
+		    	          subst_in_insn (next,
+						 note,
+						 old_reg,
+						 new_reg,
+						 0,
+						 0);
+#endif
+
+				  /* The regno in the REG_DEAD note should be
+				     changed */
+
+				  XEXP (note, 0) = new_reg;
+		          
+				  /* Now, if we replaced a REG_DEAD note, and
+				     the new_reg is the destination of the next
+				     insn, we should remove this note */
+				  /* tevid replaced regno with new_regno,
+				     twice */
+
+				  if (GET_CODE (next_dest) == REG
+				      && REGNO (next_dest) == new_regno)
+				    remove_death (new_regno, next);
+			  
+				  /* replace the registers in the free_register
+				     list */
+				  nregs = HARD_REGNO_NREGS (new_regno, mode);
+				  for (i = 0; i < nregs; i++)
+				    CLEAR_HARD_REG_BIT (free_regs, new_regno + i);
+				  nregs = HARD_REGNO_NREGS (regno, mode);
+				  for (i = 0; i < nregs; i++)
+				    SET_HARD_REG_BIT (free_regs, regno + i);
+
+				  if (file)
+				    {
+				      fprintf (file, "insn %d: reload register",
+							       INSN_UID (insn));
+				      fprintf (file, " replaced (old %d new %d)\n",
+				      regno, new_regno);
+				    }
+#ifdef REGISTER_CONSTRAINTS
+				}  /* if (! stop_replacement) */
+#endif
+
+			    }  /* if (new_regno != FIRST_PSEUDO_REGISTER
+			    	      && new_regno != regno) */
+
+			    else if (file)
+			       {
+			         fprintf (file, "insn %d: no free register for",
+							       INSN_UID (insn));
+				 fprintf (file, " reload replacement\n");
+			       }
+			}  /* if (next = next_nonnote (insn))
+				  && (note = find_regno_note (next,
+				  			      REG_DEAD,
+				  			      regno))) */
+		      for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+		        if (reload_priority[i] > 0)
+		          reload_priority[i]++;
+		      reload_priority[REGNO (SET_DEST (PATTERN (insn)))] = 1;
+	            }  /* if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
+		              && RTX_IS_SPILL_P (insn)
+		              && (pat = PATTERN (insn))
+	                      && GET_CODE (pat) == SET
+	                      && GET_CODE (SET_DEST (pat)) == REG */
+
+		  /* update the last_reloads array */
+
+		  if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
+		      && (pat = PATTERN (insn))
+	              && GET_CODE (pat) == SET
+	              && GET_CODE (SET_DEST (pat)) == REG
+	              && GET_CODE (SET_SRC (pat)) == MEM)
+	            LAST_RELOAD (REGNO (SET_DEST (pat ))) = SET_SRC (pat);
+
+	        }  /* if (in_loop_f) */
+
+	      end_of_block_f = (insn == basic_block_end[block]);
+
+	      if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
+	        {
+	          register int j;
+	          rtx set;
+
+	          if (GET_CODE (insn) == CALL_INSN)
+		    /* all call clobbered registers are now free */
+		    for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
+		      if (call_used_regs[j])
+		        SET_HARD_REG_BIT (free_regs, j);
+
+		  update_free_regs (PATTERN (insn));
+
+		  /* Update LAST_RELOADs that are no longer valid */
+		  update_last_reloads ( PATTERN (insn));
+		     
+
+		  /* add each dead register to the free_regs set */
+		  for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
+		    if ((REG_NOTE_KIND (note) == REG_DEAD
+		         || REG_NOTE_KIND (note) == REG_UNUSED)
+		        && GET_CODE (XEXP (note, 0)) == REG)
+		      {
+			register int i;
+		        register int regno = REGNO (XEXP (note, 0));
+		        register int nregs = 
+			    HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
+
+		        for (i = 0; i < nregs; i++)
+			  SET_HARD_REG_BIT (free_regs, regno + i);
+		      }
+		  if ((note = find_reg_note (insn, REG_WAS_0, 0)))
+		    {
+		      set = single_set (insn);
+		      if (set == NULL 
+		          || GET_CODE (SET_DEST (set)) == REG)
+		        { /* Since reg may have been reused.  */
+		          remove_note (insn, note);
+		        }
+		    }
+		}
+
+	    }  /* for (insn = basic_block_head[block]; */
+	}  /* for (block = 0; block < n_basic_blocks; block++) */
+    }  /* if (n_basic_blocks > 0) */
+}  /* replace_reload_registers (file, f) */
+
+
+
+/* Returns a hard register regno, if the contents of entry regno in
+   last_reloads array equals to MEM, FIRST_PSEUDO_REGISTER otherwise. */
+
+static int
+find_last_reload (rtx mem)
+{
+  register int regno;
+  
+  if (GET_CODE (mem) != MEM)
+    abort ();
+
+  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
+    /* tevid added test of LAST_RELOAD (regno) != NULL and XEXPs */
+    if (LAST_RELOAD (regno) != NULL
+        && rtx_equal_p (XEXP (LAST_RELOAD (regno), 0), XEXP (mem, 0)))
+      return (regno);
+
+  return (FIRST_PSEUDO_REGISTER);
+}
+
+/* Keep track of effect of pat on last_reloads[]. Note that making
+   an error will not effect the correctness of the code.  */
+   
+static void
+update_last_reloads (rtx pat)
+{
+  register int i, j, regno, nregs;
+  rtx set_src, set_dest;
+  register char *fmt;
+  register RTX_CODE code = GET_CODE (pat);
+
+  switch (GET_CODE (pat))
+    {
+      case SET:
+      case CLOBBER:
+        set_dest = SET_DEST (pat);
+        if (GET_CODE (set_dest) == REG)
+          {
+            regno = REGNO (set_dest);
+            nregs = HARD_REGNO_NREGS (regno, GET_MODE (set_dest));
+
+            if (nregs != 1)
+              {
+	        bzero (last_reloads, sizeof last_reloads);
+              }
+            else
+              {
+                for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+                  {
+                    if (LAST_RELOAD (i))
+                      {
+                        if (reg_overlap_mentioned_p (set_dest, LAST_RELOAD (i)))
+                          {
+                            LAST_RELOAD (i) = NULL;
+                          }
+                      }
+                  }
+              }
+          }
+        else if (GET_CODE (set_dest) == SUBREG)
+          {
+            if (GET_CODE (SUBREG_REG (set_dest)) == REG)
+              {
+                regno = REGNO (SUBREG_REG (set_dest)) + SUBREG_WORD (set_dest);
+                nregs 
+                  = HARD_REGNO_NREGS (regno, GET_MODE (SUBREG_REG (set_dest)));
+
+                if (nregs != 1)
+                  {
+	            bzero (last_reloads, sizeof last_reloads);
+                  }
+                else
+                  {
+                    for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+                      {
+                        if (LAST_RELOAD (i))
+                          {
+                            if (reg_overlap_mentioned_p (SUBREG_REG (set_dest), 
+                            LAST_RELOAD (i)))
+                              {
+                                LAST_RELOAD (i) = NULL;
+                              }
+                          }
+                      }
+                  }
+              }
+            return;
+          }
+        else if (GET_CODE (set_dest) == MEM)
+          {
+	    for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+	      if (LAST_RELOAD (i)
+	          && true_dependence (set_dest, LAST_RELOAD (i)))
+	        LAST_RELOAD (i) = 0;
+	    update_last_reloads (XEXP (set_dest, 0));
+            return;
+          }
+      case CALL:
+	for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
+	  if (call_used_regs[j])
+	    LAST_RELOAD (j) = NULL;
+        return;
+      case PRE_DEC:
+      case PRE_INC:
+      case POST_DEC:
+      case POST_INC:
+        if (GET_CODE (XEXP (pat ,0)) == REG)
+          {
+            regno = REGNO (XEXP (pat ,0));
+            nregs = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (pat ,0)));
+
+            if (nregs != 1)
+              {
+	        bzero (last_reloads, sizeof last_reloads);
+              }
+            else
+              {
+                for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+                  {
+                    if (LAST_RELOAD (i))
+                      {
+                        if (reg_overlap_mentioned_p (XEXP (pat ,0), LAST_RELOAD (i)))
+                          {
+                            LAST_RELOAD (i) = NULL;
+                          }
+                      }
+                  }
+              }
+          }
+        return;
+    case HIGH:
+    case CONST_INT:
+    case CONST:
+    case CONST_DOUBLE:
+    case SYMBOL_REF:
+    case LABEL_REF:
+    case PC:
+    case CC0:
+    case REG:
+    /*case SUBREG:*/
+        /* do nothing */
+        return;
+  }  /* switch (GET_CODE (pat)) */
+
+  fmt = GET_RTX_FORMAT (code);
+  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+    if (fmt[i] == 'e')
+      {
+        if( XEXP (pat, i))
+          update_last_reloads (XEXP (pat, i));
+      }
+    else if (fmt[i] == 'E' || fmt[i] == 'V')
+      {
+	for (j = 0; j < XVECLEN (pat, i); j++)
+	  update_last_reloads (XVECEXP (pat, i, j));
+      }
+}  
+
+/* tsl - end */
+
+static unsigned int largest_himode_const;
+
+#define MAX_COMP_REGS 4
+
+struct sign_extension_info {
+  rtx insn_set;
+  int num_comp_regs;
+  struct comp_to_reg {
+    int regno;
+    rtx comp_insn;
+    rtx *where;
+    unsigned char for_equality;
+  } compare_to_reg [MAX_COMP_REGS];
+};
+static struct sign_extension_info * sign_extension_infos;
+
+static void
+sign_extension_reduction (loop_start, loop_end)
+  rtx loop_start, loop_end;
+{
+  int cur_max_regnum = max_reg_num ();
+  int found_sign_extension = 0, regno, i, j;
+  rtx insn, sign_ext_reg;
+
+  sign_extension_infos 
+    = (struct  sign_extension_info *) 
+      alloca ( sizeof (struct sign_extension_info) * cur_max_regnum);
+  bzero (sign_extension_infos, 
+         sizeof (struct sign_extension_info) * cur_max_regnum);
+  largest_himode_const = 256;
+  if (sizeof (unsigned int) <= GET_MODE_SIZE (HImode))
+    {
+      return ;
+    }
+  for (i = 0; i < GET_MODE_SIZE (HImode); i++)
+    {
+      largest_himode_const *= 256;
+    }
+  largest_himode_const -= 1;
+  /* Go over loop - mark registers set by sign extension */
+  for (insn = loop_start; insn && insn != loop_end; insn = NEXT_INSN (insn))
+    {
+      if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
+          && GET_CODE (SET_DEST (PATTERN (insn))) == REG 
+          && GET_CODE (SET_SRC (PATTERN (insn))) == SIGN_EXTEND
+          && GET_MODE (SET_DEST (PATTERN (insn))) == SImode
+          && GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == HImode)
+         { /* Found one.  */
+           regno = REGNO (SET_DEST (PATTERN (insn)));
+           if ( regno >= cur_max_regnum)
+             {
+               return;
+             }
+           found_sign_extension++;
+           if (sign_extension_infos[regno].insn_set)
+             {
+               return;
+             }
+           sign_extension_infos[regno].insn_set = insn;
+         }
+    }
+  if (!found_sign_extension || insn != loop_end)
+    {
+      return;
+    }
+  /* Find all uses of each register marked above */
+  for (i = FIRST_PSEUDO_REGISTER; i < cur_max_regnum; i++)
+    {
+      if (sign_extension_infos[i].insn_set)
+        {
+          for (insn = loop_start; insn != loop_end; insn = NEXT_INSN (insn))
+            {
+              if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN
+                  || GET_CODE (insn) == JUMP_INSN)
+                {
+                  
+                  validate_all_references (i, insn, PATTERN (insn));
+                }
+            }
+        }
+    }
+  for (i = FIRST_PSEUDO_REGISTER; i < cur_max_regnum; i++)
+    {
+      if (sign_extension_infos[i].insn_set)
+        {
+          sign_ext_reg = SET_DEST (PATTERN (sign_extension_infos[i].insn_set));
+          if (reg_used_between_p (sign_ext_reg,
+                                  get_insns (), loop_start) ||
+              reg_used_between_p (sign_ext_reg,
+                                  loop_end, NULL)
+             )
+            {
+              sign_extension_infos[i].insn_set = NULL;
+            }
+        }
+    }
+  /* Check which registers can be sign extension reduced */
+  for (i = FIRST_PSEUDO_REGISTER; i < cur_max_regnum; i++)
+    {
+      if (sign_extension_infos[i].insn_set)
+        {
+          j = 0;
+          while (j < sign_extension_infos[i].num_comp_regs
+                 && sign_extension_infos[i].insn_set)
+            {
+              regno = sign_extension_infos[i].compare_to_reg[j].regno;
+              if (regno < FIRST_PSEUDO_REGISTER)
+                {
+                  sign_extension_infos[i].insn_set = NULL;
+                }
+              if (sign_extension_infos[regno].insn_set == NULL)
+                {
+                  sign_extension_infos[i].insn_set = NULL;
+                }
+              j++;
+            }
+        }
+    }
+  /* Do the optimization.  */
+  for (i = FIRST_PSEUDO_REGISTER; i < cur_max_regnum; i++)
+    {
+      if (sign_extension_infos[i].insn_set)
+        {
+          rtx subreg, strict_subreg;
+
+          subreg 
+            = gen_rtx (SUBREG, HImode, 
+              SET_DEST (PATTERN (sign_extension_infos[i].insn_set)),
+              0);
+          strict_subreg = gen_rtx (STRICT_LOW_PART, 0, subreg);
+          emit_insn_before (gen_rtx (SET, 0, 
+             SET_DEST (PATTERN (sign_extension_infos[i].insn_set)),
+             const0_rtx), loop_start);
+          emit_insn_before (gen_rtx (USE, 0, 
+             SET_DEST (PATTERN (sign_extension_infos[i].insn_set))),
+             loop_start);
+          SET_DEST (PATTERN (sign_extension_infos[i].insn_set)) 
+            = strict_subreg;
+          SET_SRC (PATTERN (sign_extension_infos[i].insn_set)) 
+            = XEXP (SET_SRC (PATTERN (sign_extension_infos[i].insn_set)), 0);
+          INSN_CODE (sign_extension_infos[i].insn_set) = -1;
+          j = 0;
+          while (j < sign_extension_infos[i].num_comp_regs)
+            {
+              if (sign_extension_infos[i].compare_to_reg[j].for_equality == 0)
+                {
+                  *sign_extension_infos[i].compare_to_reg[j].where
+                    = subreg;
+                  INSN_CODE (sign_extension_infos[i].compare_to_reg[j].comp_insn)
+                    = -1;
+                }
+              j++;
+            }
+        }
+    }
+}
+
+
+static void
+validate_all_references (regno, insn, pat)
+  int regno;
+  rtx insn, pat;
+{
+  register RTX_CODE code = GET_CODE (pat);
+  register int i, j, val;
+  register char *fmt;
+  int num_comp_regs, comp_regno, for_equality = 0;
+  rtx next;
+
+  switch (code)
+    {
+    case HIGH:
+    case CONST_INT:
+    case CONST:
+    case CONST_DOUBLE:
+    case SYMBOL_REF:
+    case LABEL_REF:
+    case PC:
+    case CC0:
+      return ;
+
+    case REG:
+      if (REGNO (pat) == regno)
+        {
+          sign_extension_infos[regno].insn_set = NULL;
+        }
+      break;
+      
+    case SET:
+      if (GET_CODE (SET_DEST (pat)) == REG 
+          && REGNO (SET_DEST (pat)) == regno
+          && sign_extension_infos[REGNO (SET_DEST (pat))].insn_set != insn)
+        {
+          if (GET_CODE (SET_SRC (pat)) != CONST_INT)
+            {
+              sign_extension_infos[regno].insn_set = NULL;
+            }
+          if (GET_MODE (SET_DEST (pat)) != SImode)
+            {
+              sign_extension_infos[regno].insn_set = NULL;
+            }
+          val = XINT (SET_SRC (pat), 0);
+          if (val < 0 || val > largest_himode_const)
+            {
+              sign_extension_infos[regno].insn_set = NULL;
+            }
+          validate_all_references (regno, insn, SET_SRC (pat));
+          return;
+        }
+      else if (GET_CODE (SET_DEST (pat)) == REG 
+          && REGNO (SET_DEST (pat)) == regno
+          && sign_extension_infos[REGNO (SET_DEST (pat))].insn_set == insn)
+        {
+          return;
+        }
+      break;
+
+    case AND:
+      if (GET_CODE (XEXP (pat, 0)) == REG 
+          && REGNO (XEXP (pat, 0)) == regno)
+        {
+          if (GET_CODE (XEXP (pat, 1)) != CONST_INT)
+            {
+              sign_extension_infos[regno].insn_set = NULL;
+            }
+          if (GET_MODE (XEXP (pat, 0)) != SImode)
+            {
+              sign_extension_infos[regno].insn_set = NULL;
+            }
+          val = XINT (XEXP (pat, 1), 0);
+          if (val < 0 || val > largest_himode_const)
+            {
+              sign_extension_infos[regno].insn_set = NULL;
+            }
+          validate_all_references (regno, insn, XEXP (pat, 1));
+          return;
+        }
+      else if (GET_CODE (XEXP (pat, 1)) == REG 
+          && REGNO (XEXP (pat, 1)) == regno)
+        {
+          if (GET_CODE (XEXP (pat, 0)) != CONST_INT)
+            {
+              sign_extension_infos[regno].insn_set = NULL;
+            }
+          if (GET_MODE (XEXP (pat, 1)) != SImode)
+            {
+              sign_extension_infos[regno].insn_set = NULL;
+            }
+          val = XINT (XEXP (pat, 0), 0);
+          if (val < 0 || val > largest_himode_const)
+            {
+              sign_extension_infos[regno].insn_set = NULL;
+            }
+          validate_all_references (regno, insn, XEXP (pat, 0));
+          return;
+        }
+      break;
+
+    case COMPARE:
+      next = NEXT_INSN (insn);
+      if (GET_CODE (next) == JUMP_INSN 
+	  && GET_CODE (PATTERN (next)) == SET 
+	  && SET_DEST (PATTERN (next)) == pc_rtx 
+	  && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE
+	  && (GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)) == NE
+	      ||
+	      GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)) == EQ))
+	{
+	  for_equality = 1;
+	}
+      if (GET_CODE (XEXP (pat, 0)) == REG 
+          && REGNO (XEXP (pat, 0)) == regno)
+        {
+          if (GET_MODE (XEXP (pat, 0)) != SImode)
+            {
+              sign_extension_infos[regno].insn_set = NULL;
+            }
+          if (GET_CODE (XEXP (pat, 1)) == CONST_INT)
+            {
+              val = XINT (XEXP (pat, 1), 0);
+              if (for_equality == 0 || val < 0 || val > largest_himode_const)
+                {
+                  sign_extension_infos[regno].insn_set = NULL;
+                }
+            }
+          else if (GET_CODE (XEXP (pat, 1)) == REG)
+            {
+              if (GET_MODE (XEXP (pat, 1)) != SImode)
+                {
+                  sign_extension_infos[regno].insn_set = NULL;
+                }
+#ifndef HAVE_cmphi
+              sign_extension_infos[regno].insn_set = NULL;
+#else
+              if (!HAVE_cmphi)
+                {
+                  sign_extension_infos[regno].insn_set = NULL;
+                }
+#endif
+              comp_regno = REGNO (XEXP (pat, 1));
+              if (!sign_extension_infos[comp_regno].insn_set)
+                {
+                  sign_extension_infos[regno].insn_set = NULL;
+                }
+              else
+                {
+                  num_comp_regs 
+                    = sign_extension_infos[regno].num_comp_regs;
+                  if (num_comp_regs >= MAX_COMP_REGS)
+                    {
+                      sign_extension_infos[regno].insn_set = NULL;
+                    }
+                  sign_extension_infos[regno].
+                      compare_to_reg[num_comp_regs].where = 
+                    &XEXP (pat, 0);
+                  sign_extension_infos[regno].
+                      compare_to_reg[num_comp_regs].comp_insn = insn;
+                  sign_extension_infos[regno].
+                      compare_to_reg[num_comp_regs].regno = 
+                    comp_regno;
+	          sign_extension_infos[regno].
+	             compare_to_reg[num_comp_regs].for_equality = for_equality;
+                  sign_extension_infos[regno].num_comp_regs++;
+                }
+            }
+          else
+            {
+              sign_extension_infos[regno].insn_set = NULL;
+              validate_all_references (regno, insn, XEXP (pat, 1));
+            }
+          return;
+        }
+      else if (GET_CODE (XEXP (pat, 1)) == REG 
+          && REGNO (XEXP (pat, 1)) == regno)
+        {
+          if (GET_MODE (XEXP (pat, 1)) != SImode)
+            {
+              sign_extension_infos[regno].insn_set = NULL;
+            }
+          if (GET_CODE (XEXP (pat, 0)) == CONST_INT)
+            {
+              val = XINT (XEXP (pat, 0), 0);
+              if (for_equality == 0 || val < 0 || val > largest_himode_const)
+                {
+                  sign_extension_infos[regno].insn_set = NULL;
+                }
+            }
+          else if (GET_CODE (XEXP (pat, 0)) == REG)
+            {
+              if (GET_MODE (XEXP (pat, 0)) != SImode)
+                {
+                  sign_extension_infos[regno].insn_set = NULL;
+                }
+#ifndef HAVE_cmphi
+              sign_extension_infos[regno].insn_set = NULL;
+#else
+              if (!HAVE_cmphi)
+                {
+                  sign_extension_infos[regno].insn_set = NULL;
+                }
+#endif
+              comp_regno = REGNO (XEXP (pat, 0));
+              if (!sign_extension_infos[comp_regno].insn_set)
+                {
+                  sign_extension_infos[regno].insn_set = NULL;
+                }
+              else
+                {
+                  num_comp_regs 
+                    = sign_extension_infos[regno].num_comp_regs;
+                  if (num_comp_regs >= MAX_COMP_REGS)
+                    {
+                      sign_extension_infos[regno].insn_set = NULL;
+                    }
+                  sign_extension_infos[regno].
+                      compare_to_reg[num_comp_regs].where = 
+                    &XEXP (pat, 1);
+                  sign_extension_infos[regno].
+                      compare_to_reg[num_comp_regs].comp_insn = insn;
+                  sign_extension_infos[regno].
+                      compare_to_reg[num_comp_regs].regno = 
+                    comp_regno;
+	          sign_extension_infos[regno].
+	             compare_to_reg[num_comp_regs].for_equality = for_equality;
+                  sign_extension_infos[regno].num_comp_regs++;
+                }
+            }
+          else
+            {
+              sign_extension_infos[regno].insn_set = NULL;
+              validate_all_references (regno, insn, XEXP (pat, 0));
+            }
+          return;
+        }
+      break;
+
+
+    }
+
+  fmt = GET_RTX_FORMAT (code);
+  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+    if (fmt[i] == 'e')
+      {
+        if( XEXP (pat, i))
+          validate_all_references (regno, insn, XEXP (pat, i));
+      }
+    else if (fmt[i] == 'E' || fmt[i] == 'V')
+      {
+	for (j = 0; j < XVECLEN (pat, i); j++)
+          validate_all_references (regno, insn, XVECEXP (pat, i, j));
+      }
+}
+
+#define MAX_WHERE 5
+#define MAX_DISAMBIGS 3
+#define MAX_MEM_REFS 10
+#define NO_REG -1
+#define UNKNOWN -2
+
+static struct mem_ref {
+  /*  Pointers to where this mem_ref is used.  */
+  rtx * where[MAX_WHERE];
+  /* Number of references to this mem_ref in the loop.  */
+  int num_ref;
+  /* The base register number if any, else -1.  */
+  int base_regno;
+  /* The base register number if.  */
+  rtx base_reg;
+  /* The index register number if any, else -1.  */
+  int index_regno;
+  /* The index register number if.  */
+  rtx index_reg;
+  /* Bit-map if bit# i is set then this element is true_dependence on
+     element# i. Assumes MAX_MEM_REFS < (sizeof (int) * 8) */
+  int conflict;
+  /* If 1 then this element is a varying address over the loop - or
+     should not be lifted into register for some other reason.  */
+  unsigned int varying:1;
+  /* If 1 then this mem_ref is stored into in the loop.  */
+  unsigned int stored:1;
+  /* If 1 then the first reference to the mem_ref in the loop is a store.  */
+  unsigned int first_stored:1;
+  } *mem_refs;
+
+static struct disambig{
+  rtx reg;
+  int inc_val;
+}	runtime_disambigs [MAX_DISAMBIGS];
+
+static int num_mem_refs = 0;
+static int max_regs_before_lift;
+
+extern rtx gen_jump ();
+/*
+  Shadow memory locations that are stored into in the loop and can
+  be memory disambiguated over the loop. These are loaded into a register
+  before the loop, accessed from and into the register during the loop
+  and stored from the register at the loop end.  
+*/
+static void
+lift_stores (loop_start, loop_end)
+  rtx loop_start, loop_end;
+{
+  rtx insn, lift_reg, set, new_label, new_label_insn, new_jump_insn, new_jump,
+      new_loop_label, new_loop_jump, new_compare, new_compare_insn, copy_insn;
+  int i, j, num_candidates, jmask, imask, num_lifted, num_possible,
+      indx_possible, num_runtime_disambigs, disambig_mask, found, dummy;
+  char * may_not_optimize;
+  
+  if (loop_dump_stream)
+    {
+      fprintf (loop_dump_stream, "lift stores from %d to %d\n",
+      INSN_UID (loop_start), INSN_UID (loop_end));
+    }
+  /* Handle only loops with no inner jumps labels or calls */
+  if (GET_CODE (PREV_INSN (loop_end)) != JUMP_INSN)
+    {
+      return;
+    }
+  if (GET_CODE (SET_SRC (PATTERN (PREV_INSN (loop_end)))) != IF_THEN_ELSE)
+    {
+      return;
+    }
+  if (GET_CODE (NEXT_INSN (loop_start)) != CODE_LABEL)
+    {
+      return;
+    }
+  for (insn = NEXT_INSN (NEXT_INSN (loop_start)); 
+       insn != PREV_INSN (loop_end); insn = NEXT_INSN (insn))
+    {
+      if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN
+          || GET_CODE (insn) == CODE_LABEL)
+        {
+          return;
+        }
+    }
+  /* Compute n_times_set */
+  max_regs_before_lift = max_reg_num () + 1;
+  n_times_set = (short *) alloca (max_regs_before_lift * sizeof (short));
+  bzero (n_times_set, max_regs_before_lift * sizeof (short));
+  may_not_optimize = (char *) alloca (max_regs_before_lift);	/* not used */
+  count_loop_regs_set (loop_start, loop_end, may_not_optimize, NULL,
+		       &dummy, max_regs_before_lift);
+
+  mem_refs = (struct mem_ref *) alloca (sizeof (struct mem_ref) * MAX_MEM_REFS);
+  bzero (mem_refs, sizeof (struct mem_ref) * MAX_MEM_REFS);
+  /* Locate all memory refs into the mem_refs array.  */
+  num_mem_refs = 0;
+  for (insn = loop_start; insn != loop_end; insn = NEXT_INSN (insn))
+    {
+      if (GET_CODE (insn) == INSN)
+        {
+          mark_mem_refs (PATTERN (insn), &PATTERN (insn));
+          if (num_mem_refs >= MAX_MEM_REFS)
+            {
+              return;
+            }
+        }
+    }
+  if (num_mem_refs == 0)
+    {
+      return;
+    }
+  /* Check each non varying mem_ref against all others to see if it can
+     be memory disambiguated */
+  num_candidates = 0;
+  for (i = 0; i < num_mem_refs; i++)
+    {
+      if (mem_refs[i].varying == 0 && mem_refs[i].stored == 1)
+        {
+          num_candidates++;
+          imask = 1 << i;
+          for (j = 0; j < num_mem_refs; j++)
+            {
+              jmask = (1 << j);
+              if (j != i && !(mem_refs[i].conflict & jmask))
+                {
+                  if (true_dependence (*(mem_refs[i].where[0]),
+                                       *(mem_refs[j].where[0])))
+                    {
+                      mem_refs[i].conflict |= jmask;
+                      mem_refs[j].conflict |= imask;
+                    }
+                }
+            }
+        }
+    }
+  /* Lift all the mem_refs that can be lifted.  */
+  num_lifted = 0;
+  num_possible = 0;
+  for (i = 0; i < num_mem_refs; i++)
+    {
+      if (mem_refs[i].varying == 0 && mem_refs[i].stored == 1)
+        {
+          num_possible++;
+          indx_possible = i;
+        }
+      if (mem_refs[i].varying == 0 && mem_refs[i].stored == 1
+          && mem_refs[i].conflict == 0)
+        {
+          num_lifted++;
+          lift_reg = gen_reg_rtx (GET_MODE (*(mem_refs[i].where[0])));
+          if (mem_refs[i].first_stored)
+            {
+              emit_insn_before ( gen_rtx (SET, 0, lift_reg, 
+                                          CONST0_RTX ( GET_MODE (lift_reg))),
+                                 loop_start);
+            }
+          else
+            {
+              emit_insn_before ( gen_rtx (SET, 0, lift_reg, 
+                                          copy_rtx (*(mem_refs[i].where[0]))),
+                                 loop_start);
+            }
+          emit_insn_after ( gen_rtx (SET, 0, copy_rtx (*(mem_refs[i].where[0])),
+                                              lift_reg),
+                                 loop_end);
+          /*emit_insn_after (gen_rtx (USE, 0, lift_reg),
+                          NEXT_INSN (loop_end));*/
+          for (j = 0; j < mem_refs[i].num_ref; j++)
+            {
+              *(mem_refs[i].where[j]) = lift_reg;
+            }
+          if (loop_dump_stream)
+            {
+              fprintf (loop_dump_stream, 
+              "The following memory operand lifted into reg %d during loop:\n",
+              REGNO (lift_reg));
+              tdebug_rtx (SET_DEST (PATTERN (NEXT_INSN (loop_end))),
+                          loop_dump_stream);
+              fprintf (loop_dump_stream, "\n");
+            }
+        }
+    }
+  if (num_lifted == 0 && num_possible == 1 && flag_runtime_lift_stores)
+    {  /* Do runtime disambiguation if possible */
+      if (mem_refs[indx_possible].index_regno != NO_REG
+          || mem_refs[indx_possible].base_regno == NO_REG
+          || mem_refs[indx_possible].base_regno == UNKNOWN)
+        {
+          return;
+        }
+      if (GET_MODE (mem_refs[indx_possible].base_reg) != SImode)
+        {
+          return;
+        }
+      num_runtime_disambigs = 0;
+      for (i = 0; i < num_mem_refs; i++)
+        {
+          disambig_mask = 1 << i;
+          if (mem_refs[indx_possible].conflict & disambig_mask)
+            {
+              if (num_runtime_disambigs >= MAX_DISAMBIGS)
+                {
+                  return;
+                }
+              if (mem_refs[i].base_regno == NO_REG 
+                  || mem_refs[i].base_regno == UNKNOWN
+                  || (mem_refs[i].index_regno != UNKNOWN
+                      && mem_refs[i].index_regno != NO_REG))
+                {
+                  return;
+                }
+              if (n_times_set[mem_refs[i].base_regno] > 1)
+                {
+                  return;
+                }
+              if (GET_MODE (mem_refs[i].base_reg) 
+                   != GET_MODE (mem_refs[indx_possible].base_reg))
+                {
+                  return;
+                }
+              runtime_disambigs[num_runtime_disambigs].reg
+                = mem_refs[i].base_reg;
+              runtime_disambigs[num_runtime_disambigs].inc_val = 0;
+              num_runtime_disambigs++;
+            }
+        }
+      /* Now find the setting of each of the registers of the disambigs */
+      for (i = 0; i < num_runtime_disambigs; i++)
+        {
+          if (n_times_set[REGNO (runtime_disambigs[i].reg)])
+            {
+              insn = loop_start;
+              found = 0;
+              while (insn != loop_end && !found)
+                {
+                  if (GET_CODE (insn) == INSN)
+                    {
+                      set = single_set (insn);
+                      if (set && GET_CODE (SET_DEST (set)) == REG
+                          && REGNO (SET_DEST (set)) 
+                              == REGNO (runtime_disambigs[i].reg) )
+                        {
+                          found = 1;
+                          if (!rtx_equal_p (SET_DEST (set),
+                                            runtime_disambigs[i].reg))
+                            {
+                              return;
+                            }
+                          if ((GET_CODE (SET_SRC (set)) == PLUS
+                                || GET_CODE (SET_SRC (set)) == MINUS)
+                              && rtx_equal_p (SET_DEST (set), 
+                                              XEXP (SET_SRC (set), 0))
+                              && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
+                            {
+                              runtime_disambigs[i].inc_val 
+                                = XINT (XEXP (SET_SRC (set), 1), 0) 
+                                   * (GET_CODE (SET_SRC (set)) == PLUS
+                                      ? 1 : -1);
+                            }
+                          else
+                            {
+                              return;
+                            }
+                        }
+                    }
+                  if (!found)
+                    {
+                      insn = NEXT_INSN (insn);
+                    }
+                }
+              if (!found)
+                {
+                  return;
+                }
+            }
+        }
+      /* The runtime disambiguation is possible - now do it.  */
+      /* Make a copy of the loop.  */
+      new_label = gen_label_rtx ();
+      new_label_insn 
+        = emit_label_after (new_label, PREV_INSN (loop_start));
+      new_loop_label = new_label_insn;
+      ++LABEL_NUSES (new_label_insn);
+      new_jump = copy_rtx (PATTERN (PREV_INSN (loop_end)));
+      if (XEXP (SET_SRC (new_jump), 1) == pc_rtx)
+        {
+          XEXP (SET_SRC (new_jump), 2)
+            = gen_rtx (LABEL_REF, VOIDmode, new_label);
+        }
+      else
+        {
+          XEXP (SET_SRC (new_jump), 1)
+            = gen_rtx (LABEL_REF, VOIDmode, new_label);
+        }
+      new_jump_insn = emit_jump_insn_after (new_jump, new_label_insn);
+      INSN_CODE (new_jump_insn) = recog (new_jump, new_jump_insn);
+      new_loop_jump = new_jump_insn;
+      JUMP_LABEL (new_jump_insn) = new_label_insn;
+      /* The body of the original loop is moved to the new loop */
+      NEXT_INSN (new_label_insn) = NEXT_INSN (NEXT_INSN (loop_start));
+      PREV_INSN (NEXT_INSN (new_label_insn)) = new_label_insn;
+      PREV_INSN (new_jump_insn) = PREV_INSN (PREV_INSN (loop_end));
+      NEXT_INSN ( PREV_INSN (new_jump_insn)) = new_jump_insn;
+      NEXT_INSN (NEXT_INSN (loop_start)) = PREV_INSN (loop_end);
+      PREV_INSN (PREV_INSN (loop_end)) = NEXT_INSN (loop_start);
+      /* Now make a copy of the loop in between the original label and jump.  */
+      insn = NEXT_INSN (new_label_insn);
+      copy_insn = NEXT_INSN (loop_start);
+      while (insn != new_jump_insn)
+        {
+          if (GET_CODE (insn) == INSN)
+            {
+              copy_insn = emit_insn_after (copy_rtx (PATTERN (insn)), copy_insn);
+            }
+          insn = NEXT_INSN (insn);
+        }
+      /* Now make a jump around the second copy of the loop.  */
+      new_label = gen_label_rtx ();
+      new_label_insn 
+        = emit_label_after (new_label, loop_end);
+      new_jump_insn = emit_jump_insn_after (gen_jump (new_label_insn),
+          PREV_INSN (loop_start));
+      JUMP_LABEL (new_jump_insn) = new_label_insn;
+      ++LABEL_NUSES (new_label_insn);
+      emit_barrier_after (new_jump_insn);
+      /* Now make a label just before loop start */
+      new_label = gen_label_rtx ();
+      new_label_insn 
+        = emit_label_after (new_label, PREV_INSN (loop_start));
+      ++LABEL_NUSES (new_label_insn);
+      /* Now compare the base_reg of the mem_ref to be lifted with
+         each of the base_regs that it conflicts with.  Jump around the
+         disambiguated loop if they conflict at runtime.  */
+      for (i = 0; i < num_runtime_disambigs; i++)
+        {
+          if (runtime_disambigs[i].inc_val != 0)
+            {
+              new_compare 
+                = gen_cmpsi_1 (runtime_disambigs[i].reg,
+                                mem_refs[indx_possible].base_reg);
+              new_compare_insn 
+                = emit_insn_before (new_compare, new_loop_label);
+              new_jump = copy_rtx (new_jump);
+              if (runtime_disambigs[i].inc_val > 0)
+                {
+                  GET_CODE (XEXP (SET_SRC (new_jump), 0)) = LE;
+                }
+              else
+                {
+                  GET_CODE (XEXP (SET_SRC (new_jump), 0)) = GE;
+                }
+	      XEXP (SET_SRC (new_jump), 1) 
+	        = gen_rtx (LABEL_REF, VOIDmode, new_label);
+	      XEXP (SET_SRC (new_jump), 2) = pc_rtx;
+              ++LABEL_NUSES (new_label_insn);
+              new_jump_insn 
+                = emit_jump_insn_after (new_jump, new_compare_insn);
+              JUMP_LABEL (new_jump_insn) = new_label_insn;
+              INSN_CODE (new_jump_insn)
+                = recog (new_jump, new_jump_insn);
+            }
+        }
+      /* Now do the lifting */
+      lift_reg = gen_reg_rtx (GET_MODE (*(mem_refs[indx_possible].where[0])));
+      if (mem_refs[indx_possible].first_stored)
+        {
+          emit_insn_before ( gen_rtx (SET, 0, lift_reg, 
+                                      CONST0_RTX ( GET_MODE (lift_reg))),
+                             new_loop_label);
+        }
+      else
+        {
+          emit_insn_before ( gen_rtx (SET, 0, lift_reg, 
+                            copy_rtx (*(mem_refs[indx_possible].where[0]))),
+                             new_loop_label);
+        }
+      emit_insn_after ( gen_rtx (SET, 0, 
+                                 copy_rtx (*(mem_refs[indx_possible].where[0])),
+                                          lift_reg),
+                             new_loop_jump);
+      /*emit_insn_after (gen_rtx (USE, 0, lift_reg),
+                      NEXT_INSN (new_loop_jump));*/
+      emit_insn_after (gen_rtx (CLOBBER, 0, lift_reg), loop_end);
+      for (j = 0; j < mem_refs[indx_possible].num_ref; j++)
+        {
+          *(mem_refs[indx_possible].where[j]) = lift_reg;
+        }
+      emit_note_before (NOTE_INSN_LOOP_BEG, new_loop_label);
+      emit_note_before (NOTE_INSN_LOOP_END, NEXT_INSN (new_loop_jump));
+      if (loop_dump_stream)
+        {
+          fprintf (loop_dump_stream, 
+          "The following memory operand RUNTIME lifted into reg %d during loop:\n",
+          REGNO (lift_reg));
+          tdebug_rtx (SET_DEST (PATTERN (NEXT_INSN (NEXT_INSN (new_loop_jump)))),
+                      loop_dump_stream);
+          fprintf (loop_dump_stream, "\n");
+        }
+    }
+}
+
+
+/* 
+   Go over PAT locate all mem_refs and insert them into the mem_refs
+   structure.  WHERE is the location of PAT.  */
+static void 
+mark_mem_refs (pat, where)
+     rtx pat;
+     rtx *where;
+{
+  register RTX_CODE code = GET_CODE (pat);
+  register int i, j;
+  register char *fmt;
+
+  switch (code)
+    {
+    case HIGH:
+    case CONST_INT:
+    case CONST:
+    case CONST_DOUBLE:
+    case SYMBOL_REF:
+    case LABEL_REF:
+    case PC:
+    case CC0:
+      return ;
+
+    case SET:
+      mark_mem_refs (SET_SRC (pat), &SET_SRC (pat));
+      if (GET_CODE (SET_DEST (pat)) == MEM)
+        {
+          insert_mem_ref (SET_DEST (pat), &SET_DEST (pat), 1);
+        }
+      return;
+
+     case MEM:
+       insert_mem_ref (pat, where, 0);
+       return;
+
+    }
+
+  fmt = GET_RTX_FORMAT (code);
+  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+    if (fmt[i] == 'e')
+      {
+        if( XEXP (pat, i))
+          mark_mem_refs (XEXP (pat, i), &XEXP (pat, i));
+      }
+    else if (fmt[i] == 'E' || fmt[i] == 'V')
+      {
+	for (j = 0; j < XVECLEN (pat, i); j++)
+	  mark_mem_refs (XVECEXP (pat, i, j), &XVECEXP (pat, i, j));
+      }
+}
+
+
+/*
+   Insert the memory reference MEM into the mem_refs structure.  
+   WHERE is location of MEM.  
+   if IS_STORE is 1 then MEM is being stored into.  */
+   
+static void
+insert_mem_ref (mem, where, is_store)
+  rtx mem, *where;
+  int is_store;
+{
+  int i, j, indx, found, base_regno, index_regno;
+  rtx mem_addr, base_reg, index_reg;
+
+  if (num_mem_refs >= MAX_MEM_REFS)
+    {
+      return;
+    }
+  /* Find where in table to put mem.  */
+  i = 0;
+  found = 0;
+  while (i < num_mem_refs && !found)
+    {
+      if (rtx_equal_p (mem, *(mem_refs[i].where[0])))
+        {
+          found = 1;
+        }
+      else
+        {
+          i++;
+        }
+    }
+  if (!found)
+    {
+      num_mem_refs++;
+    }
+  if (i >= MAX_MEM_REFS)
+    {
+      return;
+    }
+
+  indx = i;
+  j = mem_refs[indx].num_ref;
+  if (j >= MAX_WHERE)
+    {
+      mem_refs[indx].varying = 1;
+      return;
+    }
+  mem_refs[indx].where[j] = where;
+  mem_refs[indx].num_ref++;
+  if (is_store)
+    {
+      mem_refs[indx].stored = 1;
+      if (j == 0)
+        {
+          mem_refs[indx].first_stored = 1;
+        }
+    }
+  if (found == 1)
+    {
+      return;
+    }
+  mem_refs[indx].varying = rtx_addr_varies_p (mem);
+  /* Now analyze the mem to find it's base and index registers if any */
+  mem_refs[indx].base_regno = NO_REG;
+  mem_refs[indx].index_regno = NO_REG;
+  index_reg = NULL;
+  base_regno = NO_REG;
+  index_regno = NO_REG;
+  base_reg = NULL;
+  mem_addr = XEXP (mem, 0);
+  if (GET_CODE (mem_addr) == SYMBOL_REF)
+    {
+      return;
+    }
+  if (GET_CODE (mem_addr) == REG)
+    {
+      base_regno = REGNO (mem_addr);
+      base_reg = (mem_addr);
+    }
+  if (GET_CODE (mem_addr) == PLUS)
+    {
+      if (GET_CODE (XEXP (mem_addr, 0)) == REG)
+	{
+	  base_regno = REGNO (XEXP (mem_addr, 0));
+	  base_reg = (XEXP (mem_addr, 0));
+	  if (GET_CODE (XEXP (mem_addr, 1)) == REG)
+	    {
+	      index_regno = REGNO (XEXP (mem_addr, 1));
+	      index_reg = (XEXP (mem_addr, 1));
+	    }
+	  else if (GET_CODE (XEXP (mem_addr, 1)) != CONST_INT 
+	           && GET_CODE (XEXP (mem_addr, 1)) != CONST
+	           && GET_CODE (XEXP (mem_addr, 1)) != SYMBOL_REF)
+	    {
+	      index_regno = UNKNOWN;
+	    }
+	}
+      else if (GET_CODE (XEXP (mem_addr, 0)) == MULT)
+	{
+	  if (GET_CODE (XEXP (mem_addr, 1)) == REG)
+	    {
+	      base_regno = REGNO (XEXP (mem_addr, 1));
+	      base_reg =  (XEXP (mem_addr, 1));
+	    }
+	  else if (GET_CODE (XEXP (mem_addr, 1)) != CONST_INT 
+	           && GET_CODE (XEXP (mem_addr, 1)) != CONST
+	           && GET_CODE (XEXP (mem_addr, 1)) != SYMBOL_REF)
+	    {
+	      base_regno = UNKNOWN;
+	    }
+	  if (GET_CODE (XEXP (XEXP (mem_addr, 0), 0)) == REG
+	      && GET_CODE (XEXP (XEXP (mem_addr, 0), 1)) == CONST_INT)
+	   {
+	     index_regno = REGNO (XEXP (XEXP (mem_addr, 0), 0));
+	     index_reg = (XEXP (XEXP (mem_addr, 0), 0));
+	   }
+	 else
+	   {
+	     index_regno = UNKNOWN;
+	   }
+	}
+      else if (GET_CODE (XEXP (mem_addr, 0)) == PLUS)
+	{
+          if (GET_CODE (XEXP (XEXP (mem_addr, 0), 0)) == REG)
+	    {
+	      base_regno = REGNO (XEXP (XEXP (mem_addr, 0), 0));
+	      base_reg = (XEXP (XEXP (mem_addr, 0), 0));
+	      if (GET_CODE (XEXP (XEXP (mem_addr, 0), 1)) == REG)
+	        {
+	          index_regno = REGNO (XEXP (XEXP (mem_addr, 0), 1));
+	          index_reg = (XEXP (XEXP (mem_addr, 0), 1));
+	        }
+      	      else if (GET_CODE (XEXP (XEXP (mem_addr, 0), 1)) != CONST_INT 
+	               && GET_CODE (XEXP (XEXP (mem_addr, 0), 1)) != CONST
+	               && GET_CODE (XEXP (XEXP (mem_addr, 0), 1)) != SYMBOL_REF)
+	        {
+	          index_regno = UNKNOWN;
+	        }
+	    }
+          else if (GET_CODE (XEXP (XEXP (mem_addr, 0), 0)) == MULT)
+	    {
+	      if (GET_CODE (XEXP (XEXP (mem_addr, 0), 1)) == REG)
+	        {
+	          base_regno = REGNO (XEXP (XEXP (mem_addr, 0), 1));
+	          base_reg = (XEXP (XEXP (mem_addr, 0), 1));
+	        }
+	      if (GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0)) == REG
+	          && GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1)) == CONST_INT)
+	       {
+	         index_regno = REGNO (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0));
+	         index_reg = (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0));
+	       }
+	     else
+	       {
+	         index_regno = UNKNOWN;
+	       }
+	    }
+	  if (GET_CODE (XEXP (mem_addr, 1)) != SYMBOL_REF
+	      && GET_CODE (XEXP (mem_addr, 1)) != CONST
+	      && GET_CODE (XEXP (mem_addr, 1)) != CONST_INT)
+	    {
+	      index_regno = UNKNOWN;
+	      base_regno = UNKNOWN;
+	    }
+	}
+    }
+  else if (GET_CODE (mem_addr) == MULT)
+    {
+      if (GET_CODE (XEXP (mem_addr, 0)) == REG 
+          && GET_CODE (XEXP (mem_addr, 1)) == CONST_INT)
+        {
+          index_regno = REGNO (XEXP (mem_addr, 0));
+          index_reg = (XEXP (mem_addr, 0));
+        }
+      else
+        {
+          index_regno = UNKNOWN;
+        }
+    }
+  mem_refs[indx].base_reg = base_reg;
+  mem_refs[indx].base_regno = base_regno;
+  mem_refs[indx].index_reg = index_reg;
+  mem_refs[indx].index_regno = index_regno;
+  if (base_regno == UNKNOWN || index_regno == UNKNOWN)
+    {
+      mem_refs[indx].varying = 1;
+      return;
+    }
+  if (base_regno >= max_regs_before_lift || index_regno >= max_regs_before_lift)
+    {
+      mem_refs[indx].varying = 1;
+      return;
+    }
+  if ( (base_regno == NO_REG || n_times_set[base_regno] == 0)
+      && (index_regno == NO_REG || n_times_set[index_regno] == 0))
+    {
+      mem_refs[indx].varying = 0;
+    }
+  if (MEM_VOLATILE_P (mem))
+    {
+      mem_refs[indx].varying = 1;
+    }
+}
+ 
+
+static void opt_reg_use_copy (f)
+  rtx f;
+{
+  rtx insn, src, prev;
+  int i, length;
+  char * fmt;
+  for (insn = f; insn; insn = NEXT_INSN (insn))
+    {
+      if (GET_CODE (insn) == INSN)
+        {
+  	  if (GET_CODE (PATTERN (insn)) == SET
+	      && GET_CODE (SET_DEST (PATTERN (insn))) == REG
+	      && GET_CODE (SET_SRC (PATTERN (insn))) == REG
+	      && (prev = PREV_INSN (insn))
+	      && GET_CODE (prev) == INSN
+	      && GET_CODE (PATTERN (prev)) == SET
+	      && rtx_equal_p (SET_SRC (PATTERN (insn)), 
+	                      SET_DEST (PATTERN (prev))))
+	    {
+              src = SET_SRC (PATTERN (prev));
+              fmt = GET_RTX_FORMAT (GET_CODE (src));
+              length = GET_RTX_LENGTH (GET_CODE (src));
+              for (i=0; i<length; i++)
+                {
+                  if (fmt[i] == 'e' 
+                      && GET_CODE (XEXP (src, i)) == REG
+                      && rtx_equal_p (XEXP (src, i), SET_DEST (PATTERN (insn))))
+                    {  
+                      SET_DEST (PATTERN (insn)) = SET_SRC (PATTERN (insn));
+                      SET_SRC (PATTERN (insn)) = XEXP (src, i);
+                      SET_DEST (PATTERN (prev)) = XEXP (src, i);
+                      emit_insn_after (gen_rtx (USE, 0, 
+                                                SET_DEST (PATTERN (prev))),
+                                       prev);
+                      break;
+                    }
+                }
+	    }
+	}
+    }
 }
diff -r -u -H -N gcc-2.6.3/loop.h gcc-i2.6.3/loop.h
--- gcc-2.6.3/loop.h	Fri Mar 19 21:10:47 1993
+++ gcc-i2.6.3/loop.h	Wed Feb 15 22:47:14 1995
@@ -87,6 +87,10 @@
   unsigned maybe_dead : 1;	/* 1 if this giv might be dead.  In that case,
 				   we won't use it to eliminate a biv, it
 				   would probably lose. */
+#ifdef REDUCE_INDEX
+  unsigned is_index_induc:1; /* 1 if this is actually the index portion
+                                of a DEST_ADDR g_type intel1 */
+#endif
   int lifetime;			/* Length of life of this giv */
   int times_used;		/* # times this giv is used. */
   rtx derive_adjustment;	/* If nonzero, is an adjustment to be
@@ -128,6 +132,8 @@
   unsigned nonneg : 1;		/* 1 if we added a REG_NONNEG note for this. */
   unsigned reversed : 1;	/* 1 if we reversed the loop that this
 				   biv controls. */
+  unsigned retry_celim :2; /*intel1 is >0 if we should retry compare 
+                             elimination at the end of strength reduction */
 };
 
 /* Definitions used by the basic induction variable discovery code.  */
diff -r -u -H -N gcc-2.6.3/objc/hash.s gcc-i2.6.3/objc/hash.s
--- gcc-2.6.3/objc/hash.s	Wed Dec 31 19:00:00 1969
+++ gcc-i2.6.3/objc/hash.s	Tue Nov  8 16:29:11 1994
@@ -0,0 +1,1028 @@
+	.file	1 "hash.c"
+	.option pic2
+
+ # GNU C 2.6.1 [AL 1.1, MM 40] SGI running IRIX 5.0 compiled by CC
+
+ # Cc1 defaults:
+ # -mabicalls
+
+ # Cc1 arguments (-G value = 0, Cpu = 3000, ISA = 1):
+ # -quiet -dumpbase -g -O -o
+
+gcc2_compiled.:
+__gnu_compiled_c:
+	.text
+	.def	ptrdiff_t;	.scl	13;	.etype	0x4;	.endef
+	.def	size_t;	.scl	13;	.etype	0xe;	.endef
+	.def	wchar_t;	.scl	13;	.etype	0x5;	.endef
+	.def	cache_node;	.scl	10;	.etype	0x8;	.esize	12;	.endef
+	.def	next;	.val	0;	.scl	8;	.tag	cache_node;	.esize	12;	.etype	0x18;	.endef
+	.def	key;	.val	4;	.scl	8;	.etype	0x11;	.endef
+	.def	value;	.val	8;	.scl	8;	.etype	0x11;	.endef
+	.def	.eos;	.val	12;	.scl	102;	.tag	cache_node;	.esize	12;	.endef
+	.def	node_ptr;	.scl	13;	.tag	cache_node;	.esize	12;	.etype	0x18;	.endef
+	.def	hash_func_type;	.scl	13;	.etype	0x9e;	.endef
+	.def	compare_func_type;	.scl	13;	.etype	0x94;	.endef
+	.def	cache;	.scl	10;	.etype	0x8;	.esize	28;	.endef
+	.def	node_table;	.val	0;	.scl	8;	.tag	cache_node;	.esize	12;	.etype	0x58;	.endef
+	.def	size;	.val	4;	.scl	8;	.etype	0xe;	.endef
+	.def	used;	.val	8;	.scl	8;	.etype	0xe;	.endef
+	.def	mask;	.val	12;	.scl	8;	.etype	0xe;	.endef
+	.def	last_bucket;	.val	16;	.scl	8;	.etype	0xe;	.endef
+	.def	hash_func;	.val	20;	.scl	8;	.etype	0x9e;	.endef
+	.def	compare_func;	.val	24;	.scl	8;	.etype	0x94;	.endef
+	.def	.eos;	.val	28;	.scl	102;	.tag	cache;	.esize	28;	.endef
+	.def	cache_ptr;	.scl	13;	.tag	cache;	.esize	28;	.etype	0x18;	.endef
+	.def	BOOL;	.scl	13;	.etype	0xc;	.endef
+	.def	objc_selector;	.scl	10;	.etype	0x8;	.esize	8;	.endef
+	.def	sel_id;	.val	0;	.scl	8;	.etype	0x11;	.endef
+	.def	sel_types;	.val	4;	.scl	8;	.etype	0x1c;	.endef
+	.def	.eos;	.val	8;	.scl	102;	.tag	objc_selector;	.esize	8;	.endef
+	.def	SEL;	.scl	13;	.tag	objc_selector;	.esize	8;	.etype	0x18;	.endef
+	.def	objc_object;	.scl	10;	.etype	0x8;	.esize	4;	.endef
+	.def	class_pointer;	.val	0;	.scl	8;	.tag	objc_class;	.esize	0;	.etype	0x18;	.endef
+	.def	.eos;	.val	4;	.scl	102;	.tag	objc_object;	.esize	4;	.endef
+	.def	id;	.scl	13;	.tag	objc_object;	.esize	4;	.etype	0x18;	.endef
+	.def	IMP;	.scl	13;	.tag	objc_object;	.esize	4;	.etype	0x198;	.endef
+	.def	STR;	.scl	13;	.etype	0x1c;	.endef
+	.def	MetaClass;	.scl	13;	.tag	objc_class;	.esize	0;	.etype	0x8;	.endef
+	.def	Class;	.scl	13;	.tag	objc_class;	.esize	0;	.etype	0x8;	.endef
+	.def	objc_class;	.scl	10;	.etype	0x8;	.esize	48;	.endef
+	.def	class_pointer;	.val	0;	.scl	8;	.tag	objc_class;	.esize	48;	.etype	0x18;	.endef
+	.def	super_class;	.val	4;	.scl	8;	.tag	objc_class;	.esize	48;	.etype	0x18;	.endef
+	.def	name;	.val	8;	.scl	8;	.etype	0x1c;	.endef
+	.def	version;	.val	12;	.scl	8;	.etype	0x5;	.endef
+	.def	info;	.val	16;	.scl	8;	.etype	0xf;	.endef
+	.def	instance_size;	.val	20;	.scl	8;	.etype	0x5;	.endef
+	.def	ivars;	.val	24;	.scl	8;	.tag	objc_ivar_list;	.esize	0;	.etype	0x18;	.endef
+	.def	methods;	.val	28;	.scl	8;	.tag	objc_method_list;	.esize	0;	.etype	0x18;	.endef
+	.def	dtable;	.val	32;	.scl	8;	.tag	sarray;	.esize	0;	.etype	0x18;	.endef
+	.def	subclass_list;	.val	36;	.scl	8;	.tag	objc_class;	.esize	48;	.etype	0x18;	.endef
+	.def	sibling_class;	.val	40;	.scl	8;	.tag	objc_class;	.esize	48;	.etype	0x18;	.endef
+	.def	protocols;	.val	44;	.scl	8;	.tag	objc_protocol_list;	.esize	0;	.etype	0x18;	.endef
+	.def	.eos;	.val	48;	.scl	102;	.tag	objc_class;	.esize	48;	.endef
+	.def	objc_protocol;	.scl	10;	.etype	0x8;	.esize	20;	.endef
+	.def	class_pointer;	.val	0;	.scl	8;	.tag	objc_class;	.esize	48;	.etype	0x18;	.endef
+	.def	protocol_name;	.val	4;	.scl	8;	.etype	0x1c;	.endef
+	.def	protocol_list;	.val	8;	.scl	8;	.tag	objc_protocol_list;	.esize	0;	.etype	0x18;	.endef
+	.def	instance_methods;	.val	12;	.scl	8;	.tag	objc_method_description_list;	.esize	0;	.etype	0x18;	.endef
+	.def	class_methods;	.val	16;	.scl	8;	.tag	objc_method_description_list;	.esize	0;	.etype	0x18;	.endef
+	.def	.eos;	.val	20;	.scl	102;	.tag	objc_protocol;	.esize	20;	.endef
+	.def	Protocol;	.scl	13;	.tag	objc_protocol;	.esize	20;	.etype	0x8;	.endef
+	.def	retval_t;	.scl	13;	.etype	0x11;	.endef
+	.def	apply_t;	.scl	13;	.etype	0x91;	.endef
+	.def	.0fake;	.scl	12;	.etype	0x9;	.esize	4;	.endef
+	.def	arg_ptr;	.val	0;	.scl	11;	.etype	0x1c;	.endef
+	.def	arg_regs;	.val	0;	.scl	11;	.dim	4;	.esize	4;	.etype	0x3c;	.endef
+	.def	.eos;	.val	4;	.scl	102;	.tag	.0fake;	.esize	4;	.endef
+	.def	arglist_t;	.scl	13;	.tag	.0fake;	.esize	4;	.etype	0x19;	.endef
+	.def	__gnuc_va_list;	.scl	13;	.etype	0x1c;	.endef
+	.def	va_list;	.scl	13;	.etype	0x1c;	.endef
+	.rdata
+
+	.byte	0x24,0x52,0x65,0x76,0x69,0x73,0x69,0x6f
+	.byte	0x6e,0x3a,0x20,0x31,0x2e,0x34,0x36,0x20
+	.byte	0x24,0x0
+	.text
+	.def	fpos_t;	.scl	13;	.etype	0x5;	.endef
+	.def	__file_s;	.scl	10;	.etype	0x8;	.esize	16;	.endef
+	.def	_cnt;	.val	0;	.scl	8;	.etype	0x4;	.endef
+	.def	_ptr;	.val	4;	.scl	8;	.etype	0x1c;	.endef
+	.def	_base;	.val	8;	.scl	8;	.etype	0x1c;	.endef
+	.def	_flag;	.val	12;	.scl	8;	.etype	0xc;	.endef
+	.def	_file;	.val	13;	.scl	8;	.etype	0xc;	.endef
+	.def	.eos;	.val	16;	.scl	102;	.tag	__file_s;	.esize	16;	.endef
+	.def	FILE;	.scl	13;	.tag	__file_s;	.esize	16;	.etype	0x8;	.endef
+	.rdata
+
+	.byte	0x24,0x52,0x65,0x76,0x69,0x73,0x69,0x6f
+	.byte	0x6e,0x3a,0x20,0x31,0x2e,0x32,0x30,0x20
+	.byte	0x24,0x0
+	.text
+	.def	objc_method_description;	.scl	10;	.etype	0x8;	.esize	8;	.endef
+	.def	name;	.val	0;	.scl	8;	.tag	objc_selector;	.esize	8;	.etype	0x18;	.endef
+	.def	types;	.val	4;	.scl	8;	.etype	0x1c;	.endef
+	.def	.eos;	.val	8;	.scl	102;	.tag	objc_method_description;	.esize	8;	.endef
+	.def	objc_symtab;	.scl	10;	.etype	0x8;	.esize	16;	.endef
+	.def	sel_ref_cnt;	.val	0;	.scl	8;	.etype	0xf;	.endef
+	.def	refs;	.val	4;	.scl	8;	.tag	objc_selector;	.esize	8;	.etype	0x18;	.endef
+	.def	cls_def_cnt;	.val	8;	.scl	8;	.etype	0xd;	.endef
+	.def	cat_def_cnt;	.val	10;	.scl	8;	.etype	0xd;	.endef
+	.def	defs;	.val	12;	.scl	8;	.dim	1;	.esize	4;	.etype	0x71;	.endef
+	.def	.eos;	.val	16;	.scl	102;	.tag	objc_symtab;	.esize	16;	.endef
+	.def	Symtab;	.scl	13;	.tag	objc_symtab;	.esize	16;	.etype	0x8;	.endef
+	.def	Symtab_t;	.scl	13;	.tag	objc_symtab;	.esize	16;	.etype	0x18;	.endef
+	.def	objc_module;	.scl	10;	.etype	0x8;	.esize	16;	.endef
+	.def	version;	.val	0;	.scl	8;	.etype	0xf;	.endef
+	.def	size;	.val	4;	.scl	8;	.etype	0xf;	.endef
+	.def	name;	.val	8;	.scl	8;	.etype	0x1c;	.endef
+	.def	symtab;	.val	12;	.scl	8;	.tag	objc_symtab;	.esize	16;	.etype	0x18;	.endef
+	.def	.eos;	.val	16;	.scl	102;	.tag	objc_module;	.esize	16;	.endef
+	.def	Module;	.scl	13;	.tag	objc_module;	.esize	16;	.etype	0x8;	.endef
+	.def	Module_t;	.scl	13;	.tag	objc_module;	.esize	16;	.etype	0x18;	.endef
+	.def	Ivar_t;	.scl	13;	.tag	objc_ivar;	.esize	0;	.etype	0x18;	.endef
+	.def	objc_ivar;	.scl	10;	.etype	0x8;	.esize	12;	.endef
+	.def	ivar_name;	.val	0;	.scl	8;	.etype	0x1c;	.endef
+	.def	ivar_type;	.val	4;	.scl	8;	.etype	0x1c;	.endef
+	.def	ivar_offset;	.val	8;	.scl	8;	.etype	0x4;	.endef
+	.def	.eos;	.val	12;	.scl	102;	.tag	objc_ivar;	.esize	12;	.endef
+	.def	objc_ivar_list;	.scl	10;	.etype	0x8;	.esize	16;	.endef
+	.def	ivar_count;	.val	0;	.scl	8;	.etype	0x4;	.endef
+	.def	ivar_list;	.val	4;	.scl	8;	.tag	objc_ivar;	.dim	1;	.esize	12;	.etype	0x38;	.endef
+	.def	.eos;	.val	16;	.scl	102;	.tag	objc_ivar_list;	.esize	16;	.endef
+	.def	IvarList;	.scl	13;	.tag	objc_ivar_list;	.esize	16;	.etype	0x8;	.endef
+	.def	IvarList_t;	.scl	13;	.tag	objc_ivar_list;	.esize	16;	.etype	0x18;	.endef
+	.def	Method;	.scl	13;	.tag	objc_method;	.esize	0;	.etype	0x8;	.endef
+	.def	Method_t;	.scl	13;	.tag	objc_method;	.esize	0;	.etype	0x18;	.endef
+	.def	objc_method;	.scl	10;	.etype	0x8;	.esize	12;	.endef
+	.def	method_name;	.val	0;	.scl	8;	.tag	objc_selector;	.esize	8;	.etype	0x18;	.endef
+	.def	method_types;	.val	4;	.scl	8;	.etype	0x1c;	.endef
+	.def	method_imp;	.val	8;	.scl	8;	.tag	objc_object;	.esize	4;	.etype	0x198;	.endef
+	.def	.eos;	.val	12;	.scl	102;	.tag	objc_method;	.esize	12;	.endef
+	.def	objc_method_list;	.scl	10;	.etype	0x8;	.esize	20;	.endef
+	.def	method_next;	.val	0;	.scl	8;	.tag	objc_method_list;	.esize	20;	.etype	0x18;	.endef
+	.def	method_count;	.val	4;	.scl	8;	.etype	0x4;	.endef
+	.def	method_list;	.val	8;	.scl	8;	.tag	objc_method;	.dim	1;	.esize	12;	.etype	0x38;	.endef
+	.def	.eos;	.val	20;	.scl	102;	.tag	objc_method_list;	.esize	20;	.endef
+	.def	MethodList;	.scl	13;	.tag	objc_method_list;	.esize	20;	.etype	0x8;	.endef
+	.def	MethodList_t;	.scl	13;	.tag	objc_method_list;	.esize	20;	.etype	0x18;	.endef
+	.def	objc_protocol_list;	.scl	10;	.etype	0x8;	.esize	12;	.endef
+	.def	next;	.val	0;	.scl	8;	.tag	objc_protocol_list;	.esize	12;	.etype	0x18;	.endef
+	.def	count;	.val	4;	.scl	8;	.etype	0x4;	.endef
+	.def	list;	.val	8;	.scl	8;	.tag	objc_protocol;	.dim	1;	.esize	4;	.etype	0x78;	.endef
+	.def	.eos;	.val	12;	.scl	102;	.tag	objc_protocol_list;	.esize	12;	.endef
+	.def	objc_category;	.scl	10;	.etype	0x8;	.esize	20;	.endef
+	.def	category_name;	.val	0;	.scl	8;	.etype	0x1c;	.endef
+	.def	class_name;	.val	4;	.scl	8;	.etype	0x1c;	.endef
+	.def	instance_methods;	.val	8;	.scl	8;	.tag	objc_method_list;	.esize	20;	.etype	0x18;	.endef
+	.def	class_methods;	.val	12;	.scl	8;	.tag	objc_method_list;	.esize	20;	.etype	0x18;	.endef
+	.def	protocols;	.val	16;	.scl	8;	.tag	objc_protocol_list;	.esize	12;	.etype	0x18;	.endef
+	.def	.eos;	.val	20;	.scl	102;	.tag	objc_category;	.esize	20;	.endef
+	.def	Category;	.scl	13;	.tag	objc_category;	.esize	20;	.etype	0x8;	.endef
+	.def	Category_t;	.scl	13;	.tag	objc_category;	.esize	20;	.etype	0x18;	.endef
+	.def	objc_super;	.scl	10;	.etype	0x8;	.esize	8;	.endef
+	.def	self;	.val	0;	.scl	8;	.tag	objc_object;	.esize	4;	.etype	0x18;	.endef
+	.def	class;	.val	4;	.scl	8;	.tag	objc_class;	.esize	48;	.etype	0x18;	.endef
+	.def	.eos;	.val	8;	.scl	102;	.tag	objc_super;	.esize	8;	.endef
+	.def	Super;	.scl	13;	.tag	objc_super;	.esize	8;	.etype	0x8;	.endef
+	.def	Super_t;	.scl	13;	.tag	objc_super;	.esize	8;	.etype	0x18;	.endef
+	.rdata
+	.align	2
+$LC0:
+
+	.byte	0x4e,0x69,0x6c,0x0
+	.text
+	.def	objc_list;	.scl	10;	.etype	0x8;	.esize	8;	.endef
+	.def	head;	.val	0;	.scl	8;	.etype	0x11;	.endef
+	.def	tail;	.val	4;	.scl	8;	.tag	objc_list;	.esize	8;	.etype	0x18;	.endef
+	.def	.eos;	.val	8;	.scl	102;	.tag	objc_list;	.esize	8;	.endef
+	.align	2
+	.def	list_free;	.val	list_free;	.scl	3;	.etype	0x21;	.endef
+	.file	2 "../objc/list.h"
+
+	.loc	2 139
+	.ent	list_free
+list_free:
+	.frame	$sp,40,$31		# vars= 0, regs= 3/0, args= 16, extra= 8
+	.mask	0x90010000,-8
+	.fmask	0x00000000,0
+	.set	noreorder
+	.cpload	$25
+	.set	reorder
+	subu	$sp,$sp,40
+	.cprestore 16
+	sw	$31,32($sp)
+	sw	$28,28($sp)
+	sw	$16,24($sp)
+	move	$16,$4
+	.def	list;	.val	16;	.scl	17;	.tag	objc_list;	.esize	8;	.etype	0x18;	.endef
+
+	.loc	2 140
+$Lb0:
+	.begin	$Lb0	2
+	beq	$16,$0,$L113
+
+	.loc	2 142
+$Lb1:
+	.begin	$Lb1	4
+	lw	$4,4($16)
+	jal	list_free
+
+	.loc	2 143
+	move	$4,$16
+	jal	free
+
+	.loc	2 144
+$Le2:
+	.bend	$Le2	6
+$L113:
+
+	.loc	2 145
+$Le3:
+	.bend	$Le3	7
+	lw	$31,32($sp)
+	lw	$16,24($sp)
+	addu	$sp,$sp,40
+	j	$31
+	.end	list_free
+	.rdata
+	.align	2
+$LC1:
+
+	.byte	0x25,0x73,0x3a,0x25,0x75,0x3a,0x20,0x66
+	.byte	0x61,0x69,0x6c,0x65,0x64,0x20,0x61,0x73
+	.byte	0x73,0x65,0x72,0x74,0x69,0x6f,0x6e,0x20
+	.byte	0x60,0x25,0x73,0x27,0xa,0x0
+	.align	2
+$LC2:
+
+	.byte	0x68,0x61,0x73,0x68,0x2e,0x63,0x0
+	.align	2
+$LC3:
+
+	.byte	0x73,0x69,0x7a,0x65,0x0
+	.align	2
+$LC4:
+
+	.byte	0x21,0x28,0x73,0x69,0x7a,0x65,0x20,0x26
+	.byte	0x20,0x28,0x73,0x69,0x7a,0x65,0x20,0x2d
+	.byte	0x20,0x31,0x29,0x29,0x0
+	.align	2
+$LC5:
+
+	.byte	0x63,0x61,0x63,0x68,0x65,0x0
+	.align	2
+$LC6:
+
+	.byte	0x63,0x61,0x63,0x68,0x65,0x2d,0x3e,0x6e
+	.byte	0x6f,0x64,0x65,0x5f,0x74,0x61,0x62,0x6c
+	.byte	0x65,0x0
+	.text
+	.align	2
+	.def	hash_new;	.val	hash_new;	.scl	2;	.tag	cache;	.esize	28;	.etype	0x68;	.endef
+	.globl	hash_new
+	.file	3 "hash.c"
+
+	.loc	3 47
+	.ent	hash_new
+hash_new:
+	.frame	$sp,48,$31		# vars= 0, regs= 6/0, args= 16, extra= 8
+	.mask	0x900f0000,-4
+	.fmask	0x00000000,0
+	.set	noreorder
+	.cpload	$25
+	.set	reorder
+	subu	$sp,$sp,48
+	.cprestore 16
+	sw	$31,44($sp)
+	sw	$28,40($sp)
+	sw	$19,36($sp)
+	sw	$18,32($sp)
+	sw	$17,28($sp)
+	sw	$16,24($sp)
+	move	$17,$4
+	move	$18,$5
+	.def	size;	.val	17;	.scl	17;	.etype	0xe;	.endef
+	.def	hash_func;	.val	18;	.scl	17;	.etype	0x9e;	.endef
+	.def	compare_func;	.val	19;	.scl	17;	.etype	0x94;	.endef
+
+	.loc	3 48
+$Lb4:
+	.begin	$Lb4	2
+	.def	cache;	.val	16;	.scl	4;	.tag	cache;	.esize	28;	.etype	0x18;	.endef
+
+	.loc	3 51
+	.set	noreorder
+	.set	nomacro
+	bne	$17,$0,$L116
+	move	$19,$6
+	.set	macro
+	.set	reorder
+
+	la	$4,$LC1
+	la	$5,$LC2
+	li	$6,0x00000033		# 51
+	la	$7,$LC3
+	jal	__eprintf
+$L116:
+
+	.loc	3 52
+	addu	$2,$17,-1
+	and	$2,$17,$2
+	.set	noreorder
+	.set	nomacro
+	beq	$2,$0,$L118
+	li	$6,0x00000034		# 52
+	.set	macro
+	.set	reorder
+
+	la	$4,$LC1
+	la	$5,$LC2
+	la	$7,$LC4
+	jal	__eprintf
+$L118:
+
+	.loc	3 56
+	li	$4,0x00000001		# 1
+	li	$5,0x0000001c		# 28
+	jal	__objc_xcalloc
+	move	$16,$2
+
+	.loc	3 57
+	.set	noreorder
+	.set	nomacro
+	bne	$16,$0,$L123
+	move	$4,$17
+	.set	macro
+	.set	reorder
+
+	la	$4,$LC1
+	la	$5,$LC2
+	li	$6,0x00000039		# 57
+	la	$7,$LC5
+	jal	__eprintf
+
+	.loc	3 61
+	move	$4,$17
+$L123:
+	li	$5,0x00000004		# 4
+	jal	__objc_xcalloc
+
+	.loc	3 63
+	.set	noreorder
+	.set	nomacro
+	bne	$2,$0,$L122
+	sw	$2,0($16)
+	.set	macro
+	.set	reorder
+
+	la	$4,$LC1
+	la	$5,$LC2
+	li	$6,0x0000003f		# 63
+	la	$7,$LC6
+	jal	__eprintf
+$L122:
+
+	.loc	3 65
+	sw	$17,4($16)
+
+	.loc	3 68
+	addu	$2,$17,-1
+	sw	$2,12($16)
+
+	.loc	3 71
+	sw	$18,20($16)
+
+	.loc	3 75
+	sw	$19,24($16)
+
+	.loc	3 77
+	move	$2,$16
+
+	.loc	3 78
+$Le5:
+	.bend	$Le5	32
+	lw	$31,44($sp)
+	lw	$19,36($sp)
+	lw	$18,32($sp)
+	lw	$17,28($sp)
+	lw	$16,24($sp)
+	addu	$sp,$sp,48
+	j	$31
+	.end	hash_new
+	.align	2
+	.def	hash_delete;	.val	hash_delete;	.scl	2;	.etype	0x21;	.endef
+	.globl	hash_delete
+
+	.loc	3 83
+	.ent	hash_delete
+hash_delete:
+	.frame	$sp,40,$31		# vars= 0, regs= 3/0, args= 16, extra= 8
+	.mask	0x90010000,-8
+	.fmask	0x00000000,0
+	.set	noreorder
+	.cpload	$25
+	.set	reorder
+	subu	$sp,$sp,40
+	.cprestore 16
+	sw	$31,32($sp)
+	sw	$28,28($sp)
+	sw	$16,24($sp)
+	move	$16,$4
+	.def	cache;	.val	16;	.scl	17;	.tag	cache;	.esize	28;	.etype	0x18;	.endef
+
+	.loc	3 84
+$Lb6:
+	.begin	$Lb6	2
+	.def	node;	.val	2;	.scl	4;	.tag	cache_node;	.esize	12;	.etype	0x18;	.endef
+
+	.loc	3 88
+	move	$4,$16
+$L128:
+	move	$5,$0
+	jal	hash_next
+	.set	noreorder
+	.set	nomacro
+	beq	$2,$0,$L126
+	move	$4,$16
+	.set	macro
+	.set	reorder
+
+
+	.loc	3 89
+	lw	$5,4($2)
+	jal	hash_remove
+	.set	noreorder
+	.set	nomacro
+	j	$L128
+	move	$4,$16
+	.set	macro
+	.set	reorder
+
+$L126:
+
+	.loc	3 92
+	lw	$4,0($16)
+	jal	free
+
+	.loc	3 93
+	move	$4,$16
+	jal	free
+
+	.loc	3 94
+$Le7:
+	.bend	$Le7	12
+	lw	$31,32($sp)
+	lw	$16,24($sp)
+	addu	$sp,$sp,40
+	j	$31
+	.end	hash_delete
+	.rdata
+	.align	2
+$LC7:
+
+	.byte	0x6e,0x6f,0x64,0x65,0x0
+	.text
+	.align	2
+	.def	hash_add;	.val	hash_add;	.scl	2;	.etype	0x21;	.endef
+	.globl	hash_add
+
+	.loc	3 99
+	.ent	hash_add
+hash_add:
+	.frame	$sp,64,$31		# vars= 8, regs= 7/0, args= 16, extra= 8
+	.mask	0x901f0000,-8
+	.fmask	0x00000000,0
+	.set	noreorder
+	.cpload	$25
+	.set	reorder
+	subu	$sp,$sp,64
+	.cprestore 16
+	sw	$31,56($sp)
+	sw	$28,52($sp)
+	sw	$20,48($sp)
+	sw	$19,44($sp)
+	sw	$18,40($sp)
+	sw	$17,36($sp)
+	sw	$16,32($sp)
+	move	$17,$4
+	move	$18,$5
+	move	$20,$6
+	.def	cachep;	.val	17;	.scl	17;	.tag	cache;	.esize	28;	.etype	0x58;	.endef
+	.def	key;	.val	18;	.scl	17;	.etype	0x11;	.endef
+	.def	value;	.val	20;	.scl	17;	.etype	0x11;	.endef
+
+	.loc	3 100
+$Lb8:
+	.begin	$Lb8	2
+	.def	indx;	.val	19;	.scl	4;	.etype	0xe;	.endef
+	.def	node;	.val	16;	.scl	4;	.tag	cache_node;	.esize	12;	.etype	0x18;	.endef
+	lw	$4,0($17)
+	#nop
+	lw	$2,20($4)
+	#nop
+	move	$25,$2
+	jal	$31,$25
+	move	$19,$2
+
+	.loc	3 101
+	li	$4,0x00000001		# 1
+	li	$5,0x0000000c		# 12
+	jal	__objc_xcalloc
+	move	$16,$2
+
+	.loc	3 104
+	.set	noreorder
+	.set	nomacro
+	bne	$16,$0,$L131
+	li	$6,0x00000068		# 104
+	.set	macro
+	.set	reorder
+
+	la	$4,$LC1
+	la	$5,$LC2
+	la	$7,$LC7
+	jal	__eprintf
+$L131:
+
+	.loc	3 107
+	sw	$18,4($16)
+
+	.loc	3 108
+	sw	$20,8($16)
+
+	.loc	3 109
+	lw	$2,0($17)
+	#nop
+	lw	$2,0($2)
+	sll	$3,$19,2
+	addu	$2,$3,$2
+	lw	$2,0($2)
+	#nop
+	sw	$2,0($16)
+
+	.loc	3 125
+	lw	$2,0($17)
+	#nop
+	lw	$2,0($2)
+	#nop
+	addu	$3,$3,$2
+	sw	$16,0($3)
+
+	.loc	3 128
+	lw	$3,0($17)
+	#nop
+	lw	$2,8($3)
+	#nop
+	addu	$2,$2,1
+	sw	$2,8($3)
+
+	.loc	3 132
+	lw	$6,0($17)
+	#nop
+	lw	$4,4($6)
+	#nop
+	sll	$3,$4,2
+	addu	$3,$3,$4
+	sll	$2,$3,4
+	subu	$2,$2,$3
+	li	$3,0x51eb851f		# 1374389535
+	multu	$2,$3
+	mfhi	$2
+	#nop
+	#nop
+	srl	$2,$2,5
+	lw	$3,8($6)
+	#nop
+	sltu	$3,$3,$2
+	.set	noreorder
+	.set	nomacro
+	bne	$3,$0,$L132
+	move	$16,$0
+	.set	macro
+	.set	reorder
+
+
+	.loc	3 140
+$Lb9:
+	.begin	$Lb9	42
+	.def	node1;	.val	16;	.scl	4;	.tag	cache_node;	.esize	12;	.etype	0x18;	.endef
+	.def	new;	.val	-40;	.scl	1;	.tag	cache;	.esize	28;	.etype	0x18;	.endef
+
+	.loc	3 141
+	sll	$4,$4,1
+	lw	$5,20($6)
+	lw	$6,24($6)
+	jal	hash_new
+	sw	$2,24($sp)
+
+	.loc	3 149
+$L133:
+	lw	$4,0($17)
+	move	$5,$16
+	jal	hash_next
+	move	$16,$2
+	.set	noreorder
+	.set	nomacro
+	beq	$16,$0,$L134
+	addu	$4,$sp,24
+	.set	macro
+	.set	reorder
+
+
+	.loc	3 150
+	lw	$5,4($16)
+	lw	$6,8($16)
+	jal	hash_add
+	j	$L133
+$L134:
+
+	.loc	3 153
+	lw	$4,0($17)
+	jal	hash_delete
+
+	.loc	3 156
+	lw	$2,24($sp)
+	#nop
+	sw	$2,0($17)
+
+	.loc	3 157
+$Le10:
+	.bend	$Le10	59
+$L132:
+
+	.loc	3 158
+$Le11:
+	.bend	$Le11	60
+	lw	$31,56($sp)
+	lw	$20,48($sp)
+	lw	$19,44($sp)
+	lw	$18,40($sp)
+	lw	$17,36($sp)
+	lw	$16,32($sp)
+	addu	$sp,$sp,64
+	j	$31
+	.end	hash_add
+	.rdata
+	.align	2
+$LC8:
+
+	.byte	0x72,0x65,0x6d,0x6f,0x76,0x65,0x64,0x0
+	.text
+	.align	2
+	.def	hash_remove;	.val	hash_remove;	.scl	2;	.etype	0x21;	.endef
+	.globl	hash_remove
+
+	.loc	3 163
+	.ent	hash_remove
+hash_remove:
+	.frame	$sp,56,$31		# vars= 0, regs= 7/0, args= 16, extra= 8
+	.mask	0x901f0000,-8
+	.fmask	0x00000000,0
+	.set	noreorder
+	.cpload	$25
+	.set	reorder
+	subu	$sp,$sp,56
+	.cprestore 16
+	sw	$31,48($sp)
+	sw	$28,44($sp)
+	sw	$20,40($sp)
+	sw	$19,36($sp)
+	sw	$18,32($sp)
+	sw	$17,28($sp)
+	sw	$16,24($sp)
+	move	$19,$4
+	move	$20,$5
+	.def	cache;	.val	19;	.scl	17;	.tag	cache;	.esize	28;	.etype	0x18;	.endef
+	.def	key;	.val	20;	.scl	17;	.etype	0x11;	.endef
+
+	.loc	3 164
+$Lb12:
+	.begin	$Lb12	2
+	.def	indx;	.val	17;	.scl	4;	.etype	0xe;	.endef
+	.def	node;	.val	16;	.scl	4;	.tag	cache_node;	.esize	12;	.etype	0x18;	.endef
+	lw	$2,20($19)
+	#nop
+	move	$25,$2
+	jal	$31,$25
+	move	$17,$2
+
+	.loc	3 165
+	lw	$3,0($19)
+	sll	$2,$17,2
+	addu	$2,$2,$3
+	lw	$16,0($2)
+
+	.loc	3 169
+	#nop
+	.set	noreorder
+	.set	nomacro
+	bne	$16,$0,$L138
+	li	$6,0x000000a9		# 169
+	.set	macro
+	.set	reorder
+
+	la	$4,$LC1
+	la	$5,$LC2
+	la	$7,$LC7
+	jal	__eprintf
+$L138:
+
+	.loc	3 172
+	lw	$2,24($19)
+	lw	$4,4($16)
+	move	$5,$20
+	move	$25,$2
+	jal	$31,$25
+	.set	noreorder
+	.set	nomacro
+	beq	$2,$0,$L139
+	sll	$3,$17,2
+	.set	macro
+	.set	reorder
+
+
+	.loc	3 173
+$Lb13:
+	.begin	$Lb13	11
+	lw	$2,0($19)
+	#nop
+	addu	$3,$3,$2
+	lw	$2,0($16)
+	#nop
+	sw	$2,0($3)
+
+	.loc	3 174
+	move	$4,$16
+	jal	free
+
+	.loc	3 175
+$Le14:
+	.bend	$Le14	13
+	j	$L140
+$L139:
+
+	.loc	3 178
+$Lb15:
+	.begin	$Lb15	16
+	.def	prev;	.val	18;	.scl	4;	.tag	cache_node;	.esize	12;	.etype	0x18;	.endef
+	.def	removed;	.val	17;	.scl	4;	.etype	0xc;	.endef
+	move	$18,$16
+
+	.loc	3 179
+	move	$17,$0
+$L141:
+
+	.loc	3 183
+	lw	$2,24($19)
+	lw	$4,4($16)
+	move	$5,$20
+	move	$25,$2
+	jal	$31,$25
+	.set	noreorder
+	.set	nomacro
+	beq	$2,$0,$L144
+	move	$4,$16
+	.set	macro
+	.set	reorder
+
+
+	.loc	3 184
+$Lb16:
+	.begin	$Lb16	22
+	lw	$2,0($16)
+	#nop
+	sw	$2,0($18)
+
+	.loc	3 185
+	jal	free
+
+	.loc	3 186
+$Le17:
+	.bend	$Le17	24
+	.set	noreorder
+	.set	nomacro
+	j	$L143
+	li	$17,0x00000001		# 1
+	.set	macro
+	.set	reorder
+
+$L144:
+
+	.loc	3 187
+	move	$18,$16
+	lw	$16,0($16)
+
+	.loc	3 188
+$L143:
+	andi	$2,$17,0x00ff
+	bne	$2,$0,$L140
+	bne	$16,$0,$L141
+
+	.loc	3 189
+	.set	noreorder
+	.set	nomacro
+	bne	$2,$0,$L140
+	li	$6,0x000000bd		# 189
+	.set	macro
+	.set	reorder
+
+	la	$4,$LC1
+	la	$5,$LC2
+	la	$7,$LC8
+	jal	__eprintf
+
+	.loc	3 190
+$Le18:
+	.bend	$Le18	28
+$L140:
+
+	.loc	3 193
+	lw	$2,8($19)
+	#nop
+	addu	$2,$2,-1
+	sw	$2,8($19)
+
+	.loc	3 194
+$Le19:
+	.bend	$Le19	32
+	lw	$31,48($sp)
+	lw	$20,40($sp)
+	lw	$19,36($sp)
+	lw	$18,32($sp)
+	lw	$17,28($sp)
+	lw	$16,24($sp)
+	addu	$sp,$sp,56
+	j	$31
+	.end	hash_remove
+	.align	2
+	.def	hash_next;	.val	hash_next;	.scl	2;	.tag	cache_node;	.esize	12;	.etype	0x68;	.endef
+	.globl	hash_next
+
+	.loc	3 199
+	.ent	hash_next
+hash_next:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, extra= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.cpload	$25
+	.set	reorder
+	.def	cache;	.val	4;	.scl	17;	.tag	cache;	.esize	28;	.etype	0x18;	.endef
+	.def	node;	.val	5;	.scl	17;	.tag	cache_node;	.esize	12;	.etype	0x18;	.endef
+
+	.loc	3 202
+	bne	$5,$0,$L164
+
+	.loc	3 207
+	.set	noreorder
+	.set	nomacro
+	j	$L152
+	sw	$0,16($4)
+	.set	macro
+	.set	reorder
+
+$L164:
+
+	.loc	3 208
+	lw	$2,0($5)
+	#nop
+	bne	$2,$0,$L166
+
+	.loc	3 213
+	lw	$2,16($4)
+	#nop
+	addu	$2,$2,1
+	sw	$2,16($4)
+$L152:
+
+	.loc	3 218
+	lw	$2,16($4)
+	#nop
+	move	$5,$2
+	lw	$3,4($4)
+	#nop
+	sltu	$2,$2,$3
+	.set	noreorder
+	.set	nomacro
+	beq	$2,$0,$L166
+	move	$2,$0
+	.set	macro
+	.set	reorder
+
+
+	.loc	3 221
+	lw	$6,0($4)
+
+	.loc	3 222
+	sll	$2,$5,2
+$L167:
+	addu	$2,$2,$6
+	lw	$2,0($2)
+	#nop
+	bne	$2,$0,$L166
+
+	.loc	3 225
+	lw	$2,16($4)
+	#nop
+	addu	$2,$2,1
+	sw	$2,16($4)
+	move	$5,$2
+	sltu	$2,$2,$3
+	.set	noreorder
+	.set	nomacro
+	bne	$2,$0,$L167
+	sll	$2,$5,2
+	.set	macro
+	.set	reorder
+
+
+	.loc	3 223
+
+	.loc	3 230
+	move	$2,$0
+
+	.loc	3 231
+$L166:
+	j	$31
+	.end	hash_next
+	.align	2
+	.def	hash_value_for_key;	.val	hash_value_for_key;	.scl	2;	.etype	0x61;	.endef
+	.globl	hash_value_for_key
+
+	.loc	3 239
+	.ent	hash_value_for_key
+hash_value_for_key:
+	.frame	$sp,48,$31		# vars= 0, regs= 6/0, args= 16, extra= 8
+	.mask	0x900f0000,-4
+	.fmask	0x00000000,0
+	.set	noreorder
+	.cpload	$25
+	.set	reorder
+	subu	$sp,$sp,48
+	.cprestore 16
+	sw	$31,44($sp)
+	sw	$28,40($sp)
+	sw	$19,36($sp)
+	sw	$18,32($sp)
+	sw	$17,28($sp)
+	sw	$16,24($sp)
+	move	$18,$4
+	move	$19,$5
+	.def	cache;	.val	18;	.scl	17;	.tag	cache;	.esize	28;	.etype	0x18;	.endef
+	.def	key;	.val	19;	.scl	17;	.etype	0x11;	.endef
+
+	.loc	3 240
+$Lb20:
+	.begin	$Lb20	2
+	.def	node;	.val	16;	.scl	4;	.tag	cache_node;	.esize	12;	.etype	0x18;	.endef
+	.def	retval;	.val	17;	.scl	4;	.etype	0x11;	.endef
+	lw	$2,20($18)
+	#nop
+	move	$25,$2
+	jal	$31,$25
+	lw	$3,0($18)
+	sll	$2,$2,2
+	addu	$2,$2,$3
+	lw	$16,0($2)
+
+	.loc	3 243
+	#nop
+	.set	noreorder
+	.set	nomacro
+	beq	$16,$0,$L169
+	move	$17,$0
+	.set	macro
+	.set	reorder
+
+$L170:
+
+	.loc	3 245
+	lw	$2,24($18)
+	lw	$4,4($16)
+	move	$5,$19
+	move	$25,$2
+	jal	$31,$25
+	beq	$2,$0,$L173
+
+	.loc	3 246
+	lw	$17,8($16)
+	j	$L172
+$L173:
+
+	.loc	3 248
+	lw	$16,0($16)
+
+	.loc	3 249
+$L172:
+	.set	noreorder
+	.set	nomacro
+	bne	$17,$0,$L177
+	move	$2,$17
+	.set	macro
+	.set	reorder
+
+	bne	$16,$0,$L170
+$L169:
+
+	.loc	3 251
+	move	$2,$17
+
+	.loc	3 252
+$Le21:
+	.bend	$Le21	14
+$L177:
+	lw	$31,44($sp)
+	lw	$19,36($sp)
+	lw	$18,32($sp)
+	lw	$17,28($sp)
+	lw	$16,24($sp)
+	addu	$sp,$sp,48
+	j	$31
+	.end	hash_value_for_key
+
+	.globl free .text
+	.globl __objc_xcalloc .text
+	.globl __eprintf .text
+	.globl __objc_xmalloc .text
+	.globl strcmp .text
diff -r -u -H -N gcc-2.6.3/objc-parse.c gcc-i2.6.3/objc-parse.c
--- gcc-2.6.3/objc-parse.c	Sat Aug 27 13:52:13 1994
+++ gcc-i2.6.3/objc-parse.c	Tue Nov  8 16:00:38 1994
@@ -1720,23 +1720,8 @@
 #endif
 
 #line 184 "/usr/local/lib/bison.simple"
-
-/* The user can define YYPARSE_PARAM as the name of an argument to be passed
-   into yyparse.  The argument should have type void *.
-   It should actually point to an object.
-   Grammar actions can access the variable by casting it
-   to the proper pointer type.  */
-
-#ifdef YYPARSE_PARAM
-#define YYPARSE_PARAM_DECL void *YYPARSE_PARAM;
-#else
-#define YYPARSE_PARAM
-#define YYPARSE_PARAM_DECL
-#endif
-
 int
-yyparse(YYPARSE_PARAM)
-     YYPARSE_PARAM_DECL
+yyparse()
 {
   register int yystate;
   register int yyn;
@@ -4532,7 +4517,7 @@
     break;}
 }
    /* the action file gets copied in in place of this dollarsign */
-#line 480 "/usr/local/lib/bison.simple"
+#line 465 "/usr/local/lib/bison.simple"
 
   yyvsp -= yylen;
   yyssp -= yylen;
diff -r -u -H -N gcc-2.6.3/print-rtl.c gcc-i2.6.3/print-rtl.c
--- gcc-2.6.3/print-rtl.c	Wed Jun 30 13:26:11 1993
+++ gcc-i2.6.3/print-rtl.c	Thu Feb 16 13:18:50 1995
@@ -230,6 +230,16 @@
   fprintf (stderr, "\n");
 }
 
+void
+tdebug_rtx(x, file)
+	rtx x;
+	FILE *file;
+{
+  outfile=file;
+  print_rtx(x);
+  fprintf(file, "\n");
+}
+
 /* Count of rtx's to print with debug_rtx_list.
    This global exists because gdb user defined commands have no arguments.  */
 
diff -r -u -H -N gcc-2.6.3/reg-stack.c gcc-i2.6.3/reg-stack.c
--- gcc-2.6.3/reg-stack.c	Sat Nov  5 13:57:40 1994
+++ gcc-i2.6.3/reg-stack.c	Wed Feb 15 23:34:14 1995
@@ -228,6 +228,9 @@
   ((INSN_UID (INSN) > max_uid)	\
    ? (abort() , -1) : block_number[INSN_UID (INSN)])
 
+/* intel1 */
+extern FILE *stack_reg_dump_file;
+
 extern rtx forced_labels;
 extern rtx gen_jump ();
 extern rtx gen_movdf (), gen_movxf ();
@@ -2024,6 +2027,8 @@
 	replace_reg (dest, FIRST_STACK_REG);
 	break;
 
+      /* intel1 */
+      case FLOAT_EXTEND:
       case REG:
 	/* This is a `tstM2' case. */
 	if (*dest != cc0_rtx)
@@ -3003,4 +3008,2213 @@
       fprintf (file, "\n");
     }
 }
+/* intel1 */
+#ifdef IS_STACK_MODE
+#include "basic-block.h"
+#include "obstack.h"
+#define obstack_chunk_alloc xmalloc
+#define obstack_chunk_free free
+
+extern int regset_bytes;
+extern struct obstack momentary_obstack;
+extern rtx *regno_reg_rtx;
+extern int max_regno;
+
+static void func_stack_reg_to_stack_slot ();
+static void bb_stack_reg_to_stack_slot ();
+void float_to_int_cmp ();
+static void offload_if_necessary ();
+static void offload_reg ();
+static void replace_with_stack_slot ();
+static int stack_reg_dies_at_store ();
+static void mark_stack_regs_mentioned ();
+static void replace_with_temp_slot ();
+static int reg_dead_at_pred ();
+static int reg_only_set_or_stored ();
+static int reg_used_in_body ();
+static int store_into_temp ();
+static int visit_till_dies ();
+static int addr_or_val_changed ();
+static void find_regs_mentioned ();
+static int tests_equality ();
+static int reg_last_loaded ();
+static int reg_def_in_unvisited ();
+static rtx reg_dies_in_block ();
+static int death_blocks_ok ();
+
+/* For each basic block the union of the basic_block_live_at_start
+   of each of it's successors.  */
+regset *basic_block_maybe_live_at_end;
+
+/* To mark each block visited on a path */
+char *blocks_visited;
+
+/* To mark those blocks on the path where the reg dies.
+   It is set to the NEXT_INSN of the insn in the block where
+   the reg dies */
+rtx *death_blocks;
+
+/* To mark those blocks where the reg is defined */
+char *blocks_defined;
+
+/* For finding block sucessors */
+int *fall_thru_block, *jump_target_block;
+
+/* The temp slots allocated to stack regs */
+rtx *reg_temp_slot;
+
+int num_visits;
+
+/* Information collected for optimizing use of stack regs
+   within a basic block
+*/
+struct stack_reg_infos
+  {
+    rtx store_insn;
+    rtx non_dead_store[3];
+    rtx last_use;
+    unsigned char num_non_dead_store;
+    unsigned char dies_at_store;
+  }
+
+ *stack_reg_info;
+
+static
+struct regs_mentioned
+  {
+    rtx reg;
+    struct regs_mentioned *next;
+  } *reg_mentioned_header;
+
+void init_regset_vector ();
+
+void
+opt_reg_stack ()
+{
+
+  reg_temp_slot = (rtx *) alloca (max_regno * sizeof (rtx));
+  bzero (reg_temp_slot, max_regno * sizeof (rtx));
+
+  if (stack_reg_dump_file)
+    {
+      fprintf (stack_reg_dump_file," MAX_REGNO at start %d\n",max_regno);
+    }
+  func_stack_reg_to_stack_slot ();
+  bb_stack_reg_to_stack_slot ();
+#ifdef SPARE_REGS
+  max_regno = max_reg_num();
+  if (stack_reg_dump_file)
+    {
+      fprintf (stack_reg_dump_file," MAX_REGNO at end %d\n",max_regno);
+    }
+#endif
+}
+
+/*
+   Stack mode registers that are used only to move values
+   in a basic block are replaced with stack slots.
+   We also have something like this for between basic blocks
+   see the ear spec agc()/earfilters.c the last loop
+*/
+static void
+bb_stack_reg_to_stack_slot ()
+{
+  int block, nregs, stack_regno, num_calls;
+  rtx insn;
+
+  nregs = max_regno;
+  stack_reg_info = (struct stack_reg_infos *)
+    alloca (nregs * sizeof (struct stack_reg_infos));
+
+  for (block = 0; block < n_basic_blocks; block++)
+    {
+      bzero (stack_reg_info, nregs * sizeof (struct stack_reg_infos));
+      num_calls = 0;
+      for (insn = basic_block_end[block];
+	   insn && insn != PREV_INSN (basic_block_head[block]);
+	   insn = PREV_INSN (insn))
+	{
+	  if (GET_CODE (insn) == CALL_INSN)
+	    num_calls++;
+	  if (GET_CODE (insn) == INSN)
+	    {
+	      if (GET_CODE (PATTERN (insn)) != SET)
+		{
+		  if (GET_CODE (PATTERN (insn)) == PARALLEL)
+		    {
+		      if (flag_do_offload)
+			offload_if_necessary (insn, block);
+		    }
+		  bzero (stack_reg_info, nregs * sizeof (struct stack_reg_infos));
+		}
+	      else
+		{
+		  if (GET_CODE (SET_DEST (PATTERN (insn))) == REG
+		      && GET_MODE (SET_DEST (PATTERN (insn))) == SFmode
+		      && GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT_TRUNCATE)
+		    {
+		      rtx slot;
+		      slot 
+		        = assign_stack_local (SFmode, GET_MODE_SIZE (SFmode), -1);
+		      emit_insn_after (gen_rtx (SET, 0, SET_DEST (PATTERN (insn)),
+		                                slot), insn);
+		      SET_DEST (PATTERN (insn)) = slot;
+		    }
+		  stack_regno = -1;
+		  if (stack_reg_dies_at_store (insn, &stack_regno))
+		    { /* A store of stack_regno at which it dies.  */
+		      stack_reg_info[stack_regno].dies_at_store = 1;
+		      stack_reg_info[stack_regno].store_insn = insn;
+		      stack_reg_info[stack_regno].num_non_dead_store = 0;
+		    }
+		  else if (stack_regno != -1)
+		    {
+		      /* Stored but not dead.  */
+		      stack_reg_info[stack_regno].num_non_dead_store++;
+		      if (stack_reg_info[stack_regno].num_non_dead_store <= 3)
+			{
+			  stack_reg_info[stack_regno].non_dead_store
+			    [stack_reg_info[stack_regno].num_non_dead_store - 1] 
+			    = insn;
+			}
+		      else
+			{
+			  stack_reg_info[stack_regno].dies_at_store = 0;
+			  stack_reg_info[stack_regno].store_insn = NULL;
+			  stack_reg_info[stack_regno].last_use = NULL;
+			  stack_reg_info[stack_regno].num_non_dead_store = 0;
+			}
+		    }
+		  else
+		    mark_stack_regs_mentioned (SET_SRC (PATTERN (insn)), insn);
+		  if (GET_CODE (SET_DEST (PATTERN (insn))) != REG)
+		    mark_stack_regs_mentioned (SET_DEST (PATTERN (insn)), insn);
+		  if (GET_CODE (SET_DEST (PATTERN (insn))) == REG
+		      && IS_STACK_MODE (GET_MODE (SET_DEST (PATTERN (insn))))
+		    )
+		    { /* A setting of a stack register.  */
+		      if (((GET_CODE (SET_SRC (PATTERN (insn))) == MEM
+			     && !MEM_VOLATILE_P (SET_SRC (PATTERN (insn))))
+			   || GET_CODE (SET_SRC (PATTERN (insn))) == CONST_DOUBLE)
+			  && stack_reg_info[REGNO (SET_DEST (PATTERN (insn)))].dies_at_store)
+			{ /* It is loaded from a non volatile memory and
+			     was stored upon death later in the basic block,
+			     try to do this NOT via the register stack.  */
+			  replace_with_stack_slot (insn, block, num_calls);
+			}
+		      else
+			{ /* Just try to optimize consecutive stores and
+			     restart the information gathering.  
+			  */
+			  stack_regno = REGNO (SET_DEST (PATTERN (insn)));
+			  opt_consec_stores (stack_regno);
+			  stack_reg_info[stack_regno].dies_at_store = 0;
+			  stack_reg_info[stack_regno].store_insn = NULL;
+			  stack_reg_info[stack_regno].last_use = NULL;
+			  stack_reg_info[stack_regno].num_non_dead_store = 0;
+			}
+		    }
+		}
+	    }
+	}
+    }
+}
+
+/*
+    Change
+            fst   mem1
+            fstp  mem2
+    to
+           fstp  mem1
+           mov   mem1,mem2
+    regno is the number of the stack register being stored.  
+*/
+opt_consec_stores (regno)
+     int regno;
+{
+  rtx insn, note;
+
+  if (stack_reg_info[regno].store_insn
+      && stack_reg_info[regno].dies_at_store
+      && stack_reg_info[regno].num_non_dead_store != 0
+      && stack_reg_info[regno].non_dead_store[0] ==
+      PREV_INSN (stack_reg_info[regno].store_insn))
+    {
+      insn = stack_reg_info[regno].store_insn;
+      SET_SRC (PATTERN (insn)) 
+	= copy_rtx (SET_DEST (PATTERN (stack_reg_info[regno].non_dead_store[0])));
+      if (GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == PRE_DEC
+	  || GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == PRE_INC)
+	{
+	  XEXP (SET_SRC (PATTERN (insn)), 0) =
+	    XEXP (XEXP (SET_SRC (PATTERN (insn)), 0), 0);
+	}
+      INSN_CODE (insn) = recog (PATTERN (insn), insn, 0);
+      note = find_regno_note (insn, REG_DEAD, regno);
+      remove_note (insn, note);
+      if (!find_regno_note (stack_reg_info[regno].non_dead_store[0], REG_DEAD, regno))
+	{
+	  REG_NOTES (stack_reg_info[regno].non_dead_store[0])
+	    = gen_rtx (EXPR_LIST, REG_DEAD, regno_reg_rtx[regno],
+		       REG_NOTES (stack_reg_info[regno].non_dead_store[0]));
+	}
+    }
+}
+
+
+/*
+  If the register being compared is the result of a computation in
+  this block, and the second comparison operand is not so, and it is
+  being compared for equality.  
+    offload and reload it before the compare
+  The reason for this is that the stack registers are 80bit precision
+  and hence the comparison may fail due to precision.  
+*/
+
+static void
+offload_if_necessary (insn, blocknum)
+     rtx insn;
+     int blocknum;
+{
+  rtx cmp_part, new_insn, last_set_insn, assign_stack_local ();
+  int regno;
+
+  if (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
+    {
+      cmp_part = XVECEXP (PATTERN (insn), 0, 0);
+      last_set_insn = NULL;
+      if (SET_DEST (cmp_part) == cc0_rtx
+	  && GET_CODE (SET_SRC (cmp_part)) == COMPARE
+	  && GET_MODE (SET_SRC (cmp_part)) == CCmode)
+	{
+	  if (GET_CODE (XEXP (SET_SRC (cmp_part), 0)) == REG
+	      && GET_MODE (XEXP (SET_SRC (cmp_part), 0)) == DFmode
+	      && GET_CODE (XEXP (SET_SRC (cmp_part), 1)) != REG
+	      && !reg_last_loaded (blocknum, PREV_INSN (insn),
+		       REGNO (XEXP (SET_SRC (cmp_part), 0)), &last_set_insn)
+	      && last_set_insn
+	      && tests_equality (NEXT_INSN (insn)))
+	    {
+	      regno = REGNO (XEXP (SET_SRC (cmp_part), 0));
+	      if (reg_temp_slot[regno] == NULL)
+		{
+		  reg_temp_slot[regno] 
+		    = assign_stack_local (GET_MODE (XEXP (SET_SRC (cmp_part), 0)),
+		    GET_MODE_SIZE (GET_MODE (XEXP (SET_SRC (cmp_part), 0))),
+					-1);
+		}
+	      MEM_VOLATILE_P (reg_temp_slot[regno]) = 1;
+	      new_insn 
+		= emit_insn_before (
+				   gen_rtx (SET, 0,
+			reg_temp_slot[regno], XEXP (SET_SRC (cmp_part), 0)),
+				   insn);
+	      if (basic_block_head[blocknum] == insn)
+		{
+		  basic_block_head[blocknum] = new_insn;
+		}
+	      REG_NOTES (new_insn) 
+		= gen_rtx (EXPR_LIST, REG_DEAD,
+			 XEXP (SET_SRC (cmp_part), 0),
+			 REG_NOTES (new_insn));
+	      reg_n_deaths[regno]++;
+	      emit_insn_before (
+				 gen_rtx (SET, 0,
+			XEXP (SET_SRC (cmp_part), 0), reg_temp_slot[regno]),
+				 insn);
+	    }
+	}
+    }
+}
+
+
+/*
+  Return 1 if the insn which is a jump insn tests for equality or
+  inequality
+  else return 0
+*/
+
+static int
+tests_equality (insn)
+     rtx insn;
+{
+  if (GET_CODE (insn) == JUMP_INSN &&
+      GET_CODE (PATTERN (insn)) == SET &&
+      SET_DEST (PATTERN (insn)) == pc_rtx &&
+      GET_CODE (SET_SRC (PATTERN (insn))) == IF_THEN_ELSE &&
+      (GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == NE ||
+       GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == EQ))
+    {
+      return (1);
+    }
+  return (0);
+}
+
+
+/*
+   Search backward in block# blocknum, beginning at insn for a set of
+   reg# regno. 
+   if found
+     set *last_set_insn to that set
+     if the source that sets regno is one of the desired sources
+     (see below) return 1
+     else return 0
+   else return 0
+*/
+static int
+reg_last_loaded (blocknum, insn, regno, last_set_insn)
+     int blocknum, regno;
+     rtx insn, *last_set_insn;
+{
+  rtx last_set;
+  int found, i;
+
+  last_set = insn;
+  found = 0;
+  while (!found && last_set != PREV_INSN (basic_block_head[blocknum]))
+    {
+      if (GET_CODE (last_set) == INSN)
+	{
+	  if (GET_CODE (PATTERN (last_set)) == PARALLEL)
+	    {
+	      for (i = 0; i < XVECLEN (PATTERN (last_set), 0); i++)
+		{
+		  if (GET_CODE (XVECEXP (PATTERN (last_set), 0, i)) == SET)
+		    {
+		      if (GET_CODE (SET_DEST (XVECEXP (PATTERN (last_set), 0, i))) == REG &&
+			  REGNO (SET_DEST (XVECEXP (PATTERN (last_set), 0, i))) == regno)
+			{
+			  *last_set_insn = last_set;
+			  return (0);
+			}
+		    }
+		  else if (GET_CODE (XVECEXP (PATTERN (last_set), 0, i)) == CLOBBER)
+		    {
+		      if (GET_CODE (SET_DEST (XVECEXP (PATTERN (last_set), 0, i))) == REG &&
+			  REGNO (SET_DEST (XVECEXP (PATTERN (last_set), 0, i))) == regno)
+			{
+			  *last_set_insn = last_set;
+			  return (0);
+			}
+		    }
+		  else
+		    {
+		      return (0);
+		    }
+		}
+	    }
+	  if ((GET_CODE (PATTERN (last_set)) == SET ||
+	       GET_CODE (PATTERN (last_set)) == CLOBBER) &&
+	      GET_CODE (SET_DEST (PATTERN (last_set))) == REG &&
+	      REGNO (SET_DEST (PATTERN (last_set))) == regno)
+	    {
+	      if (GET_CODE (PATTERN (last_set)) == CLOBBER)
+		{
+		  *last_set_insn = last_set;
+		  return (0);
+		}
+	      if (GET_CODE (SET_SRC (PATTERN (last_set))) != MEM
+		  && GET_CODE (SET_SRC (PATTERN (last_set))) != CONST_DOUBLE
+		  && GET_CODE (SET_SRC (PATTERN (last_set))) != REG
+		  && GET_CODE (SET_SRC (PATTERN (last_set))) != SUBREG
+		  && GET_CODE (SET_SRC (PATTERN (last_set))) != FLOAT
+		  && GET_CODE (SET_SRC (PATTERN (last_set))) != FLOAT_EXTEND)
+		{
+		  *last_set_insn = last_set;
+		  return (0);
+		}
+	      else
+		{
+		  *last_set_insn = last_set;
+		  if (GET_CODE (SET_SRC (PATTERN (last_set))) == REG &&
+		      REGNO (SET_SRC (PATTERN (last_set))) < FIRST_PSEUDO_REGISTER)
+		    return (0);
+		  return (1);
+		}
+	    }
+	}
+      if (!found)
+	{
+	  last_set = PREV_INSN (last_set);
+	}
+    }
+  return (0);
+}
+
+
+/*
+  insn loads a stack reg from memory and later on in the block
+  at stack_reg_info[REGNO(SET_DEST(PATTERN(insn)))].store_insn
+  that stack reg is stored into memory and marked as dead.  Also
+  no insn between these two insns sets that stack reg. 
+  This procedure changes the store from the register stack to
+  a store from the regular stack - which is faster.  
+*/
+static void
+replace_with_stack_slot (insn, block_num, num_calls)
+     rtx insn;
+     int block_num, num_calls;
+{
+  rtx note, stack_slot, store_insn, new_insn;
+  rtx notes_to_move, assign_stack_local ();
+  int i, regno, mem_possibly_changed;
+  char *storage;
+
+  notes_to_move = NULL;
+  regno = REGNO (SET_DEST (PATTERN (insn)));
+  store_insn = stack_reg_info[regno].store_insn;
+  storage = (char *) obstack_alloc (&momentary_obstack, 0);
+
+  /* Check if the memory being loaded into the stack register may
+     possibly change between insn and store_insn.  
+  */
+  mem_possibly_changed 
+    = (GET_CODE (SET_SRC (PATTERN (insn))) == CONST_DOUBLE) ? 0 :
+      addr_or_val_changed (SET_SRC (PATTERN (insn)), insn, store_insn);
+  obstack_free (&momentary_obstack, storage);
+  if (stack_reg_dump_file)
+    {
+      fprintf (stack_reg_dump_file,
+	       "Offload stack reg%d used only within basic block insn %d store_insn %d\n",
+       regno, INSN_UID (insn), INSN_UID (stack_reg_info[regno].store_insn));
+      if (stack_reg_info[regno].last_use != NULL)
+	{
+	  fprintf (stack_reg_dump_file,
+		   " reg used at insn %d\n",
+		   INSN_UID (stack_reg_info[regno].last_use));
+	}
+    }
+  if (reg_temp_slot[regno] == NULL && mem_possibly_changed)
+    { /* Must allocate a stack slot */
+#ifdef SPARE_REGS
+      if (max_reg_num () < max_regno)
+        {
+          if (GET_MODE (SET_DEST (PATTERN (insn))) == SFmode)
+            reg_temp_slot[regno] = gen_reg_rtx (SImode);
+          else
+            reg_temp_slot[regno] 
+	      = assign_stack_local (GET_MODE (SET_DEST (PATTERN (insn))),
+		   GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (insn)))),
+			    -1);
+        }
+      else
+#endif
+        reg_temp_slot[regno] 
+	  = assign_stack_local (GET_MODE (SET_DEST (PATTERN (insn))),
+		       GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (insn)))),
+			    -1);
+    }
+  if (mem_possibly_changed)
+    /* Use the stack slot */
+    stack_slot = reg_temp_slot[regno];
+  else
+    /* The memory slot from which the stack register was loaded can be used */
+    stack_slot = SET_SRC (PATTERN (insn));
+  if (stack_reg_info[regno].last_use == NULL)
+    { /* The stack register was not used between the load and store */
+      if (mem_possibly_changed)
+	{
+	  SET_DEST (PATTERN (insn)) = stack_slot;
+	  if (GET_CODE (stack_slot) == REG)
+	    {
+              if (GET_CODE (SET_SRC (PATTERN (insn)))
+                  == CONST_DOUBLE)
+                {
+                  SET_SRC (PATTERN (insn)) = 
+                    gen_rtx (CONST_INT, 0, CONST_DOUBLE_HIGH (SET_SRC (PATTERN (insn))));
+                }
+              else
+                {
+	          PUT_MODE (SET_SRC (PATTERN (insn)), GET_MODE (stack_slot));
+	        }
+	    }
+	  INSN_CODE (insn) = recog (PATTERN (insn), insn, 0);
+	}
+      else
+	{
+	  PUT_CODE (insn, NOTE);
+	  NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
+	  NOTE_SOURCE_FILE (insn) = 0;
+	  notes_to_move = REG_NOTES (insn);
+	}
+    }
+  else
+    { /* The stack register was also used in some computation */
+      if (mem_possibly_changed)
+	{
+	  new_insn 
+	    = emit_insn_after (
+	  gen_rtx (SET, 0, stack_slot, copy_rtx (SET_SRC (PATTERN (insn)))),
+			      insn);
+	  if (GET_CODE (stack_slot) == REG)
+	    {
+	      PUT_MODE (SET_SRC (PATTERN (new_insn)), GET_MODE (stack_slot));
+	    }
+	  INSN_CODE (new_insn) = recog (PATTERN (new_insn), new_insn, 0);
+	}
+    }
+  SET_SRC (PATTERN (store_insn)) = stack_slot;
+  if (GET_CODE (stack_slot) == REG )
+    {
+      reg_n_refs[REGNO (stack_slot)]++;
+      reg_n_sets[REGNO (stack_slot)]++;
+      reg_n_calls_crossed[REGNO (stack_slot)] = num_calls;
+      reg_n_deaths[REGNO (stack_slot)]++;
+      if (reg_basic_block[REGNO (stack_slot)] != -1)
+        {
+          reg_basic_block[REGNO (stack_slot)] = REG_BLOCK_GLOBAL;
+        }
+      else
+        {
+          reg_basic_block[REGNO (stack_slot)] = block_num;
+        }
+      PUT_MODE (SET_DEST (PATTERN (store_insn)), GET_MODE (stack_slot));
+      REG_NOTES (store_insn) = 
+        gen_rtx (EXPR_LIST, REG_DEAD, stack_slot, REG_NOTES (store_insn));
+    }
+  INSN_CODE (store_insn) = recog (PATTERN (store_insn), store_insn, 0);
+  note = find_regno_note (store_insn, REG_DEAD, regno);
+  remove_note (store_insn, note);
+  if (notes_to_move)
+    { /* Maintain consistency of REG NOTE information */
+      rtx link, prev_link;
+      prev_link = REG_NOTES (store_insn);
+      for (link = REG_NOTES (store_insn); link; link = XEXP (link, 1))
+	{
+	  prev_link = link;
+	}
+      if (prev_link)
+	{
+	  XEXP (prev_link, 1) = notes_to_move;
+	}
+      else
+	{
+	  REG_NOTES (store_insn) = notes_to_move;
+	}
+    }
+  if (stack_reg_info[regno].last_use == NULL)
+    {
+      reg_n_deaths[regno]--;
+    }
+  else if (!find_regno_note (stack_reg_info[regno].last_use, REG_DEAD, regno))
+    {
+      REG_NOTES (stack_reg_info[regno].last_use)
+	= gen_rtx (EXPR_LIST, REG_DEAD, regno_reg_rtx[regno],
+		   REG_NOTES (stack_reg_info[regno].last_use));
+    }
+  for (i = 0;
+       i < (int) stack_reg_info[regno].num_non_dead_store;
+       i++)
+    { /* Handle the stores of the stack register that were done
+         between insn and store_insn.  */
+      store_insn 
+	= stack_reg_info[regno].non_dead_store[i];
+      SET_SRC (PATTERN (store_insn)) = stack_slot;
+      if (GET_CODE (stack_slot) == REG )
+        {
+          reg_n_refs[REGNO (stack_slot)]++;
+          PUT_MODE (SET_DEST (PATTERN (store_insn)), GET_MODE (stack_slot));
+        }
+      INSN_CODE (store_insn) = recog (PATTERN (store_insn), store_insn, 0);
+    }
+  stack_reg_info[regno].store_insn = NULL;
+  stack_reg_info[regno].last_use = NULL;
+  stack_reg_info[regno].num_non_dead_store = 0;
+  stack_reg_info[regno].dies_at_store = 0;
+}
+
+
+
+/*
+  GET_CODE(mem) is MEM
+  we are interested in the insns between start_insn and stop_insn
+  (non inclusive)
+  return 1 if the address of mem or the contents of mem may POSSIBLY
+  be changed in this interval
+  return 0 otherwise
+    by address of mem changing we mean that mem contains a base and/or
+    index register and some insn in the interval sets the register.
+*/
+static int
+addr_or_val_changed (mem, start_insn, stop_insn)
+     rtx mem, start_insn, stop_insn;
+{
+  rtx insn;
+  struct regs_mentioned *a_reg_mentioned;
+  char * storage;
+
+  if (MEM_VOLATILE_P (mem))
+    {
+      return (1);
+    }
+  /*
+  if (RTX_UNCHANGING_P (mem))
+    {
+      return (0);
+    } */
+  reg_mentioned_header = NULL;
+  storage = (char *) obstack_alloc (&momentary_obstack, 0);
+  find_regs_mentioned (mem);
+  for (insn = NEXT_INSN (start_insn); insn != stop_insn; insn = NEXT_INSN (insn))
+    {
+      if (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == CODE_LABEL)
+	{
+	  return (1);
+	}
+      if (GET_CODE (insn) == INSN)
+	{
+	  if (GET_CODE (PATTERN (insn)) == SET || GET_CODE (PATTERN (insn)) == CLOBBER)
+	    {
+	      if (GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
+		{
+		  if (true_dependence (mem, SET_DEST (PATTERN (insn))))
+		    {
+		      obstack_free (&momentary_obstack, storage);
+		      return (1);
+		    }
+		}
+	      else if (GET_CODE (SET_DEST (PATTERN (insn))) == REG)
+		{
+		  for (a_reg_mentioned = reg_mentioned_header;
+		       a_reg_mentioned != NULL;
+		       a_reg_mentioned = a_reg_mentioned->next)
+		    {
+		      if (reg_overlap_mentioned_p (SET_DEST (PATTERN (insn)),
+						   a_reg_mentioned->reg)
+			)
+			{
+  		          obstack_free (&momentary_obstack, storage);
+			  return (1);
+			}
+		    }
+		}
+	      else
+		{
+		  obstack_free (&momentary_obstack, storage);
+		  return (1);
+		}
+	    }
+	  else
+	    {
+	      obstack_free (&momentary_obstack, storage);
+	      return (1);
+	    }
+	}
+    }
+  obstack_free (&momentary_obstack, storage);
+  return (0);
+}
+
+
+/* Build a linked list of (struct regs_mentioned) describing the
+   registers used in the pattern pat.  
+*/
+static void
+find_regs_mentioned (pat)
+     rtx pat;
+{
+  register char *fmt;
+  register int i;
+  register enum rtx_code code;
+  struct regs_mentioned *one_reg;
+
+  code = GET_CODE (pat);
+
+  switch (code)
+    {
+    case REG:
+      one_reg = (struct regs_mentioned *)
+	obstack_alloc (&momentary_obstack, sizeof (struct regs_mentioned));
+      one_reg->reg = pat;
+      one_reg->next = reg_mentioned_header;
+      reg_mentioned_header = one_reg;
+      return;
+
+      /* These codes have no constituent expressions
+	 and are unique.  */
+    case SCRATCH:
+    case CC0:
+    case PC:
+    case QUEUED:
+    case CONST_INT:
+    case CONST_DOUBLE:
+    case SYMBOL_REF:
+    case CODE_LABEL:
+      return;
+
+
+    }
+
+
+  fmt = GET_RTX_FORMAT (code);
+
+  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+    {
+      if (fmt[i] == 'E')
+	{
+	  register int j;
+	  for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
+	    find_regs_mentioned (XVECEXP (pat, i, j));
+	}
+      else if (fmt[i] == 'e')
+	find_regs_mentioned (XEXP (pat, i));
+    }
+}
+
+
+/*
+  if insn stores a stack register into memory
+    set *regno to the register# stored
+    if the stack register is marked dead at the store
+      return 1
+    else
+      return 0
+*/
+static int
+stack_reg_dies_at_store (insn, regno)
+     rtx insn;
+     int *regno;
+{
+  if (GET_CODE (SET_DEST (PATTERN (insn))) == MEM
+      && GET_CODE (SET_SRC (PATTERN (insn))) == REG
+      && IS_STACK_MODE (GET_MODE (SET_SRC (PATTERN (insn))))
+    )
+    {
+      *regno = REGNO (SET_SRC (PATTERN (insn)));
+      return ((int) find_regno_note (insn, REG_DEAD, *regno));
+    }
+  return (0);
+}
+
+
+/*
+  Record relevant information on each stack register that is mentioned
+  in pat which is a subexpression of insn.  
+*/
+static void
+mark_stack_regs_mentioned (pat, insn)
+     rtx pat, insn;
+{
+  register char *fmt;
+  register int i;
+  register enum rtx_code code;
+
+  code = GET_CODE (pat);
+
+  switch (code)
+    {
+    case REG:
+      if (IS_STACK_MODE (GET_MODE (pat)))
+	{
+	  if (stack_reg_info[REGNO (pat)].last_use == NULL)
+	    {
+	      stack_reg_info[REGNO (pat)].last_use = insn;
+	    }
+	}
+      return;
+
+      /* These codes have no constituent expressions
+	 and are unique.  */
+    case SCRATCH:
+    case CC0:
+    case PC:
+    case QUEUED:
+    case CONST_INT:
+    case CONST_DOUBLE:
+    case SYMBOL_REF:
+    case CODE_LABEL:
+      return;
+
+
+    }
+
+
+  fmt = GET_RTX_FORMAT (code);
+
+  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+    {
+      if (fmt[i] == 'E')
+	{
+	  register int j;
+	  for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
+	    mark_stack_regs_mentioned (XVECEXP (pat, i, j), insn);
+	}
+      else if (fmt[i] == 'e')
+	mark_stack_regs_mentioned (XEXP (pat, i), insn);
+    }
+}
+
+
+/*
+   Stack mode registers that are set in one basic block and only
+   loaded to or stored from in successor blocks are replaced with
+   stack slots in the successor blocks. 
+*/
+static void
+func_stack_reg_to_stack_slot ()
+{
+  rtx head, tail, target;
+  register regset tem;
+  int i, j, found, target_blocknum, regno, successful_visit, reg_defined_elsewhere,
+    reg_set_or_stored, cmprd, only_cmp;
+  char *storage;
+#ifdef SPARE_REGS
+   int max_regno = max_reg_num ();
+#endif
+
+
+  storage = (char *) obstack_alloc (&momentary_obstack, 0);
+  basic_block_maybe_live_at_end = (regset *) alloca (n_basic_blocks * sizeof (regset));
+  tem = (regset) obstack_alloc (&momentary_obstack, n_basic_blocks * regset_bytes);
+  bzero (tem, n_basic_blocks * regset_bytes);
+  init_regset_vector (basic_block_maybe_live_at_end, tem, n_basic_blocks, regset_bytes);
+  jump_target_block = (int *) alloca (n_basic_blocks * sizeof (int));
+  fall_thru_block = (int *) alloca (n_basic_blocks * sizeof (int));
+  blocks_visited = (char *) alloca (n_basic_blocks * sizeof (char));
+  death_blocks = (rtx *) alloca (n_basic_blocks * sizeof (rtx));
+  blocks_defined = (char *) alloca (n_basic_blocks * sizeof (char));
+  cmprd = 0;
+  only_cmp = 1;
+
+  if (stack_reg_dump_file)
+    {
+      fprintf (stack_reg_dump_file,
+	       "Offload stack regs:\n\n");
+    }
+  /* Find block successors */
+  for (i = 0; i < n_basic_blocks; i++)
+    {
+      jump_target_block[i] = -1;
+      fall_thru_block[i] = -1;
+      head = basic_block_head[i];
+      tail = basic_block_end[i];
+      if (GET_CODE (tail) == JUMP_INSN)
+	{
+	  target = JUMP_LABEL (tail);
+	  if (target == NULL)
+	    {
+	      return;
+	    }
+	  /* target is the head of the basic block jumped to
+             find which block it is */
+	  target_blocknum = 0;
+	  found = 0;
+	  while (target_blocknum < n_basic_blocks && !found)
+	    {
+	      if (basic_block_head[target_blocknum] == target)
+		{
+		  found = 1;
+		}
+	      else
+		{
+		  target_blocknum++;
+		}
+	    }
+	  if (!found)
+	    {
+	      return;
+	    }
+	  jump_target_block[i] = target_blocknum;
+	  for (j = 0; j < regset_size; j++)
+	    basic_block_maybe_live_at_end[i][j]
+	      |= basic_block_live_at_start[target_blocknum][j];
+	}
+      if (!simplejump_p (tail))
+	{
+	  if (i < n_basic_blocks - 1)
+	    {
+	      fall_thru_block[i] = i + 1;
+	      for (j = 0; j < regset_size; j++)
+		basic_block_maybe_live_at_end[i][j]
+		  |= basic_block_live_at_start[i + 1][j];
+	    }
+	}
+    }
+  if (stack_reg_dump_file)
+    my_dump_block_info ();
+  /* Do inter block optimizations */
+  for (i = 0; i < n_basic_blocks; i++)
+    {
+      for (regno = FIRST_PSEUDO_REGISTER; regno < max_regno; regno++)
+	{
+	  register int offset = regno / REGSET_ELT_BITS;
+	  register int bit = 1 << (regno % REGSET_ELT_BITS);
+	  if (stack_reg_dump_file
+	      && IS_STACK_MODE (GET_MODE (regno_reg_rtx[regno]))
+	      && (basic_block_maybe_live_at_end[i][offset] & bit)
+	      && !(basic_block_live_at_start[i][offset] & bit)
+	    )
+	    {
+	      fprintf (stack_reg_dump_file,
+		       "\nstack reg%d in block %d  d_a_p %d\n",
+		       regno, i,
+		       reg_dead_at_pred (offset, bit, i));
+	    }
+	  if ((basic_block_maybe_live_at_end[i][offset] & bit)
+	      && reg_dead_at_pred (offset, bit, i)
+	      && !(basic_block_live_at_start[i][offset] & bit)
+	      && IS_STACK_MODE (GET_MODE (regno_reg_rtx[regno])))
+	    {
+	      /* A stack register that is live at the exit of the
+                 block and not live on entry */
+	      if (stack_reg_dump_file)
+		{
+		  fprintf (stack_reg_dump_file,
+		  "\nstack reg%d in block %d live at end but not at start\n",
+			   regno, i);
+		}
+	      bzero (blocks_visited, n_basic_blocks * sizeof (char));
+	      bzero (death_blocks, n_basic_blocks * sizeof (rtx));
+	      num_visits = 0;
+	      successful_visit = visit_till_dies (regno, i);
+	      if (stack_reg_dump_file)
+		{
+		  fprintf (stack_reg_dump_file, " blocks visited : ");
+		  for (j = 0; j < n_basic_blocks; j++)
+		    {
+		      if (blocks_visited[j])
+			{
+			  fprintf (stack_reg_dump_file, "%d ", j);
+			}
+		    }
+		  fprintf (stack_reg_dump_file, "\n");
+		}
+	      successful_visit = 
+	        successful_visit && death_blocks_ok (regno);
+	      bzero (blocks_defined, n_basic_blocks * sizeof (char));
+	      blocks_defined[i] = 1;
+	      reg_defined_elsewhere = reg_def_in_unvisited (offset, bit, i);
+	      reg_set_or_stored 
+		= reg_only_set_or_stored (regno, i, &cmprd, &only_cmp);
+	      if (successful_visit
+		  && !reg_defined_elsewhere
+		  && reg_set_or_stored)
+		{  /* This reg was never used in any computation after
+                      this set until it's death - so don't keep
+                      it in stack reg after block i.  Allocate a temp slot
+                      for it and store it there at the end of block i.  
+                      In all visited blocks replace regno with this
+                      temp slot.  */
+		  if (stack_reg_dump_file)
+		    {
+		      fprintf (stack_reg_dump_file,
+			  " only loaded or stored in all visited blocks\n");
+		    }
+		  if (store_into_temp (regno, i))
+		    {
+		      if (stack_reg_dump_file)
+			{
+			  fprintf (stack_reg_dump_file,
+			  " replaced by temp slot in all blocks visited\n");
+			}
+		      replace_with_temp_slot (regno, i);
+		    }
+		}
+	      else if (successful_visit && cmprd)
+		{
+		  /* In each block where regno is defined by a computation
+                     store it and reload it to avoid precision problems
+                     in comparison */
+		  offload_reg (regno);
+		}
+	      if (stack_reg_dump_file)
+		{
+		  fprintf (stack_reg_dump_file,
+			   "  successful visit %d  cmprd %d\n", successful_visit, cmprd);
+		}
+	    }
+	}
+    }
+  obstack_free (&momentary_obstack, storage);
+}
+
+
+/*
+  The blocks where the stack reg dies on the visit have been
+  marked by death_blocks[block_num] being set to the NEXT_INSN
+  of the insn where it dies in the block.  
+  For each of these blocks either the register must not be redefined
+  in the block or none of the successors of the block have been
+  visited.  
+*/
+
+static int
+death_blocks_ok (regno)
+     int regno;
+{
+  int i, successor_visited;
+
+  for (i = 0; i < n_basic_blocks; i++)
+    {
+      if (death_blocks[i])
+	{
+	  successor_visited = 0;
+	  if (fall_thru_block[i] != -1
+	      && blocks_visited[fall_thru_block[i]])
+	    {
+	      successor_visited = 1;
+	    }
+	  if (successor_visited == 0 && jump_target_block[i] != -1
+	      && blocks_visited[jump_target_block[i]])
+	    {
+	      successor_visited = 1;
+	    }
+	  if (successor_visited == 0)
+	    {
+	      continue;
+	    }
+	  else if (reg_set_between_p (regno_reg_rtx[regno],
+				      PREV_INSN (death_blocks[i]),
+				      NEXT_INSN (basic_block_end[i])))
+	    {
+	      return (0);
+	    }
+	}
+    }
+  return (1);
+}
+
+
+/*
+  Like offload_if_necessary but for stack registers used in equality
+  comparisons in one basic block and computed in another.  The offload
+  and reload are done at the place of computation.  
+*/
+static void
+offload_reg (regno)
+     int regno;
+{
+  int block, reg_loaded;
+  rtx last_set_insn, new_insn;
+
+  if (stack_reg_dump_file)
+    {
+      fprintf (stack_reg_dump_file,
+	       "offload compared reg %d\n", regno);
+    }
+  for (block = 0; block < n_basic_blocks; block++)
+    {
+      if (blocks_defined[block])
+	{
+	  if (stack_reg_dump_file)
+	    {
+	      fprintf (stack_reg_dump_file,
+		       " defined in block %d\n", block);
+	    }
+	  last_set_insn = NULL;
+	  reg_loaded 
+	    = reg_last_loaded (block, basic_block_end[block], regno, &last_set_insn);
+	  if (stack_reg_dump_file)
+	    {
+	      fprintf (stack_reg_dump_file,
+		       "  reg loaded %d ", reg_loaded);
+	      if (last_set_insn)
+		fprintf (stack_reg_dump_file,
+			 " last_set_insn %d", INSN_UID (last_set_insn));
+	      fprintf (stack_reg_dump_file, "\n");
+	    }
+	  if (reg_loaded == 0 && last_set_insn)
+	    {
+	      if (stack_reg_dump_file)
+		{
+		  fprintf (stack_reg_dump_file,
+			   "   actually offloading\n");
+		}
+	      if (reg_temp_slot[regno] == NULL)
+		{
+		  reg_temp_slot[regno] 
+		    = assign_stack_local (GET_MODE (regno_reg_rtx[regno]),
+			    GET_MODE_SIZE (GET_MODE (regno_reg_rtx[regno])),
+					-1);
+		}
+	      MEM_VOLATILE_P (reg_temp_slot[regno]) = 1;
+	      new_insn 
+		= emit_insn_before (
+				   gen_rtx (SET, 0,
+				reg_temp_slot[regno], regno_reg_rtx[regno]),
+				   NEXT_INSN (last_set_insn));
+	      REG_NOTES (new_insn) 
+	        = gen_rtx (EXPR_LIST, REG_DEAD,
+			 regno_reg_rtx[regno],
+			 REG_NOTES (new_insn));
+	      reg_n_deaths[regno]++;
+	      new_insn 
+		= emit_insn_before (
+				   gen_rtx (SET, 0,
+				regno_reg_rtx[regno], reg_temp_slot[regno]),
+				   NEXT_INSN (new_insn));
+	      if (basic_block_end[block] == last_set_insn)
+		{
+		  basic_block_end[block] = new_insn;
+		}
+	    }
+	}
+    }
+}
+
+/*
+  If the reg given by offset an bit in the live vecotrs is not live
+  at the end of any blocks that are the predecessors of blocknum
+  (except blocknum itself)
+    return 1
+  else
+    return 0
+*/
+static int
+reg_dead_at_pred (offset, bit, blocknum)
+     int offset, bit, blocknum;
+{
+  rtx head, jump;
+  int i;
+
+  head = basic_block_head[blocknum];
+
+  if (GET_CODE (head) == CODE_LABEL)
+    for (jump = LABEL_REFS (head);
+	 jump != head;
+	 jump = LABEL_NEXTREF (jump))
+      {
+	for (i = 0; i < n_basic_blocks; i++)
+	  {
+	    if (basic_block_end[i] == CONTAINING_INSN (jump))
+	      break;
+	  }
+	if (i == n_basic_blocks)
+	  {
+	    return (0);
+	  }
+	if (i != blocknum)
+	  {
+	    if (basic_block_maybe_live_at_end[i][offset] & bit)
+	      {
+		return (0);
+	      }
+	  }
+      }
+
+  if ((blocknum - 1) == -1 ||
+      simplejump_p (basic_block_end[blocknum - 1]) ||
+      !(basic_block_maybe_live_at_end[blocknum - 1][offset] & bit))
+    {
+      return (1);
+    }
+  return (0);
+
+}
+
+/*
+  If the definition of the register in some visited block is
+  done by a block that has not been visited then return 1
+*/
+static int
+reg_def_in_unvisited (offset, bit, blocknum)
+     int offset, bit, blocknum;
+{
+  int i, j, ret_val;
+  rtx head, jump;
+
+  ret_val = 0;
+
+  for (i = 0; i < n_basic_blocks; i++)
+    {
+      if (i != blocknum && blocks_visited[i])
+	{
+	  head = basic_block_head[i];
+
+	  if (GET_CODE (head) == CODE_LABEL)
+	    for (jump = LABEL_REFS (head);
+		 jump != head;
+		 jump = LABEL_NEXTREF (jump))
+	      {
+		for (j = 0; j < n_basic_blocks; j++)
+		  {
+		    if (basic_block_end[j] == CONTAINING_INSN (jump))
+		      break;
+		  }
+		if (j == n_basic_blocks)
+		  {
+		    ret_val = 1;
+		  }
+		if (blocks_visited[j] == 0 && j != i)
+		  {
+		    if (basic_block_maybe_live_at_end[j][offset] & bit)
+		      {
+			blocks_defined[j] = 1;
+			ret_val = 1;
+		      }
+		  }
+	      }
+
+	  if ((i - 1) != -1
+	      && !simplejump_p (basic_block_end[i - 1])
+	      && blocks_visited[i - 1] == 0
+	      && basic_block_maybe_live_at_end[i - 1][offset] & bit)
+	    {
+	      blocks_defined[i - 1] = 1;
+	      ret_val = 1;
+	    }
+	}
+    }
+  return (ret_val);
+}
+
+
+/* regno is never used in any computation from it's set in
+   source_blocknum until it's death - so don't keep
+   it in stack reg after source_blocknum.  Allocate a temp slot
+   for it and store it there at the end of block source_blocknum.
+   In all visited blocks replace regno with this temp slot. 
+   In blocks where regno dies the replacement is done
+   up until the insn in which regno dies.  
+*/
+static void
+replace_with_temp_slot (regno, source_blocknum)
+{
+  int i, had_call, num_insns;
+  rtx insn, note;
+  register int offset = regno / REGSET_ELT_BITS;
+  register int bit = 1 << (regno % REGSET_ELT_BITS);
+  register int compl_bit;
+
+  compl_bit = ~bit;
+  for (i = 0; i < n_basic_blocks; i++)
+    {
+      if (blocks_visited[i] && i != source_blocknum)
+	{
+	  basic_block_live_at_start[i][offset] &= compl_bit;
+	  if (!death_blocks[i])
+	    {
+	      basic_block_maybe_live_at_end[i][offset] &= compl_bit;
+	    }
+	  had_call = 0;
+	  num_insns = 0;
+	  for (insn = basic_block_head[i];
+	       insn && insn != death_blocks[i]
+	       && insn != NEXT_INSN (basic_block_end[i]);
+	       insn = NEXT_INSN (insn))
+	    {
+	      num_insns++;
+	      if (GET_CODE (insn) == CALL_INSN)
+	        had_call = 1;
+	      if (GET_CODE (insn) == INSN)
+		{
+		  init_undo_buf ();
+		  subst_in_insn (insn, PATTERN (insn), regno_reg_rtx[regno],
+				 reg_temp_slot[regno], 0, 0);
+		  if (GET_CODE (reg_temp_slot[regno]) == REG
+		      && GET_CODE (PATTERN (insn)) == SET)
+		    {
+	              register int n_offset = 
+	                REGNO (reg_temp_slot[regno]) / REGSET_ELT_BITS;
+	              register REGSET_ELT_TYPE n_bit
+	                = (REGSET_ELT_TYPE) 1 
+	                  << (REGNO (reg_temp_slot[regno]) % REGSET_ELT_BITS);
+	              basic_block_live_at_start[i][n_offset] |= n_bit;
+	              reg_basic_block[REGNO (reg_temp_slot[regno])] = REG_BLOCK_GLOBAL;
+		      if (rtx_equal_p (reg_temp_slot[regno], 
+		                       SET_DEST (PATTERN (insn))))
+		        {
+		          reg_n_sets[REGNO (reg_temp_slot[regno])]++;
+		          reg_n_refs[REGNO (reg_temp_slot[regno])]++;
+                          if (GET_CODE (SET_SRC (PATTERN (insn)))
+                              == CONST_DOUBLE)
+                            {
+                              union
+                                {
+                                  int i[2];
+                                  double d;
+                                }
+                              u1;
+                              union
+                                {
+                                  int i;
+                                  float f;
+                                }
+                              u2;
+                              u1.i[0] = 
+                                CONST_DOUBLE_LOW (SET_SRC (PATTERN (insn)));
+                              u1.i[1] = 
+                                CONST_DOUBLE_HIGH (SET_SRC (PATTERN (insn)));
+                              u2.f = u1.d;
+                              SET_SRC (PATTERN (insn)) = 
+                                gen_rtx (CONST_INT, 0, u2.i);
+                            }
+                          else
+                            {
+		              PUT_MODE (SET_SRC (PATTERN (insn)), 
+		                    GET_MODE (reg_temp_slot[regno]));
+
+		            }
+		        }
+		      if (rtx_equal_p (reg_temp_slot[regno], 
+		                       SET_SRC (PATTERN (insn))))
+		        {
+		          PUT_MODE (SET_DEST (PATTERN (insn)), 
+		                    GET_MODE (reg_temp_slot[regno]));
+		          reg_live_length[REGNO (reg_temp_slot[regno])] 
+		            += num_insns;
+		          reg_n_refs[REGNO (reg_temp_slot[regno])]++;
+		          if (had_call)
+		            {
+		              reg_n_calls_crossed[REGNO (reg_temp_slot[regno])]++;
+		            }
+		        }
+		    }
+		  INSN_CODE (insn) = recog (PATTERN (insn), insn, 0);
+		  if ((note = find_regno_note (insn, REG_DEAD, regno)) != NULL)
+		    {
+		      if (GET_CODE (reg_temp_slot[regno]) == REG)
+		        {
+		          XEXP (note, 0) = reg_temp_slot[regno];
+		          reg_n_deaths[REGNO (reg_temp_slot[regno])]++;
+		        }
+		      else
+		        remove_note (insn, note);
+		    }
+		}
+	    }
+	}
+    }
+}
+
+
+
+/*
+  If in each block_visited (except source_blocknum) regno is only
+  set, or used as a source in a store then
+    return 1
+  else
+    return 0
+  *used_in_cmp is set to 1 if regno is used in a comparison
+  in a block and it was not last set by a load before that
+  comparison
+  *only_cmp is set to 1 if the only other use of regno besides
+  as a dest or source of a store is in comparison, otherwise it
+  is set to 0
+*/
+static int
+reg_only_set_or_stored (regno, source_blocknum, used_in_cmp, only_cmp)
+     int regno, source_blocknum, *used_in_cmp, *only_cmp;
+{
+  int i, ret_val;
+  rtx insn, cmp_part, last_set_insn;
+
+  ret_val = 1;
+  for (i = 0; i < n_basic_blocks; i++)
+    {
+      if (blocks_visited[i] && i != source_blocknum)
+	{
+	  for (insn = basic_block_head[i];
+	       insn && insn != death_blocks[i]
+	       && insn != NEXT_INSN (basic_block_end[i]);
+	       insn = NEXT_INSN (insn))
+	    {
+	      if (GET_CODE (insn) == INSN)
+		{
+		  if (reg_used_in_body (regno, PATTERN (insn)))
+		    {
+		      ret_val = 0;
+		      if (stack_reg_dump_file)
+			{
+			  fprintf (stack_reg_dump_file,
+				   "  reg used in body of insn %d\n", INSN_UID (insn));
+			}
+		      if (GET_CODE (PATTERN (insn)) == PARALLEL
+			&& GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
+			{
+			  cmp_part = XVECEXP (PATTERN (insn), 0, 0);
+			  last_set_insn = NULL;
+			  if (SET_DEST (cmp_part) == cc0_rtx
+			      && GET_CODE (SET_SRC (cmp_part)) == COMPARE
+			      && (GET_MODE (SET_SRC (cmp_part)) == CCmode
+			          || GET_MODE (SET_SRC (cmp_part)) == CCFPEQmode
+			          || GET_MODE (SET_SRC (cmp_part)) == VOIDmode)
+			      && GET_CODE (XEXP (SET_SRC (cmp_part), 0)) == REG
+			      && REGNO (XEXP (SET_SRC (cmp_part), 0)) == regno
+			      && (GET_CODE (XEXP (SET_SRC (cmp_part), 1)) != REG
+			          || GET_MODE (SET_SRC (cmp_part)) == CCFPEQmode)
+			      && !reg_last_loaded (i, PREV_INSN (insn),
+				       REGNO (XEXP (SET_SRC (cmp_part), 0)),
+						   &last_set_insn)
+			      && !last_set_insn
+			      && tests_equality (NEXT_INSN (insn)))
+			    {
+			      *used_in_cmp = 1;
+			    }
+			  else
+			    {
+			      *only_cmp = 0;
+			    }
+			}
+		      else
+			{
+			  *only_cmp = 0;
+			}
+		    }
+		}
+	    }
+	}
+    }
+  return (ret_val);
+}
+
+/*
+  If regno is used in insn is anyway except as a dest or source of a set
+    return 1
+  else
+    return 0
+*/
+static int
+reg_used_in_body (regno, body)
+     int regno;
+     rtx body;
+{
+  int i, ret_val = 0;
+
+  if (GET_CODE (body) == SET)
+    {
+      if (GET_CODE (SET_DEST (body)) != REG)
+	{
+	  if (reg_overlap_mentioned_p (regno_reg_rtx[regno],
+				       SET_DEST (body)))
+	    {
+	      return (1);
+	    }
+	}
+      else if (REGNO (SET_DEST (body)) == regno)
+	{
+	  if (GET_CODE (SET_SRC (body)) != MEM
+	      && GET_CODE (SET_SRC (body)) != REG
+	      && GET_CODE (SET_SRC (body)) != CONST_DOUBLE)
+	    {
+	      return (1);
+	    }
+	}
+
+      if (GET_CODE (SET_SRC (body)) != REG)
+	{
+	  if (reg_overlap_mentioned_p (regno_reg_rtx[regno],
+				       SET_SRC (body)))
+	    {
+	      return (1);
+	    }
+	}
+      else if (REGNO (SET_SRC (body)) == regno)
+	{
+	  if (/*GET_CODE (SET_DEST (body)) != REG
+	      && */ GET_CODE (SET_DEST (body)) != MEM)
+	    {
+	      return (1);
+	    }
+	}
+      return (0);
+    }
+  else if (GET_CODE (body) == CLOBBER)
+    {
+      if (GET_CODE (SET_DEST (body)) == REG && REGNO (SET_DEST (body)) == regno)
+	{
+	  return (1);
+	}
+      return (0);
+    }
+  else if (GET_CODE (body) == PARALLEL)
+    {
+      for (i = 0; i < XVECLEN (body, 0); i++)
+	{
+	  ret_val |= reg_used_in_body (regno, XVECEXP (body, 0, i));
+	  if (ret_val)
+	    {
+	      return (1);
+	    }
+	}
+      return (ret_val);
+    }
+  else
+    {
+      return (1);
+    }
+}
+
+/*
+   If the stack reg regno has not already been allocated a temp slot then
+     allocate one for it. 
+   Store the last value of regno in block# source_blocknum into it's
+   temp_slot.  
+   Mark the last use of regno in the block as REG_DEAD
+*/
+static int
+store_into_temp (regno, source_blocknum)
+     int regno, source_blocknum;
+{
+  rtx last_set, last_use, stack_slot, store_rtx, store_insn, note;
+  int found, insn_code_num, i;
+  register int offset;
+  register int bit;
+  register int compl_bit;
+
+
+  /* Find where regno is last set in source_blocknum */
+  last_set = basic_block_end[source_blocknum];
+  found = 0;
+  while (!found && last_set != PREV_INSN (basic_block_head[source_blocknum]))
+    {
+      if (GET_CODE (last_set) == INSN)
+	{
+	  if (GET_CODE (PATTERN (last_set)) == PARALLEL)
+	    {
+	      for (i = 0; i < XVECLEN (PATTERN (last_set), 0); i++)
+		{
+		  if (GET_CODE (XVECEXP (PATTERN (last_set), 0, i)) == SET)
+		    {
+		      if (GET_CODE (SET_DEST (XVECEXP (PATTERN (last_set), 0, i))) == REG &&
+			  REGNO (SET_DEST (XVECEXP (PATTERN (last_set), 0, i))) == regno)
+			{
+			  return (0);
+			}
+		    }
+		  else if (GET_CODE (XVECEXP (PATTERN (last_set), 0, i)) == CLOBBER)
+		    {
+		      if (GET_CODE (SET_DEST (XVECEXP (PATTERN (last_set), 0, i))) == REG &&
+			  REGNO (SET_DEST (XVECEXP (PATTERN (last_set), 0, i))) == regno)
+			{
+			  return (0);
+			}
+		    }
+		  else
+		    {
+		      return (0);
+		    }
+		}
+	    }
+	  if ((GET_CODE (PATTERN (last_set)) == SET ||
+	       GET_CODE (PATTERN (last_set)) == CLOBBER) &&
+	      GET_CODE (SET_DEST (PATTERN (last_set))) == REG &&
+	      REGNO (SET_DEST (PATTERN (last_set))) == regno)
+	    {
+	      if (GET_CODE (PATTERN (last_set)) == CLOBBER)
+		return (0);
+	      if (GET_CODE (SET_SRC (PATTERN (last_set))) != MEM)
+		return (0);
+	      found = 1;
+	    }
+	}
+      if (!found)
+	{
+	  last_set = PREV_INSN (last_set);
+	}
+    }
+  if (!found)
+    {
+      return (0);
+    }
+
+
+  /* Allocate a temp slot and store the value that is loaded into
+     regno at last_set into that temp slot and place the insn to
+     do this right after the load to regno */
+  if (reg_temp_slot[regno] == NULL)
+    {
+#ifdef SPARE_REGS
+      if (max_reg_num () < max_regno)
+        {
+          if (GET_MODE (SET_DEST (PATTERN (last_set))) == SFmode)
+            {
+              reg_temp_slot[regno] = gen_reg_rtx (SImode);
+            }
+          else
+            reg_temp_slot[regno] 
+	      = assign_stack_local (GET_MODE (SET_DEST (PATTERN (last_set))),
+		   GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (last_set)))),
+			    -1);
+        }
+      else
+#endif
+        reg_temp_slot[regno] 
+	  = assign_stack_local (GET_MODE (SET_DEST (PATTERN (last_set))),
+		   GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (last_set)))),
+			    -1);
+    }
+  store_rtx = gen_rtx (SET, 0, reg_temp_slot[regno],
+		       copy_rtx (SET_SRC (PATTERN (last_set))));
+  if (GET_CODE (reg_temp_slot[regno]) == REG )
+    {
+      if (GET_CODE (SET_SRC (store_rtx)) == CONST_DOUBLE)
+        {
+          union
+            {
+              int i[2];
+              double d;
+            }
+          u1;
+          union
+            {
+              int i;
+              float f;
+            }
+          u2;
+          u1.i[0] = CONST_DOUBLE_LOW (SET_SRC (store_rtx));
+          u1.i[1] = CONST_DOUBLE_HIGH (SET_SRC (store_rtx));
+          u2.f = u1.d;
+          SET_SRC (store_rtx) = 
+            gen_rtx (CONST_INT, 0, u2.i);
+        }
+      else
+        {
+          PUT_MODE (SET_SRC (store_rtx), GET_MODE (reg_temp_slot[regno]));
+        }
+      reg_n_sets[REGNO (reg_temp_slot[regno])]++;
+      reg_n_refs[REGNO (reg_temp_slot[regno])]++;
+      reg_live_length[REGNO (reg_temp_slot[regno])] = 2;
+    }
+  insn_code_num = recog (store_rtx, last_set);
+  if (insn_code_num < 0)
+    {
+      return (0);
+    }
+  store_insn = emit_insn_after (store_rtx, PREV_INSN (last_set));
+  INSN_CODE (store_insn) = insn_code_num;
+
+  /* Find where regno is last use in source_blocknum */
+  last_use = basic_block_end[source_blocknum];
+  found = 0;
+  while (!found && last_use != PREV_INSN (basic_block_head[source_blocknum]))
+    {
+      if (GET_CODE (last_use) == INSN)
+	{
+	  if (reg_overlap_mentioned_p (regno_reg_rtx[regno], PATTERN (last_use)))
+	    {
+	      found = 1;
+	    }
+	}
+      if (!found)
+	{
+	  last_use = PREV_INSN (last_use);
+	}
+    }
+  offset = regno / REGSET_ELT_BITS;
+  bit = 1 << (regno % REGSET_ELT_BITS);
+  compl_bit = ~bit;
+  if (!found)
+    { /* regno was only loaded and never used - the load can be deleted */
+      delete_insn_for_stacker (last_set);
+      basic_block_maybe_live_at_end[source_blocknum][offset] &= compl_bit;
+      return (1);
+    }
+  /* Mark regno as dead at last_use */
+  note = gen_rtx (EXPR_LIST, REG_DEAD, regno_reg_rtx[regno],
+		  REG_NOTES (last_use));
+  XEXP (note, 1) = REG_NOTES (last_use);
+  REG_NOTES (last_use) = note;
+  basic_block_maybe_live_at_end[source_blocknum][offset] &= compl_bit;
+  return (1);
+}
+
+
+/*
+  Starting at block# block_num visit all successor blocks recursively
+  stopping at a block where regno is not live at exit or regno
+  is set in block
+*/
+static int
+visit_till_dies (regno, block_num)
+     int regno, block_num;
+{
+  register int offset = regno / REGSET_ELT_BITS;
+  register int bit = 1 << (regno % REGSET_ELT_BITS);
+  int ret_val = 1;
+  int already_visited;
+  rtx reg_death = NULL;
+
+  already_visited = blocks_visited[block_num];
+  blocks_visited[block_num] = 1;
+  if (num_visits > n_basic_blocks * 2)
+    { /* Failed to find where regno dies */
+      return (0);
+    }
+  if (already_visited)
+    {
+      num_visits++;
+      return (1);
+    }
+  num_visits++;
+  if ((basic_block_maybe_live_at_end[block_num][offset] & bit)
+      && !(reg_death = reg_dies_in_block (regno, block_num)))
+    {
+      if (jump_target_block[block_num] != -1)
+	{
+	  ret_val = visit_till_dies (regno, jump_target_block[block_num]);
+	}
+      if (ret_val && fall_thru_block[block_num] != -1)
+	{
+	  ret_val = visit_till_dies (regno, fall_thru_block[block_num]);
+	}
+      return (ret_val);
+    }
+  else
+    {
+      if (reg_death)
+	{
+	  death_blocks[block_num] = NEXT_INSN (reg_death);
+	}
+      return (1);
+    }
+}
+
+
+/* Return the insn where regno dies in the block if it does,
+   otherwise return NULL
+*/
+static rtx
+reg_dies_in_block (regno, block_num)
+     int regno, block_num;
+{
+  rtx insn;
+
+  for (insn = basic_block_head[block_num];
+       insn && insn != NEXT_INSN (basic_block_end[block_num]);
+       insn = NEXT_INSN (insn))
+    {
+      if (GET_CODE (insn) == INSN && find_regno_note (insn, REG_DEAD, regno))
+	{
+	  return (insn);
+	}
+    }
+  return (NULL);
+}
+
+my_dump_block_info ()
+{
+  int i;
+  int max_regno = max_reg_num();
+  for (i = 0; i < n_basic_blocks; i++)
+    {
+      register rtx head, jump;
+      register int regno;
+      fprintf (stack_reg_dump_file, "\nBasic block %d: first insn %d, last %d.\n",
+	       i,
+	       INSN_UID (basic_block_head[i]),
+	       INSN_UID (basic_block_end[i]));
+      /* The control flow graph's storage is freed
+	 now when flow_analysis returns.
+	 Don't try to print it if it is gone.  */
+      fprintf (stack_reg_dump_file, "Succesor blocks: %d %d\n",
+	       fall_thru_block[i], jump_target_block[i]);
+      fprintf (stack_reg_dump_file, "\nRegisters live at start:");
+      for (regno = 0; regno < max_regno; regno++)
+	{
+	  register int offset = regno / REGSET_ELT_BITS;
+	  register int bit = 1 << (regno % REGSET_ELT_BITS);
+	  if (basic_block_live_at_start[i][offset] & bit)
+	    {
+	      fprintf (stack_reg_dump_file, " %d", regno);
+	    }
+	}
+      fprintf (stack_reg_dump_file, "\n");
+      fprintf (stack_reg_dump_file, "Registers live at end:");
+      for (regno = 0; regno < max_regno; regno++)
+	{
+	  register int offset = regno / REGSET_ELT_BITS;
+	  register int bit = 1 << (regno % REGSET_ELT_BITS);
+	  if (basic_block_maybe_live_at_end[i][offset] & bit)
+	    {
+	      fprintf (stack_reg_dump_file, " %d", regno);
+	    }
+	}
+      fprintf (stack_reg_dump_file, "\n");
+    }
+  fprintf (stack_reg_dump_file, "\n");
+}
+
+#define   MINUS0  0x80000000
+
+/*
+  change floating point compares to integer compares
+*/
+
+void
+float_to_int_cmp (f, allow_new_jumps)
+     rtx f;
+{
+  union
+    {
+      int i[2];
+      double d;
+    }
+  u1;
+  union
+    {
+      int i;
+      float f;
+    }
+  u2;
+  int block, found, next_is_ok, rev_new_targets, const_is_zero, no_new_jump,
+      change_org_jump, new_org_cond, rev_org_targets, new_jump_cond,
+      make_new_lab, new_lab_true;
+  rtx insn, sf_reg, sf_dead_note, last_set, mem_loaded, int_cmp, cmp_part,
+      op1, next, org_jump_insn, double_const, tmp, new_jump,  new_jump_insn, 
+      new_label, new_label_insn, gen_cmpsi_1 ();
+
+  if (HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
+      || HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT)
+    {
+      return;
+    }
+  if (TARGET_IEEE_FP)
+    {
+      return;
+    }
+  insn = f;
+  for (insn; insn != NULL; insn = NEXT_INSN (insn))
+    {
+      if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == PARALLEL)
+	{
+	  if (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
+	    {
+	      cmp_part = XVECEXP (PATTERN (insn), 0, 0);
+	      if (SET_DEST (cmp_part) == cc0_rtx
+		  && GET_CODE (SET_SRC (cmp_part)) == COMPARE
+		  && (GET_MODE (SET_SRC (cmp_part)) == CCmode
+		      || GET_MODE (SET_SRC (cmp_part)) == VOIDmode)
+		  && ( 
+		      (GET_CODE (XEXP (SET_SRC (cmp_part), 0)) == FLOAT_EXTEND
+		       && GET_CODE (XEXP (XEXP (SET_SRC (cmp_part), 0), 0)) == REG
+		       && REGNO (XEXP (XEXP (SET_SRC (cmp_part), 0), 0)) == FIRST_FLOAT_REG
+	               && GET_MODE (XEXP (XEXP (SET_SRC (cmp_part), 0), 0)) == SFmode)
+	              || /* Will have to make sure later it was loaded 
+	                    from SFmode */
+		      (GET_CODE (XEXP (SET_SRC (cmp_part), 0)) == REG
+		       && REGNO (XEXP (SET_SRC (cmp_part), 0)) == FIRST_FLOAT_REG
+	               && GET_MODE (XEXP (SET_SRC (cmp_part), 0)) == DFmode)
+	             )
+		  && GET_CODE (XEXP (SET_SRC (cmp_part), 1)) == MEM)
+		{
+		  if (CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (SET_SRC (cmp_part), 1), 0)))
+		    {
+		      double_const
+			= get_pool_constant (XEXP (XEXP (SET_SRC (cmp_part), 1), 0));
+		      if (GET_CODE (double_const) == CONST_DOUBLE)
+			{
+			  u1.i[0] = CONST_DOUBLE_LOW (double_const);
+			  u1.i[1] = CONST_DOUBLE_HIGH (double_const);
+			  u2.f = u1.d;
+			  if (GET_CODE (XEXP (SET_SRC (cmp_part), 0)) == FLOAT_EXTEND)
+			    sf_reg = XEXP (XEXP (SET_SRC (cmp_part), 0), 0);
+			  else
+			    sf_reg = XEXP (SET_SRC (cmp_part), 0);
+			  sf_dead_note
+			    = find_regno_note (insn, REG_DEAD, REGNO (sf_reg));
+			}
+		      else
+			{
+			  double_const = NULL;
+			  sf_dead_note = NULL;
+			}
+		    }
+		  else
+		    {
+		      double_const = NULL;
+		      sf_dead_note = NULL;
+		    }
+
+		  next_is_ok = 1;
+		  no_new_jump = 0;
+		  const_is_zero = 0;
+		  if (u1.d == 0.0)
+		    {  /* 0.0 needs special handling because -0.0 has
+		          a different representation */
+		      const_is_zero = 1;
+		      next_is_ok = 0;
+		      rev_new_targets = 0;
+		      change_org_jump = 0;
+		      rev_org_targets = 0;
+		      new_jump_cond = EQ;
+		      make_new_lab = 0;
+		      new_lab_true = 0;
+		      next = NEXT_INSN (insn);
+		      if (allow_new_jumps
+		          && GET_CODE (next) == JUMP_INSN
+		          && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
+			{
+			  org_jump_insn = next;
+			  if (GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)) == LT
+			      && XEXP (SET_SRC (PATTERN (next)), 1) == pc_rtx
+			      && XEXP (XEXP (SET_SRC (PATTERN (next)), 0), 0) == cc0_rtx
+			      && XEXP (XEXP (SET_SRC (PATTERN (next)), 0), 1) == const0_rtx)
+			    {
+			      next_is_ok = 1;
+			      rev_new_targets = 1;
+			    }			  
+			  else if (GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)) == GT
+			      && XEXP (SET_SRC (PATTERN (next)), 1) == pc_rtx
+			      && XEXP (XEXP (SET_SRC (PATTERN (next)), 0), 0) == cc0_rtx
+			      && XEXP (XEXP (SET_SRC (PATTERN (next)), 0), 1) == const0_rtx)
+			    {
+			      next_is_ok = 1;
+			      rev_new_targets = 1;
+			      change_org_jump = 1;
+			      new_org_cond = LE;
+			      rev_org_targets = 1;
+			      no_new_jump = 1;
+			    } 
+			  else if (GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)) == EQ
+			      && XEXP (SET_SRC (PATTERN (next)), 1) == pc_rtx
+			      && XEXP (XEXP (SET_SRC (PATTERN (next)), 0), 0) == cc0_rtx
+			      && XEXP (XEXP (SET_SRC (PATTERN (next)), 0), 1) == const0_rtx)
+			    {
+			      next_is_ok = 1;
+			      new_jump_cond = NE;
+			      rev_new_targets = 1;
+			      /* The original jump will jump to the new
+			         label, that will be placed immediately
+			         after the new jump.  */
+			      make_new_lab = 1;
+			      /* The new label is to be jumped to
+			         if the condition is true */
+			      new_lab_true = 1;
+			    } 
+			  else if (GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)) == NE
+			      && XEXP (SET_SRC (PATTERN (next)), 1) != pc_rtx
+			      && XEXP (SET_SRC (PATTERN (next)), 2) == pc_rtx
+			      && XEXP (XEXP (SET_SRC (PATTERN (next)), 0), 0) == cc0_rtx
+			      && XEXP (XEXP (SET_SRC (PATTERN (next)), 0), 1) == const0_rtx)
+			    {
+			      next_is_ok = 1;
+			      change_org_jump = 1;
+			      new_org_cond = EQ;
+			      new_jump_cond = NE;
+			      /* The original jump will jump to the new
+			         label, that will be placed immediately
+			         after the new jump.  */
+			      make_new_lab = 1;
+			      /* The new label is to be jumped to
+			         if the condition is true */
+			      new_lab_true = 1;
+			    } 
+			  else if ((GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)) == GE
+			            && XEXP (SET_SRC (PATTERN (next)), 1) == pc_rtx
+			            && XEXP (XEXP (SET_SRC (PATTERN (next)), 0), 0) == cc0_rtx
+			            && XEXP (XEXP (SET_SRC (PATTERN (next)), 0), 1) == const0_rtx)
+			           ||
+			           (GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)) == LT
+			            && XEXP (SET_SRC (PATTERN (next)), 1) != pc_rtx
+			            && XEXP (SET_SRC (PATTERN (next)), 2) == pc_rtx
+			            && XEXP (XEXP (SET_SRC (PATTERN (next)), 0), 0) == cc0_rtx
+			            && XEXP (XEXP (SET_SRC (PATTERN (next)), 0), 1) == const0_rtx))
+			    {
+			      next_is_ok = 1;
+			      change_org_jump = 1;
+			      new_org_cond = GE;
+			      new_jump_cond = NE;
+			      rev_new_targets = 1;
+			      /* The original jump will jump to the new
+			         label, that will be placed immediately
+			         after the new jump.  */
+			      make_new_lab = 1;
+			      /* The new label is to be jumped to
+			         if the condition is true */
+			      new_lab_true = 1;
+			    } 
+			  else if (GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)) == GT
+			           && XEXP (SET_SRC (PATTERN (next)), 1) != pc_rtx
+			           && XEXP (SET_SRC (PATTERN (next)), 2) == pc_rtx
+			           && XEXP (XEXP (SET_SRC (PATTERN (next)), 0), 0) == cc0_rtx
+			           && XEXP (XEXP (SET_SRC (PATTERN (next)), 0), 1) == const0_rtx)
+			    {
+			      next_is_ok = 1;
+			      no_new_jump = 1;
+			    }
+			  else if ((GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)) == GE
+			            || GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)) == EQ)
+			           && XEXP (SET_SRC (PATTERN (next)), 1) != pc_rtx
+			           && XEXP (SET_SRC (PATTERN (next)), 2) == pc_rtx
+			           && XEXP (XEXP (SET_SRC (PATTERN (next)), 0), 0) == cc0_rtx
+			           && XEXP (XEXP (SET_SRC (PATTERN (next)), 0), 1) == const0_rtx)
+			    {
+			      next_is_ok = 1;
+			    }
+			  else if (GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)) == NE
+			           && XEXP (SET_SRC (PATTERN (next)), 1) == pc_rtx
+			           && XEXP (XEXP (SET_SRC (PATTERN (next)), 0), 0) == cc0_rtx
+			           && XEXP (XEXP (SET_SRC (PATTERN (next)), 0), 1) == const0_rtx)
+			    {
+			      next_is_ok = 1;
+			    }
+			  else if (GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)) == LE)
+			    {
+			      next_is_ok = 1;
+			      no_new_jump = 1;
+			    }
+			}
+		    }
+		  if (sf_dead_note
+		      && next_is_ok
+		      && u1.d >= 0.0
+		      && ((double) u2.f == u1.d)
+		      && ((float) u1.d == u2.f))
+		    { /* Find where the sf_reg was loaded from.  */
+		      last_set = PREV_INSN (insn);
+		      found = 0;
+		      while (!found && last_set)
+			{
+			  if (GET_CODE (last_set) == INSN)
+			    {
+			      if (GET_CODE (PATTERN (last_set)) == SET
+				  && rtx_equal_p (sf_reg,
+					      SET_DEST (PATTERN (last_set)))
+			          &&
+			          (GET_CODE (SET_SRC (PATTERN (last_set))) 
+			              == MEM ||
+			           (GET_CODE (SET_SRC (PATTERN (last_set))) 
+			             == FLOAT_EXTEND 
+			            &&
+			            GET_CODE (XEXP (SET_SRC (PATTERN (last_set)),0))
+			                      == MEM)
+				  ))
+				{
+				  if (GET_CODE (SET_SRC (PATTERN (last_set))) 
+			               == FLOAT_EXTEND)
+			            {
+			              mem_loaded = 
+			                XEXP (SET_SRC (PATTERN (last_set)),0);
+				      found = 1;
+			            }
+			          else if (GET_CODE (XEXP (SET_SRC (cmp_part), 0)) 
+			                   == FLOAT_EXTEND)
+			            {
+			              mem_loaded = 
+			                SET_SRC (PATTERN (last_set));
+				      found = 1;
+			            }
+			          else
+			            {
+			              last_set = NULL;
+			            }
+				}
+		 	      else if (GET_CODE (PATTERN (last_set)) == SET
+		 	               && GET_CODE (SET_DEST (PATTERN (last_set)))
+		 	                   == REG
+		 	               && !IS_STACK_MODE (
+		 	                    GET_MODE (SET_DEST (PATTERN (last_set)))))
+		 	        {
+		 	          last_set = PREV_INSN (last_set);
+		 	        }
+			      else
+				last_set = NULL;
+			    }
+			  else if (GET_CODE (last_set) == NOTE)
+			    {
+			      last_set = PREV_INSN (last_set);
+			    }
+			  else
+			    last_set = NULL;
+			}
+		      if (last_set)
+			{
+			  op1 = gen_rtx (MEM, SImode, XEXP (mem_loaded,0));
+			  /* See if op1 is also in a register.  */
+			  if (next_nonnote_insn (last_set) == insn)
+			    {
+			      tmp = prev_nonnote_insn (last_set);
+			    }
+			  else
+			    {
+			      tmp = next_nonnote_insn (last_set);
+			      if (next_nonnote_insn (tmp) != insn)
+			        {
+			          tmp = NULL;
+			        }
+			    }
+			  if (tmp
+			      && GET_CODE (tmp) == INSN
+			      && GET_CODE (PATTERN (tmp)) == SET
+			      && GET_CODE (SET_DEST (PATTERN (tmp))) == REG
+			      && rtx_equal_p (op1, 
+			                      SET_SRC (PATTERN (tmp))))
+			    {
+			      op1 = SET_DEST (PATTERN (tmp));
+			    }
+			  int_cmp
+				= gen_cmpsi_1 (op1,
+					      gen_rtx (CONST_INT, 0, u2.i));
+			  PATTERN (insn) = int_cmp;
+			  INSN_CODE (insn) = recog (int_cmp, insn);
+			  remove_note (insn, sf_dead_note);
+			  reg_n_deaths[REGNO (sf_reg)]--;
+			  PUT_CODE (last_set, NOTE);
+			  NOTE_LINE_NUMBER (last_set) = NOTE_INSN_DELETED;
+			  NOTE_SOURCE_FILE (last_set) = 0;
+			  if (const_is_zero && change_org_jump)
+			    {
+			      PUT_CODE (XEXP (SET_SRC (PATTERN (org_jump_insn)), 0), 
+			                new_org_cond);  
+			      INSN_CODE (org_jump_insn)
+				= recog (PATTERN (org_jump_insn), org_jump_insn);
+			    }
+			  if (const_is_zero && rev_org_targets)
+			    {
+
+			      tmp = XEXP (SET_SRC (PATTERN (org_jump_insn)), 1);
+			      XEXP (SET_SRC (PATTERN (org_jump_insn)), 1)
+				    = XEXP (SET_SRC (PATTERN (org_jump_insn)), 2);
+			      XEXP (SET_SRC (PATTERN (org_jump_insn)), 2) = tmp;
+			      INSN_CODE (org_jump_insn)
+				= recog (PATTERN (org_jump_insn), org_jump_insn);
+			    }
+			  if (const_is_zero && !no_new_jump)
+			    {
+			      new_jump = copy_rtx (PATTERN (next));
+			      PUT_CODE (XEXP (SET_SRC (new_jump), 0), new_jump_cond);
+			      if (rev_new_targets)
+				{
+				  tmp = XEXP (SET_SRC (new_jump), 1);
+				  XEXP (SET_SRC (new_jump), 1)
+				    = XEXP (SET_SRC (new_jump), 2);
+				  XEXP (SET_SRC (new_jump), 2) = tmp;
+				}
+			      int_cmp
+				= gen_cmpsi_1 (op1,
+					    gen_rtx (CONST_INT, 0, MINUS0));
+			      int_cmp
+				= emit_insn_before (int_cmp, NEXT_INSN (next));
+			      INSN_CODE (int_cmp) = INSN_CODE (insn);
+			      new_jump_insn
+				= emit_jump_insn_after (new_jump, int_cmp);
+			      INSN_CODE (new_jump_insn)
+				= recog (new_jump, new_jump_insn);
+			    }
+			  if (const_is_zero && make_new_lab)
+			    {
+			      if (no_new_jump)
+			        abort ();
+                              new_label = gen_label_rtx ();
+                              new_label_insn 
+                                = emit_label_after (new_label, new_jump_insn);
+                              ++LABEL_NUSES (new_label_insn);
+                              JUMP_LABEL (org_jump_insn) = new_label_insn;
+                              if (new_lab_true)
+                                {
+			          XEXP (SET_SRC (PATTERN (org_jump_insn)), 1)
+			            = gen_rtx (LABEL_REF, VOIDmode, new_label);
+			          XEXP (SET_SRC (PATTERN (org_jump_insn)), 2)
+			            = pc_rtx;
+                                }
+                              else
+                                {
+			          XEXP (SET_SRC (PATTERN (org_jump_insn)), 1)
+			            = pc_rtx;
+			          XEXP (SET_SRC (PATTERN (org_jump_insn)), 2)
+			            = gen_rtx (LABEL_REF, VOIDmode, new_label);
+                                }
+			      INSN_CODE (org_jump_insn)
+				 = recog (PATTERN (org_jump_insn), org_jump_insn);
+			    }
+			}
+		    }
+		}
+	    }
+	}
+    }
+}
+
+#endif
 #endif /* STACK_REGS */
diff -r -u -H -N gcc-2.6.3/reload.c gcc-i2.6.3/reload.c
--- gcc-2.6.3/reload.c	Thu Oct 27 13:04:09 1994
+++ gcc-i2.6.3/reload.c	Wed Feb 15 22:47:18 1995
@@ -4024,6 +4024,10 @@
 {
   register int regno;
   rtx tem;
+#ifdef REWRITE_ADDRESS
+  /* intel1 */
+  rtx rewrite_address();
+#endif
 
   /* If the address is a register, see if it is a legitimate address and
      reload if not.  We first handle the cases where we need not reload
@@ -4289,6 +4293,37 @@
 	}
     }
 
+  /* intel1 - even if one of the registers is still a pseudo
+             subst_reg_equivs may be able to substitute a
+             constant for it too */
+    else
+             
+    if (tem != ad && memory_address_p (mode, tem))
+      {
+        rtx tmp_rtx;
+        tmp_rtx = copy_rtx (tem);
+	/* Ok, we win that way.  Replace any additional eliminable
+	   registers.  */
+	subst_reg_equivs_changed = 0;
+	tmp_rtx = subst_reg_equivs (tmp_rtx);
+#ifdef REWRITE_ADDRESS
+	if (!strict_memory_address_p (mode, tmp_rtx))
+	  {
+            tmp_rtx = gen_rtx (MEM, mode, tmp_rtx);
+            REWRITE_ADDRESS (tmp_rtx);
+            tmp_rtx = XEXP (tmp_rtx, 0);
+	  }
+#endif
+
+	/* Make sure that didn't make the address invalid again.  */
+
+	if (strict_memory_address_p (mode, tmp_rtx))
+	  {
+	    *loc = tmp_rtx;
+	    return 0;
+	  }
+	
+      }
   /* If constants aren't valid addresses, reload the constant address
      into a register.  */
   if (CONSTANT_P (ad) && ! strict_memory_address_p (mode, ad))
diff -r -u -H -N gcc-2.6.3/reload.h gcc-i2.6.3/reload.h
--- gcc-2.6.3/reload.h	Mon Oct 17 11:28:49 1994
+++ gcc-i2.6.3/reload.h	Wed Feb 15 22:47:19 1995
@@ -234,3 +234,15 @@
 
 /* Find the places where hard regs are live across calls and save them.  */
 extern void save_call_clobbered_regs PROTO((enum machine_mode));
+/* intel1 */
+#define MAX_RELOAD_STACK_SLOTS 100
+struct reload_slot_info {
+    rtx  reload_stack_slot;
+    rtx  reload_insn;
+    rtx last_store;
+    int is_loaded_to_reg;
+    int stack_slot_pseudo_reg;
+    int cur_stack_offset;
+    char reload_stack_mode;
+    unsigned reload_slot_updated:1;
+    } ;
diff -r -u -H -N gcc-2.6.3/reload1.c gcc-i2.6.3/reload1.c
--- gcc-2.6.3/reload1.c	Sat Nov  5 13:57:29 1994
+++ gcc-i2.6.3/reload1.c	Thu Feb 16 12:19:37 1995
@@ -75,6 +75,8 @@
 #ifndef MEMORY_MOVE_COST
 #define MEMORY_MOVE_COST(x) 4
 #endif
+/* intel1 */
+static int cur_stack_offset;
 
 /* During reload_as_needed, element N contains a REG rtx for the hard reg
    into which reg N has been reloaded (perhaps for a previous insn). */
@@ -261,6 +263,9 @@
 #define obstack_chunk_alloc xmalloc
 #define obstack_chunk_free free
 
+/* intel1 */
+extern FILE * global_reg_dump_file;
+
 /* List of labels that must never be deleted.  */
 extern rtx forced_labels;
 
@@ -301,6 +306,15 @@
 
 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
 
+/* intel1 */
+/* information for loop_after_global optimizations */
+struct reload_slot_info reload_slots[MAX_RELOAD_STACK_SLOTS];
+int num_reload_stack_slots=0;
+static rtx treplace_insn = NULL_RTX;
+
+/* is 1 is the pseudo has been spilled */
+int * pseudo_spilled;
+
 /* Record the number of pending eliminations that have an offset not equal
    to their initial offset.  If non-zero, we use a new copy of each
    replacement result in any insns encountered.  */
@@ -365,6 +379,8 @@
 static void inc_for_reload		PROTO((rtx, rtx, int));
 static int constraint_accepts_reg_p	PROTO((char *, rtx));
 static int count_occurrences		PROTO((rtx, rtx));
+/* intel1 */
+int is_a_param_slot();
 
 /* Initialize the reload pass once per compilation.  */
 
@@ -459,6 +475,26 @@
   /* The basic block number currently being processed for INSN.  */
   int this_block;
 
+  /* intel1 */
+  /* intel1. Look for insns whose src is equal to dest and delete them.  */
+  for (insn = next_nonnote_insn (first); insn; insn = next_nonnote_insn (insn))
+    {
+      if (GET_CODE (insn) == INSN 
+          && GET_CODE (PATTERN (insn)) == SET
+          && !(GET_CODE (SET_SRC (PATTERN (insn))) == MEM
+               && MEM_VOLATILE_P (SET_SRC (PATTERN (insn))))
+          && rtx_equal_p (SET_SRC (PATTERN (insn)), SET_DEST (PATTERN (insn))))
+        {
+	  PUT_CODE (insn, NOTE);
+	  NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
+	  NOTE_SOURCE_FILE (insn) = 0;
+        }
+    }
+  num_reload_stack_slots = 0;
+  pseudo_spilled = (int *)alloca(max_regno*sizeof(int));
+  bzero(pseudo_spilled,max_regno*sizeof(int));
+  bzero(reload_slots,MAX_RELOADS*sizeof(struct reload_slot_info));
+
   /* Make sure even insns with volatile mem refs are recognizable.  */
   init_recog ();
 
@@ -804,6 +840,9 @@
 
       num_not_at_initial_offset = 0;
 
+	  /* intel1 */
+	  cur_stack_offset = 0;
+
       bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
 
       /* Set a known offset for each forced label to be at the initial offset
@@ -1937,6 +1976,42 @@
 
   reload_in_progress = 0;
 
+  /* intel1 */
+  for (insn = first; insn; insn = NEXT_INSN (insn))
+    {
+      if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
+          && GET_CODE (SET_DEST (PATTERN (insn))) == REG
+          && GET_CODE (SET_SRC (PATTERN (insn))) == REG)
+        {
+          if (REGNO (SET_DEST (PATTERN (insn))) < FIRST_PSEUDO_REGISTER
+              && REGNO (SET_SRC (PATTERN (insn))) >= FIRST_PSEUDO_REGISTER
+              && reg_equiv_mem[REGNO (SET_SRC (PATTERN (insn)))]
+              && reg_renumber[REGNO (SET_SRC (PATTERN (insn)))] < 0
+              && RTX_IS_SPILL_P (reg_equiv_mem[REGNO (SET_SRC (PATTERN (insn)))])
+              && !RTX_IS_SPILL_P (insn))
+            {
+              RTX_IS_SPILL_P (insn) = 1;
+              SPILL_PSEUDO (insn) = REGNO (SET_SRC (PATTERN (insn)));
+            }
+          if (REGNO (SET_DEST (PATTERN (insn))) >= FIRST_PSEUDO_REGISTER
+              && REGNO (SET_SRC (PATTERN (insn))) < FIRST_PSEUDO_REGISTER
+              && reg_equiv_mem[REGNO (SET_DEST (PATTERN (insn)))]
+              && reg_renumber[REGNO (SET_DEST (PATTERN (insn)))] < 0
+              && RTX_IS_SPILL_P (reg_equiv_mem[REGNO (SET_DEST (PATTERN (insn)))])
+              && !RTX_IS_SPILL_P (insn))
+            {
+              RTX_IS_SPILL_P (insn) = 1;
+              SPILL_PSEUDO (insn) = REGNO (SET_DEST (PATTERN (insn)));
+            }
+  if (scratch_list)
+    free (scratch_list);
+  scratch_list = 0;
+  if (scratch_block)
+    free (scratch_block);
+  scratch_block = 0;
+
+        }
+    }
   /* Now eliminate all pseudo regs by modifying them into
      their equivalent memory references.
      The REG-rtx's for the pseudos are modified in place,
@@ -1998,13 +2073,17 @@
   reg_equiv_constant = 0;
   reg_equiv_memory_loc = 0;
 
-  if (scratch_list)
-    free (scratch_list);
-  scratch_list = 0;
-  if (scratch_block)
-    free (scratch_block);
-  scratch_block = 0;
-
+  /* intel1 */
+  if (num_reload_stack_slots == MAX_RELOAD_STACK_SLOTS)
+    { /* Too many so don't use any */
+      for (insn = first; insn ; insn = next_nonnote_insn (insn))
+        {
+          if (GET_CODE (insn) == INSN )
+            {
+              RTX_IS_SPILL_P (insn) = 0;
+            }
+        }
+    }
   return failure;
 }
 
@@ -2303,6 +2382,15 @@
   REGNO (regno_reg_rtx[i])
     = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
 
+  /* intel1 */
+  if (reg_renumber[i] < 0 
+      && reg_equiv_memory_loc[i] != 0
+      && is_a_param_slot (reg_equiv_memory_loc[i]))
+    {
+      pseudo_spilled[i] = 1;
+      RTX_IS_SPILL_P (reg_equiv_memory_loc[i]) = 1;
+      RTX_IS_SPILL_P (XEXP (reg_equiv_memory_loc[i], 0)) = 1;
+    }
   /* If we have a pseudo that is needed but has no hard reg or equivalent,
      allocate a stack slot for it.  */
 
@@ -2316,6 +2404,8 @@
       int total_size = MAX (inherent_size, reg_max_ref_width[i]);
       int adjust = 0;
 
+      /* intel1 */
+      pseudo_spilled[i] = 1;
       /* Each pseudo reg has an inherent size which comes from its own mode,
 	 and a total size which provides room for paradoxical subregs
 	 which refer to the pseudo reg in wider modes.
@@ -2328,6 +2418,9 @@
 	{
 	  /* No known place to spill from => no slot to reuse.  */
 	  x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, -1);
+	  /* intel1 */
+	  RTX_IS_SPILL_P (x) = 1;
+	  RTX_IS_SPILL_P (XEXP (x, 0)) = 1;
 #if BYTES_BIG_ENDIAN
 	  /* Cancel the  big-endian correction done in assign_stack_local.
 	     Get the address of the beginning of the slot.
@@ -2341,7 +2434,9 @@
 	       && spill_stack_slot_width[from_reg] >= total_size
 	       && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
 		   >= inherent_size))
+        {
 	x = spill_stack_slot[from_reg];
+ 	}
       /* Allocate a bigger slot.  */
       else
 	{
@@ -2358,6 +2453,9 @@
 	    }
 	  /* Make a slot with that size.  */
 	  x = assign_stack_local (mode, total_size, -1);
+	  /* intel1 */
+	  RTX_IS_SPILL_P (x) = 1;
+	  RTX_IS_SPILL_P (XEXP (x, 0)) = 1;
 #if BYTES_BIG_ENDIAN
 	  /* Cancel the  big-endian correction done in assign_stack_local.
 	     Get the address of the beginning of the slot.
@@ -2383,6 +2481,9 @@
 	  x = gen_rtx (MEM, GET_MODE (regno_reg_rtx[i]),
 		       plus_constant (XEXP (x, 0), adjust));
 	  RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
+	  /* intel1 */
+	  RTX_IS_SPILL_P (x) = 1;
+	  RTX_IS_SPILL_P (XEXP (x, 0)) = 1;
 	}
 
       /* Save the stack slot for later.   */
@@ -2621,6 +2722,8 @@
   int i, j;
   char *fmt;
   int copied = 0;
+  /* intel1 */
+  int indx;
 
   switch (code)
     {
@@ -2670,6 +2773,24 @@
 	     address in case it is shared.  */
 	  new = eliminate_regs (reg_equiv_memory_loc[regno],
 				mem_mode, insn);
+	  /* intel1 */
+	  if ((flag_loop_after_global || flag_peep_spills)
+	      && treplace_insn && is_a_stack_slot (new) 
+	      && !is_a_reload_stack_slot (new, &indx, cur_stack_offset, treplace_insn)
+	      && num_reload_stack_slots < MAX_RELOAD_STACK_SLOTS)
+	    {
+              if (num_reload_stack_slots < MAX_RELOAD_STACK_SLOTS)
+                {
+	          reload_slots[num_reload_stack_slots].cur_stack_offset 
+	            = cur_stack_offset;
+	          reload_slots[num_reload_stack_slots].stack_slot_pseudo_reg 
+		    = regno;
+	          reload_slots[num_reload_stack_slots].reload_stack_slot 
+		    = new;
+	          reload_slots[num_reload_stack_slots++].reload_insn
+		    = treplace_insn;
+		}
+	    }
 	  if (new != reg_equiv_memory_loc[regno])
 	    {
 	      cannot_omit_stores[regno] = 1;
@@ -3066,10 +3187,14 @@
       new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
       if (new != XEXP (x, 0))
 	{
+	  /* intel1 */
+	  new->is_spill_rtx = x->is_spill_rtx;
 	  new = gen_rtx (MEM, GET_MODE (x), new);
 	  new->volatil = x->volatil;
 	  new->unchanging = x->unchanging;
 	  new->in_struct = x->in_struct;
+	  /* intel1 */
+	  new->is_spill_rtx = x->is_spill_rtx;
 	  return new;
 	}
       else
@@ -3260,8 +3385,12 @@
      re-recognize the insn.  We do this in case we had a simple addition
      but now can do this as a load-address.  This saves an insn in this
      common case. */
+  /* intel1 */
+  treplace_insn = replace ? insn : NULL_RTX;
 
   new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
+  /* intel1 */
+  treplace_insn = NULL_RTX;
   if (new_body != old_body)
     {
       /* If we aren't replacing things permanently and we changed something,
@@ -3777,7 +3906,6 @@
       else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
 	{
 	  rtx avoid_return_reg = 0;
-
 #ifdef SMALL_REGISTER_CLASSES
 	  /* Set avoid_return_reg if this is an insn
 	     that might use the value of a function call.  */
@@ -3932,6 +4060,16 @@
 		  forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
 	      }
 #endif
+          /* intel1 */
+	  if (GET_CODE (PATTERN (insn)) == PARALLEL)
+	    {
+	      int i;
+	      for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
+		update_stack_offset (XVECEXP (PATTERN (insn), 0, i), 
+		                     &cur_stack_offset);
+	    }
+	  else
+	    update_stack_offset (PATTERN (insn), &cur_stack_offset);
 	}
       /* A reload reg's contents are unknown after a label.  */
       if (GET_CODE (insn) == CODE_LABEL)
@@ -5631,6 +5769,8 @@
   int special;
   /* Values to be put in spill_reg_store are put here first.  */
   rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
+  int indx; /* intel1 */
+  rtx tmp_stack_slot, reload_insn; /* intel1 */
 
   for (j = 0; j < reload_n_operands; j++)
     input_reload_insns[j] = input_address_reload_insns[j]
@@ -6029,9 +6169,41 @@
 					   third_reload_reg)));
 			    }
 			  else
+              /* intel1 */
+              reload_insn =
 			    gen_reload (second_reload_reg, oldequiv,
 					reload_opnum[j],
-					reload_when_needed[j]);
+			reload_when_needed[j]);
+             /* intel1 */
+             if ((flag_loop_after_global ||flag_peep_spills) 
+               &&is_a_reload_stack_slot(oldequiv,&indx,cur_stack_offset,NULL))
+              {
+                 RTX_IS_SPILL_P (reload_insn) = 1;
+                 if (indx == -1)
+                 {
+                    tmp_stack_slot
+                     = eliminate_regs (
+                     reg_equiv_memory_loc[REGNO (oldequiv)],
+                     GET_MODE (oldequiv), NULL_RTX);
+
+                     if (num_reload_stack_slots < MAX_RELOAD_ STACK_SLOTS
+                     && !is_a_reload_stack_slot (tmp_stack_slot, &indx, cur_stack_offset, NULL))
+                     {
+                        reload_slots[num_reload_stack_slots].cur_stack_offset
+                           = cur_stack_offset;
+                      reload_slots[num_reload_stack_slots].stack_slot_pseudo_reg
+                           = REGNO (oldequiv);
+                          reload_slots[num_reload_stack_slots].reload_stack_slot
+                           = tmp_stack_slot;
+                           reload_slots[num_reload_stack_slots++].reload_insn
+                           = NULL;
+                      }
+                         SPILL_PSEUDO (reload_insn) = REGNO (oldequiv);
+                    }
+                     else
+                        SPILL_PSEUDO (reload_insn)
+                         = reload_slots[indx].stack_slot_pseudo_reg;
+                  }
 
 			  oldequiv = second_reload_reg;
 			}
@@ -6040,8 +6212,38 @@
 #endif
 
 	      if (! special && ! rtx_equal_p (reloadreg, oldequiv))
-		gen_reload (reloadreg, oldequiv, reload_opnum[j],
+		  /* intel1 */
+		reload_insn = gen_reload (reloadreg, oldequiv, reload_opnum[j],
 			    reload_when_needed[j]);
+      /* intel1 */ if ((flag_loop_after_global || flag_peep_spills)
+           && is_a_reload_stack_slot (oldequiv, &indx, cur_stack_offset, NULL))
+          {
+           RTX_IS_SPILL_P (reload_insn) = 1;
+           if (indx == -1)
+             {
+               tmp_stack_slot
+                 = eliminate_regs (
+                 reg_equiv_memory_loc[REGNO (oldequiv)],
+                 GET_MODE (oldequiv), NULL_RTX);
+
+                  if (num_reload_stack_slots < MAX_RELOAD_STACK_SLOTS
+                     && !is_a_reload_stack_slot (tmp_stack_slot, &indx, cur_stack_offset, NULL))
+                  {
+                     reload_slots[num_reload_stack_slots].cur_stack_offset
+                      = cur_stack_offset;
+                     reload_slots[num_reload_stack_slots].stack_slot_pseudo_reg
+                      = REGNO (oldequiv);
+                       reload_slots[num_reload_stack_slots].reload_stack_slot 
+                      = tmp_stack_slot;
+                        reload_slots[num_reload_stack_slots++].reload_insn
+                      = NULL;
+                  }
+                    SPILL_PSEUDO (reload_insn) = REGNO (oldequiv);
+              }
+            else
+              SPILL_PSEUDO (reload_insn)
+                = reload_slots[indx].stack_slot_pseudo_reg;
+          }
 
 #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P)
 	      /* We may have to make a REG_DEAD note for the secondary reload
@@ -6342,6 +6544,8 @@
 		}
 	    }
 #endif
+	/* PROBLEM: supposed to be intel code here, but too much has
+	  changed above, I don't know how it maps */
 
 	  /* Output the last reload insn.  */
 	  if (! special)
@@ -6624,6 +6828,8 @@
      enum reload_type type;
 {
   rtx last = get_last_insn ();
+  /* intel1 */
+  int indx;
 
   /* How to do this reload can get quite tricky.  Normally, we are being
      asked to reload a simple operand, such as a MEM, a constant, or a pseudo
@@ -6776,7 +6982,24 @@
 
   /* If IN is a simple operand, use gen_move_insn.  */
   else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
+  {
     emit_insn (gen_move_insn (out, in));
+    if ((flag_loop_after_global || flag_peep_spills)   /* intel1 */
+      && is_a_reload_stack_slot (in, &indx, cur_stack_offset, get_last_insn()))
+      {
+        rtx reload_insn = get_last_insn ();
+
+  RTX_IS_SPILL_P ( reload_insn) = 1;
+  if (indx == -1)
+     {
+           SPILL_PSEUDO (reload_insn) = REGNO (in);
+     }
+  else
+     SPILL_PSEUDO (reload_insn)
+        = reload_slots[indx].stack_slot_pseudo_reg;
+      }
+  }
+
 
 #ifdef HAVE_reload_load_address
   else if (HAVE_reload_load_address)
@@ -7091,4 +7314,255 @@
 	}
     }
   return count;
+}
+
+/* intel1 */
+
+/* return 1 if rx is a stack slot */
+int
+is_a_stack_slot (rx)
+  rtx rx;
+{
+ if (GET_CODE (rx) != MEM)
+    {
+      return (0);
+    }
+  if (GET_CODE (XEXP (rx, 0)) == PLUS 
+      && XEXP ( XEXP (rx, 0), 0) == stack_pointer_rtx 
+      && !frame_pointer_needed)
+    {
+      if ( GET_CODE (XEXP ( XEXP (rx, 0), 1)) == CONST_INT)
+        {
+          return (1);
+        }
+      else
+        {
+          return (0);
+        }
+    }
+  else if (GET_CODE (XEXP (rx, 0)) == PLUS 
+      && XEXP ( XEXP (rx, 0), 0) == frame_pointer_rtx
+      && frame_pointer_needed)
+    {
+      if ( GET_CODE (XEXP ( XEXP (rx, 0), 1)) == CONST_INT)
+        {
+          return (1);
+        }
+      else
+        {
+          return (0);
+        }
+    }
+  else if ((XEXP (rx, 0) == frame_pointer_rtx  && frame_pointer_needed)
+           || (XEXP (rx, 0) == stack_pointer_rtx && ! frame_pointer_needed))
+    {
+      return (1);
+    }
+  else
+    {
+      return (0);
+    }
+   
+}
+
+/*
+  if rx is a reload slot then set *indx to the index in the
+    reload_slots array which contains it and return 1
+  else
+    return 0
+*/
+
+int
+is_a_reload_stack_slot (rx, indx, cur_stack_offset, reload_insn)
+     rtx rx;
+     int *indx;
+     int cur_stack_offset;
+     rtx reload_insn;
+{
+  int i, is_based_on_stack_pointer, stack_offset, stack_i_offset;
+  rtx stack_slot_i;
+
+  
+  if (GET_CODE (rx) == REG && REGNO (rx) >= FIRST_PSEUDO_REGISTER
+      && pseudo_spilled[REGNO (rx)])
+    {
+      *indx = -1;
+      return (1);
+    }
+  if (GET_CODE (rx) == SUBREG 
+      && GET_CODE (SUBREG_REG (rx)) == MEM)
+    {
+      return (is_a_reload_stack_slot (SUBREG_REG (rx), indx, 
+                                      cur_stack_offset, reload_insn));
+    }
+  if (GET_CODE (rx) != MEM)
+    {
+      return (0);
+    }
+  is_based_on_stack_pointer = 0;
+  if (GET_CODE (XEXP (rx, 0)) == PLUS 
+      && XEXP ( XEXP (rx, 0), 0) == stack_pointer_rtx 
+      && !frame_pointer_needed)
+    {
+      is_based_on_stack_pointer = 1;
+      if ( GET_CODE (XEXP ( XEXP (rx, 0), 1)) == CONST_INT)
+        {
+          stack_offset = XINT (XEXP ( XEXP (rx, 0), 1), 0);
+        }
+      else
+        {
+          return (0);
+        }
+    }
+  else if (GET_CODE (XEXP (rx, 0)) == PLUS 
+      && XEXP ( XEXP (rx, 0), 0) == frame_pointer_rtx
+      && frame_pointer_needed)
+    {
+      if ( GET_CODE (XEXP ( XEXP (rx, 0), 1)) == CONST_INT)
+        {
+          ;
+        }
+      else
+        {
+          return (0);
+        }
+    }
+  else if ((XEXP (rx, 0) == frame_pointer_rtx  && frame_pointer_needed)
+           || (XEXP (rx, 0) == stack_pointer_rtx && ! frame_pointer_needed))
+    {
+      is_based_on_stack_pointer = (XEXP (rx, 0) == stack_pointer_rtx );
+    }
+  else
+    {
+      return (0);
+    }
+           
+
+  for (i = 0; i < num_reload_stack_slots; i++)
+    {
+      if (!is_based_on_stack_pointer)
+        {
+          if ((reload_insn == NULL || reload_insn == reload_slots[i].reload_insn)
+              && rtx_equal_p (XEXP (reload_slots[i].reload_stack_slot, 0), 
+                           XEXP (rx, 0)))
+	    {
+	      *indx = i;
+	      return (1);
+	    }
+	}
+      else
+        {
+          stack_slot_i = XEXP (reload_slots[i].reload_stack_slot, 0);
+          if (GET_CODE (stack_slot_i) == PLUS 
+              && XEXP ( stack_slot_i, 0) == stack_pointer_rtx)
+            {
+              if ( GET_CODE (XEXP ( stack_slot_i, 1)) == CONST_INT)
+                {
+                  stack_i_offset = XINT (XEXP ( stack_slot_i, 1), 0);
+                }
+              else
+                {
+                  abort ();
+                }
+            }
+          else if (stack_slot_i == stack_pointer_rtx)
+            {
+              stack_i_offset = 0;
+            }
+          else
+            {
+              abort ();
+            }
+          stack_i_offset -= reload_slots[i].cur_stack_offset;
+          if ((reload_insn == NULL || reload_insn == reload_slots[i].reload_insn)
+              && (stack_offset - cur_stack_offset == stack_i_offset))
+            {
+	      *indx = i;
+	      return (1);
+            }
+        }
+    }
+  return (0);
+}
+
+
+int
+are_same_reload_slots (slot1, offset1, slot2, offset2)
+  rtx slot1, slot2;
+  int offset1, offset2;
+{
+  rtx base_reg1, base_reg2;
+  int add_val1, add_val2;
+
+  if (GET_CODE (XEXP (slot1, 0)) == PLUS)
+    {
+      if (GET_CODE (XEXP (XEXP (slot1, 0), 0)) == REG)
+        {
+          base_reg1 = XEXP (XEXP (slot1, 0), 0);
+          if (GET_CODE (XEXP (XEXP (slot1, 0), 1)) == CONST_INT)
+            {
+              add_val1 = XINT (XEXP (XEXP (slot1, 0), 1), 0);
+            }
+        }
+    }
+  else
+    {
+      add_val1 = 0;
+      base_reg1 = XEXP (slot1, 0);
+    }
+    
+  if (GET_CODE (XEXP (slot2, 0)) == PLUS)
+    {
+      if (GET_CODE (XEXP (XEXP (slot2, 0), 0)) == REG)
+        {
+          base_reg2 = XEXP (XEXP (slot2, 0), 0);
+          if (GET_CODE (XEXP (XEXP (slot2, 0), 1)) == CONST_INT)
+            {
+              add_val2 = XINT (XEXP (XEXP (slot2, 0), 1), 0);
+            }
+        }
+    }
+  else
+    {
+      add_val2 = 0;
+      base_reg2 = XEXP (slot2, 0);
+    }
+  if (base_reg1 == frame_pointer_rtx)
+    {
+      offset1 = 0;
+    }
+  if (base_reg2 == frame_pointer_rtx)
+    {
+      offset2 = 0;
+    }
+  if (base_reg1 == base_reg2 
+      && ((add_val1 - offset1) == (add_val2 - offset2)))
+    {
+      return (1);
+    }
+  return (0);
+}
+
+/*
+  if x refernces a paramater then return 1
+  else return 0
+*/
+
+int 
+is_a_param_slot (x)
+     rtx x;
+{
+  if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PLUS
+      && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
+      && REGNO (XEXP (XEXP (x, 0), 0)) == ARG_POINTER_REGNUM
+      && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
+    {
+      return (1);
+    }
+  if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == REG
+      && REGNO (XEXP (x, 0)) == ARG_POINTER_REGNUM)
+    {
+      return (1);
+    }
+  return (0);
 }
diff -r -u -H -N gcc-2.6.3/rtl.c gcc-i2.6.3/rtl.c
--- gcc-2.6.3/rtl.c	Fri Mar 25 14:17:09 1994
+++ gcc-i2.6.3/rtl.c	Wed Feb 15 22:47:24 1995
@@ -173,11 +173,12 @@
 			   "NOTE_INSN_PROLOGUE_END", "NOTE_INSN_EPILOGUE_BEG",
 			   "NOTE_INSN_DELETED_LABEL", "NOTE_INSN_FUNCTION_BEG"};
 
+/* intel1 added REG_DEP_TMP */
 char *reg_note_name[] = { "", "REG_DEAD", "REG_INC", "REG_EQUIV", "REG_WAS_0",
 			  "REG_EQUAL", "REG_RETVAL", "REG_LIBCALL",
 			  "REG_NONNEG", "REG_NO_CONFLICT", "REG_UNUSED",
 			  "REG_CC_SETTER", "REG_CC_USER", "REG_LABEL",
-			  "REG_DEP_ANTI", "REG_DEP_OUTPUT" };
+			  "REG_DEP_ANTI", "REG_DEP_OUTPUT", "REG_DEP_TMP"  };
 
 /* Allocate an rtx vector of N elements.
    Store the length, and initialize all elements to zero.  */
@@ -301,6 +302,8 @@
   copy->volatil = orig->volatil;
   copy->unchanging = orig->unchanging;
   copy->integrated = orig->integrated;
+  /* intel1 */
+  copy->is_spill_rtx = orig->is_spill_rtx;
   
   format_ptr = GET_RTX_FORMAT (GET_CODE (copy));
 
diff -r -u -H -N gcc-2.6.3/rtl.def gcc-i2.6.3/rtl.def
--- gcc-2.6.3/rtl.def	Fri May  6 17:33:49 1994
+++ gcc-i2.6.3/rtl.def	Thu Feb 16 12:57:19 1995
@@ -346,7 +346,8 @@
    ---------------------------------------------------------------------- */
 
 /* An instruction that cannot jump.  */
-DEF_RTL_EXPR(INSN, "insn", "iuueiee", 'i')
+/* intel1 added last 0 - this field is used in scheduling */
+DEF_RTL_EXPR(INSN, "insn", "iuueiee0", 'i')
 
 /* An instruction that can possibly jump.
    Fields ( rtx->fld[] ) have exact same meaning as INSN's.  */
@@ -643,7 +644,11 @@
 
 /* Operand:
      0:  value to be shifted.
-     1:  number of bits.  */
+     1:  number of bits.  
+   ASHIFT and LSHIFT are distinguished because on some machines
+   these allow a negative operand and shift right in that case.
+*/
+DEF_RTL_EXPR(LSHIFT, "lshift", "ee", '2')
 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", '2')
 DEF_RTL_EXPR(ROTATE, "rotate", "ee", '2')
 
diff -r -u -H -N gcc-2.6.3/rtl.h gcc-i2.6.3/rtl.h
--- gcc-2.6.3/rtl.h	Thu Sep  1 22:13:31 1994
+++ gcc-i2.6.3/rtl.h	Wed Feb 15 22:47:24 1995
@@ -139,6 +139,9 @@
      In a REG, nonzero means this reg refers to the return value
      of the current function.  */
   unsigned integrated : 1;
+  /* intel1 Nonzero if this rtx is a spill rtx */
+  /* intel2 overlap: Nonzero if this rtx was created by memory_simplify */
+  unsigned is_spill_rtx: 1;
   /* The first element of the operands of this rtx.
      The number of operands and their types are controlled
      by the `code' field, according to rtl.def.  */
@@ -210,6 +213,10 @@
 
 #define RTX_INTEGRATED_P(RTX) ((RTX)->integrated)
 #define RTX_UNCHANGING_P(RTX) ((RTX)->unchanging)
+/* intel1 */
+#define RTX_IS_SPILL_P(RTX) ((RTX)->is_spill_rtx)
+/* intel2 - see a note above (for is_spill_rtx field) */
+#define RTX_IS_RISC_P(RTX) ((RTX)->is_spill_rtx)
 
 /* RTL vector.  These appear inside RTX's when there is a need
    for a variable number of things.  The principle use is inside
@@ -258,6 +265,11 @@
 #define PREV_INSN(INSN)	((INSN)->fld[1].rtx)
 #define NEXT_INSN(INSN)	((INSN)->fld[2].rtx)
 
+/* intel1 used in sched*/
+#define ORG_NEXT_INSN(INSN)	((INSN)->fld[7].rtx)
+/* intel1 used in (loop) opt of spills */
+#define SPILL_PSEUDO(INSN)	((INSN)->fld[7].rtint)
+
 /* The body of an insn.  */
 #define PATTERN(INSN)	((INSN)->fld[3].rtx)
 
@@ -347,7 +359,7 @@
 		REG_EQUAL = 5, REG_RETVAL = 6, REG_LIBCALL = 7,
 		REG_NONNEG = 8, REG_NO_CONFLICT = 9, REG_UNUSED = 10,
 		REG_CC_SETTER = 11, REG_CC_USER = 12, REG_LABEL = 13,
-		REG_DEP_ANTI = 14, REG_DEP_OUTPUT = 15 };
+		REG_DEP_ANTI = 14, REG_DEP_OUTPUT = 15, REG_DEP_TMP = 16 };
 
 /* Define macros to extract and insert the reg-note kind in an EXPR_LIST.  */
 #define REG_NOTE_KIND(LINK) ((enum reg_note) GET_MODE (LINK))
diff -r -u -H -N gcc-2.6.3/sched.c gcc-i2.6.3/sched.c
--- gcc-2.6.3/sched.c	Tue Sep 20 15:55:14 1994
+++ gcc-i2.6.3/sched.c	Wed Feb 15 23:52:38 1995
@@ -124,7 +124,29 @@
 #include "insn-config.h"
 #include "insn-attr.h"
 
+/* intel1 */
+#ifndef STACK_PUSH_CODE
+#ifdef STACK_GROWS_DOWNWARD
+#define STACK_PUSH_CODE PRE_DEC
+#else
+#define STACK_PUSH_CODE PRE_INC
+#endif
+#endif
 #ifdef INSN_SCHEDULING
+/* intel1 */
+#ifndef STACK_PUSH_CODE
+#ifdef STACK_GROWS_DOWNWARD
+#define STACK_PUSH_CODE PRE_DEC
+#else
+#define STACK_PUSH_CODE PRE_INC
+#endif
+#endif
+#ifdef SMALL_REGISTER_CLASSES
+  /* can't move anything past a hard register */
+static rtx first_insn_to_pivot;
+static rtx last_hard_reg_insn;
+#endif
+
 /* Arrays set up by scheduling for the same respective purposes as
    similar-named arrays set up by flow analysis.  We work with these
    arrays during the scheduling pass so we can compare values against
@@ -145,6 +167,17 @@
 static regset reg_pending_sets;
 static int reg_pending_sets_all;
 
+/* intel1 */
+#ifdef NO_STACK_REG_REORDER
+/* don't reorder insns that refernce stack registers */
+static rtx prev_stack_reg_insn = NULL;
+#endif
+/* intel1 */
+#ifdef STACK_REGS
+static int maintain_order = 0;
+#endif
+static FILE * cur_dump_file;
+
 /* Vector indexed by INSN_UID giving the original ordering of the insns.  */
 static int *insn_luid;
 #define INSN_LUID(INSN) (insn_luid[INSN_UID (INSN)])
@@ -292,13 +325,17 @@
 };
 
 /* Forward declarations.  */
+
+/* intel1 */
+static int is_part_of_group			PROTO((rtx, rtx));
+static int prev_insts_in_block		PROTO((int, rtx));
 static rtx canon_rtx			PROTO((rtx));
 static int rtx_equal_for_memref_p	PROTO((rtx, rtx));
 static rtx find_symbolic_term		PROTO((rtx));
 static int memrefs_conflict_p		PROTO((int, rtx, int, rtx,
 					       HOST_WIDE_INT));
 static void add_dependence		PROTO((rtx, rtx, enum reg_note));
-static void remove_dependence		PROTO((rtx, rtx));
+void remove_dependence		PROTO((rtx, rtx));
 static rtx find_insn_list		PROTO((rtx, rtx));
 static int insn_unit			PROTO((rtx));
 static unsigned int blockage_range	PROTO((int, rtx));
@@ -628,6 +665,241 @@
   else
     y = canon_rtx (y);
 
+  /* intel1
+     Missing special handling of a push onto the stack.  */
+  if (reload_completed
+      &&
+      (GET_CODE (x) == STACK_PUSH_CODE
+       && XEXP (x, 0) == stack_pointer_rtx)
+      ||
+      (GET_CODE (y) == STACK_PUSH_CODE
+       && XEXP (y, 0) == stack_pointer_rtx)
+      )
+    {
+      rtx *push, *non_push;
+
+      if (GET_CODE (x) == STACK_PUSH_CODE
+          && XEXP (x, 0) == stack_pointer_rtx)
+        {
+          push = &x;
+          non_push = &y;
+        }
+      else
+        {
+          push = &y;
+          non_push = &x;
+        }
+      if (find_symbolic_term (*non_push) != NULL)
+        {  /* push onto stack does not conflict with global */
+          return (0);
+        }
+      if (RTX_IS_SPILL_P (*non_push))
+        { /* push onto stack does not overlap with spill slot */
+          return (0);
+        }
+      /* Check to see if the non push is a stack slot */
+      if (c == 0 && GET_CODE (*non_push) == PLUS 
+          && XEXP ( *non_push, 0) == stack_pointer_rtx 
+          && !frame_pointer_needed)
+        {
+          if ( GET_CODE (XEXP ( *non_push, 1)) == CONST_INT
+               && XINT (XEXP (*non_push, 1), 0) 
+                  > GET_MODE_SIZE (GET_MODE (*push)))
+            {
+              return (0);
+            }
+        }
+      else if (c == 0 && GET_CODE (*non_push) == PLUS 
+          && XEXP ( *non_push, 0) == frame_pointer_rtx
+          && frame_pointer_needed)
+        {
+          if ( GET_CODE (XEXP ( *non_push, 1)) == CONST_INT)
+            {
+              return (0); /* Definitely not the same as the push if
+                             frame_pointer is used.  */
+            }
+        }
+    }
+  
+  
+  /* intel1
+     Missing handling of a spill slot - can't conflict with anything
+     that is not a spill slot */
+  if (reload_completed && RTX_IS_SPILL_P (x) != RTX_IS_SPILL_P (y)
+      && !rtx_equal_p(x,y) /*just to be safe */)
+    { /* Actually some spill slots are not being marked at present -
+         but no non spill slots are ever marked.  So make sure
+         that the non spill slot does not overlap with spill slot */
+      rtx *spill, *non_spill;
+      int *spill_size, *non_spill_size, spill_offset, non_spill_offset, 
+          spill_unknown, non_spill_unknown, maybe_spill;
+      spill_unknown = 0;
+      non_spill_unknown = 0;
+      maybe_spill = 0;
+      if (RTX_IS_SPILL_P (x))
+        {
+          spill = &x;
+          spill_size = &xsize;
+          non_spill = &y;
+          non_spill_size = &ysize;
+        }
+      else
+        {
+          spill = &y;
+          spill_size = &ysize;
+          non_spill = &x;
+          non_spill_size = &xsize;
+        }
+      if (GET_CODE (*non_spill) == PLUS)
+        {
+          if (GET_CODE (XEXP (*non_spill, 1)) == CONST_INT)
+            {
+              non_spill_offset = XINT (XEXP (*non_spill, 1), 0);
+            }
+          else
+            {
+              non_spill_unknown = 1;
+            }
+          if (GET_CODE (XEXP (*non_spill, 0)) == REG
+              && ((frame_pointer_needed && XEXP (*non_spill, 0) == frame_pointer_rtx)
+                  || XEXP (*non_spill, 0) == stack_pointer_rtx))
+            {
+              maybe_spill = 1; /* It may overlap the spill slot */
+            }
+        }
+      else
+      if (GET_CODE (*non_spill) == REG
+          && ((frame_pointer_needed && *non_spill == frame_pointer_rtx)
+              || *non_spill == stack_pointer_rtx))
+        {
+          non_spill_offset = 0;
+          maybe_spill = 1;
+        }
+      if (maybe_spill == 0)
+        return (0);
+        
+      if (GET_CODE (*spill) == PLUS)
+        {
+          if (GET_CODE (XEXP (*spill, 1)) == CONST_INT)
+            {
+              spill_offset = XINT (XEXP (*spill, 1), 0);
+            }
+          else
+            {
+              spill_unknown = 1;
+            }
+          if (GET_CODE (XEXP (*spill, 0)) == REG
+              && ((frame_pointer_needed && XEXP (*spill, 0) == frame_pointer_rtx)
+                  || XEXP (*spill, 0) == stack_pointer_rtx))
+            {
+              ; /* ok */
+            }
+          else
+            {
+              spill_unknown = 1;
+            }
+        }
+      else
+      if (GET_CODE (*spill) == REG
+          && ((frame_pointer_needed && *spill == frame_pointer_rtx)
+              || *spill == stack_pointer_rtx))
+        {
+         spill_offset = 0;
+        }
+      else
+        {
+          spill_unknown = 1;
+        }
+      if (non_spill_unknown == 0  && spill_unknown == 0)
+        {
+          if (non_spill_offset < spill_offset)
+            return (!(non_spill_offset + *non_spill_size <= spill_offset));
+          else
+            return (!(spill_offset + *spill_size <= non_spill_offset));
+        } 
+    }
+  
+  /* intel1
+     Missing handling two spill slots conflict only if they overlap */
+  if (reload_completed && RTX_IS_SPILL_P (y) && RTX_IS_SPILL_P (x) 
+      && c == 0 
+      && !rtx_equal_p(y, x))
+    {
+      int x_offset, y_offset, x_unknown, y_unknown;
+      x_unknown = y_unknown = 0;
+      if (GET_CODE (x) == PLUS)
+        {
+          if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+            {
+              x_offset = XINT (XEXP (x, 1), 0);
+            }
+          else
+            {
+              x_unknown = 1;
+            }
+          if (GET_CODE (XEXP (x, 0)) == REG
+              && ((frame_pointer_needed && XEXP (x, 0) == frame_pointer_rtx)
+                  || XEXP (x, 0) == stack_pointer_rtx))
+            {
+              ; /* ok */
+            }
+          else
+            {
+              x_unknown = 1;
+            }
+        }
+      else
+      if (GET_CODE (x) == REG
+          && ((frame_pointer_needed && x == frame_pointer_rtx)
+              || x == stack_pointer_rtx))
+        {
+         x_offset = 0;
+        }
+      else
+        {
+          x_unknown = 1;
+        }
+      if (GET_CODE (y) == PLUS)
+        {
+          if (GET_CODE (XEXP (y, 1)) == CONST_INT)
+            {
+              y_offset = XINT (XEXP (y, 1), 0);
+            }
+          else
+            {
+              y_unknown = 1;
+            }
+          if (GET_CODE (XEXP (y, 0)) == REG
+              && ((frame_pointer_needed && XEXP (y, 0) == frame_pointer_rtx)
+                  || XEXP (y, 0) == stack_pointer_rtx))
+            {
+              ; /* ok */
+            }
+          else
+            {
+              y_unknown = 1;
+            }
+        }
+      else
+      if (GET_CODE (y) == REG
+          && ((frame_pointer_needed && y == frame_pointer_rtx)
+              || y == stack_pointer_rtx))
+        {
+         y_offset = 0;
+        }
+      else
+        {
+          y_unknown = 1;
+        }
+      if (x_unknown == 0  && y_unknown == 0)
+        {
+          if (x_offset < y_offset)
+            return (!(x_offset + xsize <= y_offset));
+          else
+            return (!(y_offset + ysize <= x_offset));
+        } 
+    }
+  
   if (rtx_equal_for_memref_p (x, y))
     return (xsize == 0 || ysize == 0 ||
 	    (c >= 0 && xsize > c) || (c < 0 && ysize+c > 0));
@@ -921,7 +1193,15 @@
 	 SCHED_GROUP_P.  */
       while (NEXT_INSN (next) && SCHED_GROUP_P (NEXT_INSN (next))
 	     && GET_CODE (NEXT_INSN (next)) != CODE_LABEL)
+      {
+        /* intel1 - next might already be part of this SCHED_GROUP,
+        */
+        if(next==insn )
+        {
+	  return;
+        }
 	next = NEXT_INSN (next);
+      }
 
       /* Again, don't depend an insn on itself.  */
       if (insn == next)
@@ -955,7 +1235,7 @@
 /* Remove ELEM wrapped in an INSN_LIST from the LOG_LINKS
    of INSN.  Abort if not found.  */
 
-static void
+void
 remove_dependence (insn, elem)
      rtx insn;
      rtx elem;
@@ -1216,9 +1496,22 @@
       if (function_units[unit].blockage_range_function)
 	{
 	  if (function_units[unit].blockage_function)
+	    {
+	    /* intel1 */
+#ifdef ADJUST_BLOCKAGE
+            {
+              int blockage = (function_units[unit].blockage_function
+		       (insn, unit_last_insn[instance]));
+	      ADJUST_BLOCKAGE (unit_last_insn[instance], insn, blockage);
+	      tick +=  blockage 
+		       - function_units[unit].max_blockage;
+	    }
+#else
 	    tick += (function_units[unit].blockage_function
 		     (insn, unit_last_insn[instance])
 		     - function_units[unit].max_blockage);
+#endif
+	    }
 	  else
 	    tick += ((int) MAX_BLOCKAGE_COST (blockage_range (unit, insn))
 		     - function_units[unit].max_blockage);
@@ -1705,6 +1998,33 @@
 		/* Function calls clobber all call_used regs.  */
 		add_dependence (insn, last_function_call, REG_DEP_ANTI);
 	    }
+#ifdef SMALL_REGISTER_CLASSES
+/* intel1 
+   lifetime of hard registers must not be changed so this
+   insn becomes a pivot in the block.
+*/
+          if(reload_completed==0 && regno!=STACK_POINTER_REGNUM
+             && regno!=FRAME_POINTER_REGNUM)
+            {
+              rtx tinsn;
+
+              tinsn = first_insn_to_pivot;
+              while(tinsn!=insn)
+                {
+                  if(GET_CODE(tinsn)==INSN || GET_CODE(tinsn)==CALL_INSN)
+                  {
+                    add_dependence (insn,tinsn,0);
+                  }
+                  tinsn = NEXT_INSN(tinsn);
+                }
+              if(last_hard_reg_insn)
+                {
+                  add_dependence (insn,last_hard_reg_insn,0);
+                }
+              first_insn_to_pivot = insn; 
+              last_hard_reg_insn = insn;
+            }
+#endif
 	}
       else
 	{
@@ -1805,6 +2125,26 @@
   if (x == 0)
     return;
 
+/* intel1 */
+#ifdef STACK_REGS
+#ifdef IS_STACK_MODE
+#ifdef NO_STACK_REG_REORDER
+  if (NO_STACK_REG_REORDER)
+    {
+      if (prev_stack_reg_insn!=NULL && insn!=prev_stack_reg_insn
+         && IS_STACK_MODE (GET_MODE (x)))
+        {
+	    add_dependence (insn, prev_stack_reg_insn, REG_DEP_TMP);
+        }
+      if (IS_STACK_MODE (GET_MODE (x)))
+        {
+          prev_stack_reg_insn = insn;
+        }
+    }
+#endif
+#endif
+#endif
+
   code = GET_CODE (x);
 
   switch (code)
@@ -1870,6 +2210,33 @@
 		  /* Function calls clobber all call_used regs.  */
 		  add_dependence (insn, last_function_call, REG_DEP_ANTI);
 	      }
+#ifdef SMALL_REGISTER_CLASSES
+/* intel1 
+   lifetime of hard registers must not be changed so this
+   insn becomes a pivot in the block.
+*/
+            if(reload_completed==0 && regno!=STACK_POINTER_REGNUM
+             && regno!=FRAME_POINTER_REGNUM)
+              {
+                rtx tinsn;
+  
+                tinsn = first_insn_to_pivot;
+                while(tinsn!=insn)
+                  {
+                    if(GET_CODE(tinsn)==INSN || GET_CODE(tinsn)==CALL_INSN)
+                    {
+                      add_dependence (insn,tinsn,0);
+                    }
+                    tinsn = NEXT_INSN(tinsn);
+                  }
+                if(last_hard_reg_insn)
+                  {
+                    add_dependence (insn,last_hard_reg_insn,0);
+                  }
+                first_insn_to_pivot = insn; 
+                last_hard_reg_insn = insn;
+              }
+#endif
 	  }
 	else
 	  {
@@ -2022,6 +2389,14 @@
   int maxreg = max_reg_num ();
   int i;
 
+#ifdef SMALL_REGISTER_CLASSES
+/* intel1 */
+  if (reload_completed==0 && last_hard_reg_insn!=NULL)
+    {
+      add_dependence (insn,last_hard_reg_insn,0);
+    }
+#endif
+
   if (code == SET || code == CLOBBER)
     sched_analyze_1 (x, insn);
   else if (code == PARALLEL)
@@ -2169,6 +2544,27 @@
   register int luid = 0;
   rtx loop_notes = 0;
 
+/* intel1 */
+  rtx pinsn;
+#ifdef STACK_REGS
+  pinsn = NULL;
+  if (maintain_order && reload_completed==0)
+    { /* A block we don't want to change order but keep track of
+         register life information.  */
+      for (insn = head; insn != tail; insn = NEXT_INSN (insn))
+        {
+          if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
+            {
+              if (pinsn)
+                {
+                  add_dependence (insn, pinsn, REG_DEP_TMP);
+                }
+              pinsn = insn;
+            }
+        }
+    }
+#endif
+
   for (insn = head; ; insn = NEXT_INSN (insn))
     {
       INSN_LUID (insn) = luid++;
@@ -2513,6 +2909,22 @@
       rtx note;
       int n_deaths = 0;
 
+      /* intel1 */
+#ifdef STACK_REGS
+#ifdef IS_STACK_MODE
+#ifdef STACK_REG_REORDER
+      /* For stack registers don't take lifetimes into account */
+      if (birthing_insn_p (PATTERN (prev)) && STACK_REG_REORDER && 0)
+	{
+	  if (GET_CODE (prev) == INSN && GET_CODE (PATTERN (prev)) == SET
+	      && IS_STACK_MODE (GET_MODE (SET_DEST (PATTERN (prev)))))
+	    {
+	      return;
+	    }
+	}
+#endif
+#endif
+#endif
       /* ??? This code has no effect, because REG_DEAD notes are removed
 	 before we ever get here.  */
       for (note = REG_NOTES (prev); note; note = XEXP (note, 1))
@@ -3136,10 +3548,44 @@
   register struct sometimes *regs_sometimes_live;
   int sometimes_max;
 
+  /* intel1 */
+#ifdef HAVE_cc0
+  rtx prev_to_cc0_setter;
+#endif
+#ifdef AGI
+  int possible_agi = 0;
+#endif
+#ifdef NO_STACK_REG_REORDER
+  rtx tinsn, tlink, tprev_link;
+#endif /* NO_STACK_REG_REORDER */
+
   if (file)
     fprintf (file, ";;\t -- basic block number %d from %d to %d --\n",
 	     b, INSN_UID (basic_block_head[b]), INSN_UID (basic_block_end[b]));
 
+/* intel1 */
+#ifdef NO_STACK_REG_REORDER
+  prev_stack_reg_insn = NULL;
+#endif
+#ifdef STACK_REGS
+  maintain_order = 0;
+  if (STACK_NON_STACK_INTERLEAVE || STACK_REG_REORDER)
+    {
+      rtx tinsn = head;
+      int found_stack_mode = 0;
+      while (tinsn && !found_stack_mode && tinsn != tail)
+        {
+          if (GET_CODE (tinsn) == INSN && GET_CODE (PATTERN (tinsn)) == SET
+              && IS_STACK_MODE (GET_MODE (SET_DEST (PATTERN (tinsn)))))
+            {
+              found_stack_mode = 1;
+            }
+          tinsn = next_nonnote_insn (tinsn);
+        }
+      maintain_order = !found_stack_mode;
+    }
+#endif
+
   i = max_reg_num ();
   reg_last_uses = (rtx *) alloca (i * sizeof (rtx));
   bzero ((char *) reg_last_uses, i * sizeof (rtx));
@@ -3231,6 +3677,11 @@
 
   LOG_LINKS (sched_before_next_call) = 0;
 
+#ifdef SMALL_REGISTER_CLASSES
+/* intel1 */
+  first_insn_to_pivot = head;
+  last_hard_reg_insn = NULL;
+#endif
   n_insns += sched_analyze (head, tail);
   if (n_insns == 0)
     {
@@ -3247,6 +3698,92 @@
   /* TAIL is now the last of the insns to be rearranged.
      Put those insns into the READY vector.  */
   insn = tail;
+/* intel1 */
+#ifdef HAVE_cc0
+  /* intel1 further if we have done compare elimination then the
+     insn before the compare should not be moved */
+  if (head!=tail 
+     && GET_CODE (basic_block_end[b])==JUMP_INSN 
+     && GET_CODE (PATTERN (basic_block_end[b]))!=PARALLEL 
+     && GET_CODE (PATTERN (basic_block_end[b]))!=ADDR_VEC 
+     && GET_CODE (XEXP (SET_SRC (PATTERN (basic_block_end[b])),0))==NE 
+     && GET_CODE (PREV_INSN (basic_block_end[b]))==INSN 
+     && GET_CODE (PATTERN (PREV_INSN (basic_block_end[b])))==SET 
+     && SET_DEST (PATTERN (PREV_INSN (basic_block_end[b])))==cc0_rtx 
+     && GET_CODE (SET_SRC (PATTERN (PREV_INSN (basic_block_end[b]))))==COMPARE 
+     && XEXP (SET_SRC (PATTERN (PREV_INSN (basic_block_end[b]))),1)==const0_rtx)
+    {
+      prev_to_cc0_setter = 
+        prev_nonnote_insn( PREV_INSN (basic_block_end[b]));
+      if (! (prev_to_cc0_setter && RTX_IS_RISC_P (prev_to_cc0_setter))
+         && prev_insts_in_block (b,PREV_INSN (basic_block_end[b])) 
+         && (head != PREV_INSN (basic_block_end[b])) )
+        {
+          SCHED_GROUP_P (PREV_INSN (basic_block_end[b]))=1;
+          /* Also must remove the 
+             prev_nonnote_insn(PREV_INSN(basic_block_end[b]) from the
+             dependency chain of both basic_block_end[b] and
+             PREV_INSN(basic_block_end[b]), to ensure that it doesn't
+             go through the ready list also */
+          if(prev_to_cc0_setter 
+             && (GET_CODE (prev_to_cc0_setter)==INSN 
+                 || GET_CODE (prev_to_cc0_setter)==CALL_INSN )
+	     && ! RTX_IS_RISC_P (prev_to_cc0_setter))  /* intel2 */
+            {
+	      if (find_insn_list (prev_to_cc0_setter, 
+	                          LOG_LINKS (PREV_INSN (basic_block_end[b]))))
+	        remove_dependence (PREV_INSN (basic_block_end[b]), 
+	                           prev_to_cc0_setter);
+	      if (find_insn_list (prev_to_cc0_setter, 
+	                          LOG_LINKS ( basic_block_end[b])))
+	        remove_dependence (basic_block_end[b], 
+	                           prev_to_cc0_setter);
+	    }
+        }
+      else
+        SCHED_GROUP_P(PREV_INSN(basic_block_end[b]))=0;
+    } 
+  else
+  if (head!=tail 
+     && GET_CODE (basic_block_end[b])==JUMP_INSN 
+     && GET_CODE (PATTERN (basic_block_end[b]))!=PARALLEL 
+     && GET_CODE (PATTERN (basic_block_end[b]))!=ADDR_VEC 
+     && GET_CODE (PREV_INSN (basic_block_end[b]))==INSN 
+     && GET_CODE (PATTERN (PREV_INSN (basic_block_end[b])))==SET 
+     && SET_DEST (PATTERN (PREV_INSN (basic_block_end[b])))==cc0_rtx 
+     && GET_CODE (SET_SRC (PATTERN (PREV_INSN (basic_block_end[b]))))!=COMPARE)
+    {
+      prev_to_cc0_setter = 
+        prev_nonnote_insn( PREV_INSN (basic_block_end[b]));
+      if (! (prev_to_cc0_setter && RTX_IS_RISC_P (prev_to_cc0_setter))
+         && prev_insts_in_block (b,PREV_INSN (basic_block_end[b])) 
+         && (head != PREV_INSN (basic_block_end[b])) )
+        {
+          SCHED_GROUP_P (PREV_INSN (basic_block_end[b]))=1;
+          /* Also must remove the 
+             prev_nonnote_insn(PREV_INSN(basic_block_end[b]) from the
+             dependency chain of both basic_block_end[b] and
+             PREV_INSN(basic_block_end[b]), to ensure that it doesn't
+             go through the ready list also */
+          if(prev_to_cc0_setter 
+             && (GET_CODE (prev_to_cc0_setter) == INSN 
+                 || GET_CODE (prev_to_cc0_setter) == CALL_INSN )
+	     && ! RTX_IS_RISC_P (prev_to_cc0_setter))  /* intel2 */
+            {
+	      if (find_insn_list (prev_to_cc0_setter, 
+	                          LOG_LINKS (PREV_INSN (basic_block_end[b]))))
+	        remove_dependence (PREV_INSN (basic_block_end[b]), 
+	                           prev_to_cc0_setter);
+	      if (find_insn_list (prev_to_cc0_setter, 
+	                          LOG_LINKS ( basic_block_end[b])))
+	        remove_dependence (basic_block_end[b], 
+	                           prev_to_cc0_setter);
+	    }
+        }
+      else
+        SCHED_GROUP_P(PREV_INSN(basic_block_end[b]))=0;
+    } 
+#endif
 
   /* For all branches, calls, uses, and cc0 setters, force them to remain
      in order at the end of the block by adding dependencies and giving
@@ -3664,14 +4201,19 @@
 		for (; insn; insn = NEXT_INSN (insn))
 		  {
 		    if (file)
-		      fprintf (file, ";; launching %d before %d with %d stalls at T-%d\n",
-			       INSN_UID (insn), INSN_UID (last), stalls, clock);
+		      fprintf (file, ";; launching %d before %d with %d stalls at T-%d i_q[%d]\n",
+			       INSN_UID (insn), INSN_UID (last), stalls, clock, new_ready);
 		    ready[new_ready++] = insn;
 		    q_size -= 1;
 		  }
 		insn_queue[NEXT_Q_AFTER (q_ptr, stalls)] = 0;
 		break;
 	      }
+         /* intel1 */
+#ifdef AGI
+          if (new_ready == 1)
+            possible_agi = 1;
+#endif
 
 	  q_ptr = NEXT_Q_AFTER (q_ptr, stalls); clock += stalls;
 	}
@@ -3682,7 +4224,8 @@
 
       if (file)
 	{
-	  fprintf (file, ";; ready list at T-%d:", clock);
+	  fprintf (file, ";; ready list at T-%d (new_r %d n_r %d):", 
+	  clock, new_ready, n_ready);
 	  for (i = 0; i < new_ready; i++)
 	    fprintf (file, " %d (%x)",
 		     INSN_UID (ready[i]), INSN_PRIORITY (ready[i]));
@@ -3910,6 +4453,21 @@
 	      last = insn;
 	    }
 	}
+#ifdef AGI
+      if (possible_agi && reload_completed && flag_swap_for_agi)
+        {
+          rtx next_to_last = NEXT_INSN (last);	
+          if (try_eliminate_agi (last, file))
+            { /* last has been swapped downwards */
+              if (PREV_INSN (last) == tail)
+                { /* last has moved down to become tail */
+                  tail = last;
+                }
+              last = next_to_last;
+              insn = last;
+            }
+        }
+#endif
     }
   if (q_size != 0)
     abort ();
@@ -3922,6 +4480,34 @@
      TAIL is the last of those insns.  */
   head = insn;
 
+/* intel1 */
+#ifdef NO_STACK_REG_REORDER
+  if (NO_STACK_REG_REORDER)
+    { /* remove all the REG_DEP_TMP dependencies that were added */
+      for (tinsn = head; tinsn != NEXT_INSN (tail); tinsn = NEXT_INSN (tinsn))
+        {
+	  tlink = LOG_LINKS (tinsn); 
+	  tprev_link = tlink;
+	  while (tlink) 
+	    {
+	      if (REG_NOTE_KIND (tlink) == REG_DEP_TMP)
+	        {
+	          if (tlink == LOG_LINKS (tinsn))
+	            {
+	              LOG_LINKS (tinsn) = XEXP (tlink, 1);
+	            }
+	          else
+	            {
+	              XEXP (tprev_link, 1) = XEXP (tlink, 1);
+	            }
+	        }
+	      tprev_link = tlink;
+	      tlink = XEXP (tlink, 1);
+	    }
+        }
+    }
+#endif /* NO_STACK_REG_REORDER */
+
   /* NOTE_LIST is the end of a chain of notes previously found
      among the insns.  Insert them at the beginning of the insns.  */
   if (note_list != 0)
@@ -4646,11 +5232,99 @@
   int b;
   rtx insn;
 
+  cur_dump_file = dump_file;
   /* Taking care of this degenerate case makes the rest of
      this code simpler.  */
   if (n_basic_blocks == 0)
     return;
 
+  /* intel1 */
+#ifdef STACK_REGS
+  if (STACK_NON_STACK_INTERLEAVE || STACK_REG_REORDER)
+    {
+      rtx tinsn = get_insns();
+      int found_stack_mode = 0;
+      while (tinsn && !found_stack_mode)
+        {
+          if (GET_CODE (tinsn) == INSN && GET_CODE (PATTERN (tinsn)) == SET
+              && IS_STACK_MODE (GET_MODE (SET_DEST (PATTERN (tinsn)))))
+            {
+              found_stack_mode = 1;
+            }
+          tinsn = next_nonnote_insn (tinsn);
+        }
+      if (!found_stack_mode) /* Nothing to do */
+        {
+          unused_insn_list = 0;
+          unused_expr_list = 0;
+          return;
+        }
+    }
+#endif
+    /* intel1 - Remove all LOG_LINK information as the reload pass
+       may have invalidated some LOG_LINKs eg:
+       before reload:
+       (insn 21 20 24 (set (reg:SI 25)
+               (ashiftrt:SI (reg/v:SI 22)
+                   (const_int 3))) 142 {ashrsi3} (nil)
+           (nil))
+
+       (insn 24 21 28 (set (reg/v:SI 22)
+               (and:SI (reg/v:SI 22)
+                   (const_int 7))) 102 {andsi3} (nil)
+           (nil))
+
+       (insn 28 24 29 (set (reg:QI 27)
+               (and:QI (mem:QI (plus:SI (reg:SI 25)
+                           (symbol_ref:SI ("buf"))))
+                   (mem/s:QI (plus:SI (reg/v:SI 22)
+                           (symbol_ref:SI ("rmask")))))) 104 {andqi3}
+           (insn_list 21 (insn_list 24 (nil)))
+           (nil))
+
+       after reload:
+       (insn:HI 21 281 24 (set (reg:SI %edx)
+               (ashiftrt:SI (reg:SI %edx)
+                   (const_int 3))) 142 {ashrsi3} (nil)
+           (nil))
+
+
+       (insn 24 21 284 (set (reg/v:SI %ebp)
+               (and:SI (reg/v:SI %ebp)
+                   (const_int 7))) 102 {andsi3} (nil)
+           (nil))
+
+       (insn 284 24 28 (set (reg:QI %cl)
+               (mem:QI (plus:SI (reg:SI %edx)
+                       (symbol_ref:SI ("buf"))))) -1 (nil)
+           (nil))
+
+       (insn:HI 28 284 285 (set (reg:QI %cl)
+               (and:QI (reg:QI %cl)
+                   (mem/s:QI (plus:SI (reg/v:SI %ebp)
+                           (symbol_ref:SI ("rmask")))))) 104 {andqi3}
+           (insn_list 21 (insn_list 24 (nil)))
+            (nil))
+
+     Note that the LOG_LINKs of insn 28 is no longer valid - it does
+     not depend directly on insn 21 any longer. Leaving the LOG_LINKs
+     as they are may produce suboptimal, although valid, schedules.
+     */
+  if (reload_completed)
+    {
+      rtx tinsn = get_insns();
+      while (tinsn)
+        {
+          if (GET_CODE (tinsn) == INSN || GET_CODE (tinsn) == CALL_INSN
+              || GET_CODE (tinsn) == JUMP_INSN)
+            {
+              LOG_LINKS (tinsn) = NULL;
+            }
+          tinsn = next_nonnote_insn (tinsn);
+        }
+    }
+
+
   /* Create an insn here so that we can hang dependencies off of it later.  */
   sched_before_next_call
     = gen_rtx (INSN, VOIDmode, 0, NULL_RTX, NULL_RTX,
@@ -4791,6 +5465,8 @@
 		  PUT_CODE (insn, NOTE);
 		  NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
 		  NOTE_SOURCE_FILE (insn) = 0;
+		  /* intel1 */
+		  SCHED_GROUP_P(insn) = 0;
 		}
 
 	      continue;
@@ -4813,6 +5489,8 @@
 		  PUT_CODE (insn, NOTE);
 		  NOTE_SOURCE_FILE (insn) = 0;
 		  NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
+		  /* intel1 */
+		  SCHED_GROUP_P(insn) = 0;
 		  if (insn == basic_block_head[b])
 		    basic_block_head[b] = first;
 		  if (insn == basic_block_end[b])
@@ -4858,6 +5536,8 @@
 		notes++;
 		NOTE_SOURCE_FILE (insn) = 0;
 		NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
+		/* intel1 */
+		SCHED_GROUP_P(insn) = 0;
 	      }
 	    /* If the line number is unchanged, LINE is redundant.  */
 	    else if (line
@@ -4941,4 +5621,286 @@
 	  }
     }
 }
+/* intel1
+   return 1 if insn_b is part of the SCHED_GROUP of insn_a 
+*/
+static int
+is_part_of_group (insn_a, insn_b)
+     rtx insn_a;
+     rtx insn_b;
+{
+  rtx pn;
+
+  pn = PREV_INSN(insn_a);
+  while(pn)
+    {
+      if(GET_CODE(pn)==INSN || GET_CODE(pn)==CALL_INSN ||
+         GET_CODE(pn)==JUMP_INSN)
+        {
+          if(pn==insn_b)
+            {
+              return(1);
+            }
+          if(!SCHED_GROUP_P(pn))
+            {
+              return(0);
+            }
+        }
+      pn = PREV_INSN(pn);
+    }
+  return(0);
+}
+
+/* intel1 return 1 if there are insts in block b before insn */
+static int prev_insts_in_block(b, insn)
+int b;
+rtx insn;
+{
+  insn = PREV_INSN(insn);
+  while(insn && insn!=basic_block_head[b])
+    {
+      if(GET_RTX_CLASS (GET_CODE (insn)) == 'i')
+        {
+          return(1);
+        }
+      insn = PREV_INSN(insn);
+    }
+  if(insn && 
+     insn==basic_block_head[b] && GET_RTX_CLASS (GET_CODE (insn)) == 'i')
+    {
+      return(1);
+    }
+  return(0);
+}
+
+#ifdef AGI
+/* intel1
+  If insn updates a register by a constant and NEXT_INSN (insn) uses
+  that register as a base or index and this is the only dependence
+  between the two insns - then try to swap these two insns by replacing
+  register with (register + constant) in NEXT_INSN (insn).  
+*/
+int try_eliminate_agi (insn, file)
+  rtx insn;
+  FILE * file;
+{
+  rtx next;
+  int success;
+  
+  next = NEXT_INSN (insn);
+  if (!try_swap (insn))
+    {
+      return (0);
+    }
+  /* Now swap insn with next.  */
+  PREV_INSN (NEXT_INSN (next)) = insn;
+  NEXT_INSN (insn) = NEXT_INSN (next);
+  NEXT_INSN (next) = insn;
+  PREV_INSN (insn) = next;
+  success = 1;
+  if (file)
+    {
+      fprintf (file, ";; swapped %d with %d to eliminate agi, %d is last scheduled\n",
+      INSN_UID (insn), INSN_UID (next), INSN_UID (next));
+    }
+  while (success)
+    {  /* Keep trying to swap insn downwards */
+      success = try_swap (insn);
+      if (success)
+        {
+          next = NEXT_INSN (insn);
+          if (file)
+            {
+              fprintf (file, ";;   (swapped %d with %d to eliminate agi)\n",
+              INSN_UID (insn), INSN_UID (next));
+            }
+          NEXT_INSN (PREV_INSN (insn)) = next;
+          PREV_INSN (next) = PREV_INSN (insn);
+          PREV_INSN (NEXT_INSN (next)) = insn;
+          NEXT_INSN (insn) = NEXT_INSN (next);
+          NEXT_INSN (next) = insn;
+          PREV_INSN (insn) = next;
+        }
+    }
+  return (1);
+}
+
+int try_swap (insn)
+  rtx insn;
+{
+  rtx next, tmp, src, dest, next_src, next_dest, reg_to_update,
+      copy_dest, copy_src;
+  int offst_update, updates_by_const, regno_updated, length, i,
+      insn_code_number, save_code;
+  char * fmt, * storage;
+  next = NEXT_INSN (insn);
+  if (GET_CODE (insn) != INSN || next == NULL || GET_CODE (next) != INSN
+      || GET_CODE (PATTERN (insn)) != SET || GET_CODE (PATTERN (next)) != SET)
+    {
+      return (0);
+    }
+  src = SET_SRC (PATTERN (insn));
+  dest = SET_DEST (PATTERN (insn));
+  next_src = SET_SRC (PATTERN (next));
+  next_dest = SET_DEST (PATTERN (next));
+  if (next_dest == cc0_rtx)
+    {
+      return (0);
+    }
+  if (rtx_equal_p (dest, next_dest))
+    {
+      return (0);
+    }
+  if (GET_CODE (next_dest) == REG)
+    {
+      if (reg_overlap_mentioned_p (next_dest, PATTERN (insn)))
+        {
+          return (0);
+        }
+    }
+  /* See if insn updates some register by a constant ammount */
+  updates_by_const = 0;
+  if (GET_CODE (dest) == REG)
+    {
+      if ((GET_CODE (src) == PLUS || GET_CODE (src) == MINUS)
+          && rtx_equal_p (XEXP (src, 0), dest) 
+          && GET_CODE (XEXP (src, 1)) == CONST_INT)
+        {
+          updates_by_const = 1;
+          offst_update 
+            = XINT (XEXP (src, 1), 0) * (GET_CODE (src) == PLUS ? 1 : -1);
+          regno_updated = REGNO (dest);
+          reg_to_update = dest;
+        }
+    }
+  if (GET_CODE (dest) == MEM && push_operand (dest, GET_MODE (dest))
+      && (GET_CODE (src) == REG
+          || (GET_CODE (src) == MEM && !side_effects_p (XEXP (src, 0)))))
+    {
+      updates_by_const = 1;
+      offst_update = GET_MODE_SIZE (GET_MODE (dest));
+      if (GET_CODE (XEXP (dest, 0)) == PRE_DEC ||
+          GET_CODE (XEXP (dest, 0)) == POST_DEC)
+        {
+          offst_update *= -1;
+        }
+      regno_updated = STACK_POINTER_REGNUM;
+      reg_to_update = stack_pointer_rtx;
+    }
+  if (!updates_by_const)
+    {
+      return (0);
+    }
+  if (!reg_overlap_mentioned_p (reg_to_update, PATTERN (next)))
+    {
+      return (0);
+    }
+  if (GET_CODE (dest) == MEM)
+    {
+      if (GET_CODE (next_src) == MEM
+           && true_dependence (dest, next_src))
+        {
+          return (0);
+        }
+      else if (GET_CODE (next_src) != REG)
+        {
+          fmt = GET_RTX_FORMAT (GET_CODE (next_src));
+          length = GET_RTX_LENGTH (GET_CODE (next_src));
+          for (i=0; i<length; i++)
+            {
+              if (fmt[i] == 'e' && GET_CODE (XEXP (next_src, i)) == MEM)
+                {
+                  if (true_dependence (dest, XEXP (next_src, i)))
+                    {
+                      return (0);
+                    }
+                }
+            }
+        }
+      if (GET_CODE (next_dest) == MEM
+           && true_dependence (dest, next_dest))
+        {
+          return (0);
+        }
+    }
+  if (GET_CODE (src) == MEM)
+    {
+      if (GET_CODE (next_dest) == MEM
+           && true_dependence (src, next_dest))
+        {
+          return (0);
+        }
+    }
+  /* First check that regno_updated is not used in next with any
+     other mode */
+  init_undo_buf ();
+  subst_in_insn (next, PATTERN (next), reg_to_update, const0_rtx, 0, 0);
+  if (reg_overlap_mentioned_p (reg_to_update, PATTERN (next)))
+    {
+      loop_undo_all ();
+      return (0);
+    }
+  loop_undo_all ();
+  /* Now substitute reg_to_update with  reg_to_update + offst_update.  */
+  storage = (char *) oballoc (0);
+  /* Since may be sharing of rtl */
+  copy_dest = copy_rtx (next_dest);
+  copy_src = copy_rtx (next_src);
+  SET_SRC (PATTERN (next)) = copy_src;
+  SET_DEST (PATTERN (next)) = copy_dest;
+  init_undo_buf ();
+  subst_in_insn (next, PATTERN (next), reg_to_update,
+                 gen_rtx (PLUS , GET_MODE (reg_to_update), reg_to_update,
+                          gen_rtx (CONST_INT, 0, offst_update)), 0, 0);
+#ifdef REWRITE_ADDRESS
+  if (GET_CODE (copy_dest) == MEM)
+    {
+      REWRITE_ADDRESS (copy_dest);
+    }
+  if (GET_CODE (copy_src) == MEM)
+    {
+      REWRITE_ADDRESS (copy_src);
+    }
+  else
+    {
+      fmt = GET_RTX_FORMAT (GET_CODE (copy_src));
+      length = GET_RTX_LENGTH (GET_CODE (copy_src));
+      for (i=0; i<length; i++)
+        {
+          if (fmt[i] == 'e' && GET_CODE (XEXP (copy_src, i)) == MEM)
+            {
+              REWRITE_ADDRESS (XEXP (copy_src, i));
+            }
+        }
+    }
+#endif
+  if ((insn_code_number = recog (PATTERN (next), next, 0)) < 0)
+    {
+      loop_undo_all ();
+      SET_DEST (PATTERN (next)) = next_dest;
+      SET_SRC (PATTERN (next)) = next_src;
+      obfree (storage);
+      return (0);
+    }
+  else
+    {
+#ifdef REGISTER_CONSTRAINTS
+      save_code = INSN_CODE (next);
+      INSN_CODE (next) = insn_code_number;
+      insn_extract (next);
+      if (!constrain_operands (insn_code_number, 1))
+	{
+	  loop_undo_all ();
+          SET_DEST (PATTERN (next)) = next_dest;
+          SET_SRC (PATTERN (next)) = next_src;
+	  INSN_CODE (next) = save_code;
+          obfree (storage);
+	  return (0);
+	}
+#endif
+    }
+  return (1);
+}
+#endif
+
 #endif /* INSN_SCHEDULING */
diff -r -u -H -N gcc-2.6.3/toplev.c gcc-i2.6.3/toplev.c
--- gcc-2.6.3/toplev.c	Tue Oct 25 16:09:12 1994
+++ gcc-i2.6.3/toplev.c	Thu Feb 16 11:49:14 1995
@@ -195,7 +195,9 @@
 int combine_dump = 0;
 int sched_dump = 0;
 int local_reg_dump = 0;
+int memory_simplify_dump = 0; /* intel2 */
 int global_reg_dump = 0;
+int loop2_dump = 0; /* intel1 */
 int sched2_dump = 0;
 int jump2_opt_dump = 0;
 int dbr_sched_dump = 0;
@@ -364,6 +366,42 @@
 /* Nonzero enables strength-reduction in loop.c.  */
 
 int flag_strength_reduce = 0;
+/* intel1 my optimization controllers */
+int flag_opt_reg_use = 0;
+int flag_all_mem_givs = 0;
+int flag_reduce_index_givs = 0;
+int flag_peep_spills = 0;
+int flag_loop_after_global = 0;
+int flag_jump_back = 0;
+int flag_copy_prop = 0;
+int flag_lift_stores = 0;
+int flag_runtime_lift_stores = 0;
+int flag_compare_elim = 0;
+int flag_sign_extension_elim = 0;
+int flag_sftwr_pipe = 0;
+int flag_opt_jumps_out = 0;
+int flag_replace_mem = 0;
+int flag_replace_stack_mem = 0;
+int flag_reg_reg_copy_opt = 0;
+int flag_do_offload = 0;
+int flag_opt_reg_stack = 0;
+int flag_correct_cse_mistakes = 0;
+int flag_push_load_into_loop = 0;
+int flag_risc = 0;
+int flag_risc_const = 0;
+int flag_risc_mem_dest = 0;	/* intel2 */
+int flag_replace_reload_regs = 0;
+int flag_recombine = 0;
+int flag_swap_for_agi = 0;
+int flag_no_omit_frame_pointer = 0;
+int flag_no_risc = 0;
+int flag_no_risc_const = 0;
+int flag_no_risc_mem_dest = 0;	/* intel2 */
+int flag_no_recombine = 0;
+int flag_schedule_stack_reg_insns = 0;
+int flag_interleave_stack_non_stack = 0;
+int flag_no_schedule_stack_reg_insns = 0;
+int flag_no_interleave_stack_non_stack = 0;
 
 /* Nonzero enables loop unrolling in unroll.c.  Only loops for which the
    number of iterations can be calculated at compile-time (UNROLL_COMPLETELY,
@@ -553,7 +591,42 @@
   {"inhibit-size-directive", &flag_inhibit_size_directive, 1},
   {"verbose-asm", &flag_verbose_asm, 1},
   {"gnu-linker", &flag_gnu_linker, 1},
-  {"bytecode", &output_bytecode, 1}
+  {"bytecode", &output_bytecode, 1},
+  /* intel1 */
+  {"compare-elim", &flag_compare_elim, 1},
+  {"sign-extension-elim", &flag_sign_extension_elim, 1},
+  {"jump-back", &flag_jump_back, 1},
+  {"loop-after-global", &flag_loop_after_global, 1},
+  {"opt-reg-use", &flag_opt_reg_use, 1},
+  {"all-mem-givs", &flag_all_mem_givs, 1},
+  {"reduce-index-givs", &flag_reduce_index_givs, 1},
+  {"peep-spills", &flag_peep_spills, 1},
+  {"copy-prop", &flag_copy_prop, 1},
+  {"lift-stores", &flag_lift_stores, 1},
+  {"runtime-lift-stores", &flag_runtime_lift_stores, 1},
+  {"do-offload", &flag_do_offload, 1},
+  {"opt-reg-stack", &flag_opt_reg_stack, 1},
+  {"correct-cse-mistakes", &flag_correct_cse_mistakes, 1},
+  {"spl", &flag_sftwr_pipe, 1},
+  {"opt-jumps-out", &flag_opt_jumps_out, 1},
+  {"replace-mem", &flag_replace_mem, 1},
+  {"replace-stack-mem", &flag_replace_stack_mem, 1},
+  {"no-interleave-stack-non-stack", &flag_no_interleave_stack_non_stack, 1},
+  {"interleave-stack-non-stack", &flag_interleave_stack_non_stack, 1},
+  {"no-schedule-stack-reg-insns", &flag_no_schedule_stack_reg_insns, 1},
+  {"schedule-stack-reg-insns", &flag_schedule_stack_reg_insns, 1},
+  {"reg-reg-copy-opt", &flag_reg_reg_copy_opt, 1},
+  {"push-load-into-loop", &flag_push_load_into_loop, 1},
+  {"swap-for-agi", &flag_swap_for_agi, 1},
+  {"no-recombine", &flag_no_recombine, 1},
+  {"recombine", &flag_recombine, 1},
+  {"no-risc", &flag_no_risc, 1},
+  {"risc", &flag_risc, 1},
+  {"no-risc-const", &flag_no_risc_const, 1},
+  {"risc-const", &flag_risc_const, 1},
+  {"replace-reload-regs", &flag_replace_reload_regs, 1},
+  {"no-risc-mem-dest", &flag_no_risc_mem_dest, 1},	/* intel2 */
+  {"risc-mem-dest", &flag_risc_mem_dest, 1},	/* intel2 */
 };
 
 /* Table of language-specific options.  */
@@ -821,6 +894,9 @@
 FILE *sched_dump_file;
 FILE *local_reg_dump_file;
 FILE *global_reg_dump_file;
+FILE *memory_simplify_dump_file; /* intel2 */
+/* intel1 */
+FILE *loop2_dump_file;
 FILE *sched2_dump_file;
 FILE *jump2_opt_dump_file;
 FILE *dbr_sched_dump_file;
@@ -840,6 +916,9 @@
 int sched_time;
 int local_alloc_time;
 int global_alloc_time;
+int memory_simplify_time; /* intel2 */
+/* intel1 */
+int loop2_time;
 int sched2_time;
 int dbr_sched_time;
 int shorten_branch_time;
@@ -987,6 +1066,10 @@
     fflush (local_reg_dump_file);
   if (global_reg_dump_file)
     fflush (global_reg_dump_file);
+  if (memory_simplify_dump_file) /* intel2 */
+      fflush (memory_simplify_dump_file);
+  if (loop2_dump_file) /* intel1 */
+    fflush (loop2_dump_file);
   if (sched2_dump_file)
     fflush (sched2_dump_file);
   if (jump2_opt_dump_file)
@@ -2045,6 +2128,9 @@
   sched_time = 0;
   local_alloc_time = 0;
   global_alloc_time = 0;
+  memory_simplify_time = 0; /* intel2 */
+  /* intel1 */
+  loop2_time = 0;
   sched2_time = 0;
   dbr_sched_time = 0;
   shorten_branch_time = 0;
@@ -2141,6 +2227,17 @@
   if (global_reg_dump)
     global_reg_dump_file = open_dump_file (dump_base_name, ".greg");
 
+  /* intel1 */
+  /* If loop invariants after greg dump desired, open the output file.  */
+  if (loop2_dump)
+  	loop2_dump_file = open_dump_file(dump_base_name, ".l2" );
+
+/* intel2 - begin */
+  /* If memory_simplify dump desired, open the output file.  */
+  if (memory_simplify_dump)
+  	memory_simplify_dump_file=open_dump_file(dump_base_name, ".msim");
+/* intel2 - end */
+
   /* If 2nd scheduling dump desired, open the output file.  */
   if (sched2_dump)
     sched2_dump_file = open_dump_file (dump_base_name, ".sched2");
@@ -2549,6 +2646,12 @@
   if (global_reg_dump)
     fclose (global_reg_dump_file);
 
+  if (memory_simplify_dump)
+    fclose (memory_simplify_dump_file); /* intel2 */
+	
+  if (loop2_dump) /* intel1 */
+    fclose (loop2_dump_file);
+
   if (sched2_dump)
     fclose (sched2_dump_file);
 
@@ -2577,28 +2680,30 @@
     {
       fprintf (stderr,"\n");
       print_time ("parse", parse_time);
-
       if (!output_bytecode)
-	{
-	  print_time ("integration", integration_time);
-	  print_time ("jump", jump_time);
-	  print_time ("cse", cse_time);
-	  print_time ("loop", loop_time);
-	  print_time ("cse2", cse2_time);
-	  print_time ("flow", flow_time);
-	  print_time ("combine", combine_time);
-	  print_time ("sched", sched_time);
-	  print_time ("local-alloc", local_alloc_time);
-	  print_time ("global-alloc", global_alloc_time);
-	  print_time ("sched2", sched2_time);
-	  print_time ("dbranch", dbr_sched_time);
-	  print_time ("shorten-branch", shorten_branch_time);
-	  print_time ("stack-reg", stack_reg_time);
-	  print_time ("final", final_time);
-	  print_time ("varconst", varconst_time);
-	  print_time ("symout", symout_time);
-	  print_time ("dump", dump_time);
-	}
+	  {
+        print_time ("integration", integration_time);
+        print_time ("jump", jump_time);
+        print_time ("cse", cse_time);
+        print_time ("loop", loop_time);
+        print_time ("cse2", cse2_time);
+        print_time ("flow", flow_time);
+        print_time ("combine", combine_time);
+        print_time ("sched", sched_time);
+        print_time ("local-alloc", local_alloc_time);
+        print_time ("global-alloc", global_alloc_time);
+        print_time ("memory-simplify", memory_simplify_time); /* intel2 */
+        /* intel1 */
+        print_time ("loop2", loop2_time);
+        print_time ("sched2", sched2_time);
+        print_time ("dbranch", dbr_sched_time);
+        print_time ("shorten-branch", shorten_branch_time);
+        print_time ("stack-reg", stack_reg_time);
+        print_time ("final", final_time);
+        print_time ("varconst", varconst_time);
+        print_time ("symout", symout_time);
+        print_time ("dump", dump_time);
+      }
     }
 }
 
@@ -3030,7 +3135,7 @@
 	 and write some of the results to dump file.  */
 
       TIMEVAR (flow_time, flow_analysis (insns, max_reg_num (),
-					 flow_dump_file));
+					 flow_dump_file /* intel2: */, 1));
       if (warn_uninitialized)
 	{
 	  uninitialized_vars_warning (DECL_INITIAL (decl));
@@ -3064,6 +3169,31 @@
 	       fflush (combine_dump_file);
 	     });
 
+  /* intel1 */
+#ifdef STACK_REGS
+#ifdef IS_STACK_MODE
+  if (optimize > 0 && flag_opt_reg_stack)
+    {
+      if(stack_reg_dump)
+        {
+          TIMEVAR (dump_time,
+	           {
+		     fprintf (stack_reg_dump_file, "\n;; Function %s\n\n",
+			      IDENTIFIER_POINTER (DECL_NAME (decl)));
+	           });
+        }
+      opt_reg_stack();
+      if(stack_reg_dump)
+        {
+          TIMEVAR (dump_time,
+	           {
+		     print_rtl (stack_reg_dump_file, insns);
+		     fflush (stack_reg_dump_file);
+	           });
+        }
+    }
+#endif
+#endif
   /* Print function header into sched dump now
      because doing the sched analysis makes some of the dump.  */
 
@@ -3131,6 +3261,12 @@
 	       failure = reload (insns, 0, global_reg_dump_file);
 	   });
 
+ /* intel1 */
+  if(optimize > 0 && flag_reg_reg_copy_opt)
+    {
+	  reg_to_reg_copy_opt(insns, global_reg_dump_file);
+    }  
+
   if (global_reg_dump)
     TIMEVAR (dump_time,
 	     {
@@ -3144,6 +3280,70 @@
 
   reload_completed = 1;
 
+#ifdef STACK_REGS
+  /* intel1 */
+  if (optimize > 0 && flag_opt_reg_stack)
+    {
+      TIMEVAR (stack_reg_time, float_to_int_cmp (insns, 0));
+    }
+#endif
+
+  /* intel1 */
+  if (loop2_dump)
+    TIMEVAR (dump_time,
+	     {
+	       fprintf (loop2_dump_file, "\n;; Function %s\n\n",
+			IDENTIFIER_POINTER (DECL_NAME (decl)));
+	     });
+
+  if(optimize>0 && flag_loop_after_global) 
+  {
+      TIMEVAR (loop2_time,
+	       {
+	         /* intel2 - begin */
+	         if (flag_replace_reload_regs)
+	           replace_reload_registers (get_insns(),
+				             loop2_dump ? loop2_dump_file : 0);
+	         /* intel2 - end */
+                 loop_after_global(get_insns(),loop2_dump ? loop2_dump_file : 0); 
+	       });
+  }
+  if (optimize>0 && flag_peep_spills)
+    {
+     TIMEVAR (loop2_time,
+	      {
+	      peep_spills(get_insns(),loop2_dump ? loop2_dump_file : 0); 
+	      });
+    }
+    
+  /* Dump rtl code after loop2 opt, if we are doing that.  */
+
+  if (loop2_dump && flag_loop_after_global)
+    TIMEVAR (dump_time,
+	     {
+	       print_rtl (loop2_dump_file, insns);
+	       fflush (loop2_dump_file);
+	     });
+
+/* intel2 - begin */
+  if (optimize>0 && flag_risc)
+    {
+      if (memory_simplify_dump)
+        TIMEVAR (dump_time,
+	         fprintf (memory_simplify_dump_file, "\n;; Function %s\n\n",
+		          IDENTIFIER_POINTER (DECL_NAME (decl))));
+    
+  	    TIMEVAR (memory_simplify_time,
+	       memory_simplify (memory_simplify_dump ? memory_simplify_dump_file : 0,
+							    insns));
+      if (memory_simplify_dump)
+        TIMEVAR (dump_time,
+	         {
+	           print_rtl (memory_simplify_dump_file, insns);
+	           fflush (memory_simplify_dump_file);
+	         });
+    }
+/* intel2 - end */
   /* On some machines, the prologue and epilogue code, or parts thereof,
      can be represented as RTL.  Doing so lets us schedule insns between
      it and the rest of the code and also allows delayed branch
@@ -3175,6 +3375,13 @@
 		 });
     }
 
+  /* intel2 - begin */
+  /* Combine those riscified insns that were not used for scheduling */
+  if (flag_risc && flag_recombine)
+    combine_unscheded (get_insns (),max_reg_num ());
+  /* intel2 - end */
+
+
 #ifdef LEAF_REGISTERS
   leaf_function = 0;
   if (optimize > 0 && only_leaf_regs_used () && leaf_function_p ())
@@ -3235,6 +3442,11 @@
 	     });
 
 #ifdef STACK_REGS
+  /* intel1 */
+  if (optimize > 0 && flag_opt_reg_stack)
+    {
+      TIMEVAR (stack_reg_time, float_to_int_cmp (insns));
+    }
   TIMEVAR (stack_reg_time, reg_to_stack (insns, stack_reg_dump_file));
   if (stack_reg_dump)
     {
@@ -3246,6 +3458,13 @@
 		 fflush (stack_reg_dump_file);
 	       });
     }
+/* intel1 spl */
+#ifdef STORE_NOT_SET_CC0
+  if(flag_sftwr_pipe)
+    {
+      do_spl(insns);
+    }
+#endif
 #endif
 
   /* Now turn the rtl into assembler code.  */
@@ -3492,10 +3711,12 @@
  		    dbr_sched_dump = 1;
  		    flow_dump = 1;
  		    global_reg_dump = 1;
+		    memory_simplify_dump = 1; /* intel2 */
  		    jump_opt_dump = 1;
  		    jump2_opt_dump = 1;
  		    local_reg_dump = 1;
  		    loop_dump = 1;
+ 		    loop2_dump = 1; /* intel1 */
  		    rtl_dump = 1;
  		    cse_dump = 1, cse2_dump = 1;
  		    sched_dump = 1;
@@ -3517,6 +3738,11 @@
 		  case 'g':
 		    global_reg_dump = 1;
 		    break;
+		  /* intel2 - begin */
+		  case 'b':
+		    memory_simplify_dump = 1;
+		    break;
+		  /* intel2 - end */
 		  case 'j':
 		    jump_opt_dump = 1;
 		    break;
@@ -3529,6 +3755,10 @@
 		  case 'L':
 		    loop_dump = 1;
 		    break;
+		    /* intel1 */
+		  case 'A':
+		    loop2_dump = 1;
+		    break;
 		  case 'm':
 		    flag_print_mem = 1;
 		    break;
@@ -3932,6 +4162,9 @@
       fprintf (stderr, "%s version %s", language_string, version_string);
 #ifdef TARGET_VERSION
       TARGET_VERSION;
+#endif
+#ifdef SUB_TARGET_VERSION
+      SUB_TARGET_VERSION;
 #endif
 #ifdef __GNUC__
 #ifndef __VERSION__
diff -r -u -H -N gcc-2.6.3/unroll.c gcc-i2.6.3/unroll.c
--- gcc-2.6.3/unroll.c	Thu Oct 20 16:28:42 1994
+++ gcc-i2.6.3/unroll.c	Wed Feb 15 22:47:30 1995
@@ -155,6 +155,9 @@
 #include <stdio.h>
 #include "loop.h"
 
+/* intel1 */
+extern FILE *loop_dump_stream;
+
 /* This controls which loops are unrolled, and by how much we unroll
    them.  */
 
@@ -1688,6 +1691,42 @@
 	  else
 	    {
 	      pattern = copy_rtx_and_substitute (pattern, map);
+/* intel1 since a DEST_ADDR giv may be only a part of an address
+   then just substituting reg+const for reg may result in an
+   invalid insn - we check for that and try to make it good */
+#if REDUCE_INDEX || SAVE_ON_REGS
+              if(GET_CODE(PATTERN(insn))==SET)
+	        {
+	          int dummy;
+	          rtx try_to_make_good(); /* see loop.c */
+	          if(recog(pattern,insn,&dummy)==-1)
+	            {
+	              try_to_make_good(SET_SRC(pattern));
+	              try_to_make_good(SET_DEST(pattern));
+  	              if(recog(pattern,insn,&dummy)==-1)
+  	              {
+  	                fprintf(stderr,"bad pattern in insn not better:\n");
+  	                debug_rtx(insn);
+  	                abort();
+  	              }
+	            }
+	        }
+#endif
+	      /* intel1 Don't want to be reusing STACK_MODE registers
+	         since that inhibits scheduling opportunities */
+#ifdef STACK_REGS
+#ifdef IS_STACK_MODE
+#ifdef ONLY_STACK_REG_REORDER
+            if (GET_CODE (pattern) == SET && GET_CODE (SET_DEST (pattern)) == REG
+                && IS_STACK_MODE (GET_MODE (SET_DEST (pattern))))
+              {
+	        tem = gen_reg_rtx (GET_MODE (SET_DEST (pattern)));
+	        map->reg_map[REGNO (SET_DEST (PATTERN (insn)))] = tem;
+	        SET_DEST (pattern) = tem;
+              }
+#endif
+#endif
+#endif
 	      copy = emit_insn (pattern);
 	    }
 	  REG_NOTES (copy) = initial_reg_note_copy (REG_NOTES (insn), map);
diff -r -u -H -N gcc-2.6.3/varasm.c gcc-i2.6.3/varasm.c
--- gcc-2.6.3/varasm.c	Mon Nov 21 22:22:11 1994
+++ gcc-i2.6.3/varasm.c	Wed Feb 15 22:47:31 1995
@@ -75,13 +75,13 @@
 
 /* Number for making the label on the next
    constant that is stored in memory.  */
-
-int const_labelno;
+/* intel1 */
+static int const_labelno = 0;
 
 /* Number for making the label on the next
    static variable internal to a function.  */
-
-int var_labelno;
+/* intel1 */
+static int var_labelno = 0;
 
 /* Carry information from ASM_DECLARE_OBJECT_NAME
    to ASM_FINISH_DECLARE_OBJECT.  */
@@ -1083,12 +1083,23 @@
 	    else
 	      {
 #ifdef ASM_OUTPUT_ALIGNED_COMMON
-		ASM_OUTPUT_ALIGNED_COMMON (asm_out_file, name, size,
-					   DECL_ALIGN (decl));
+/* intel1 */
+#ifdef ALIGN_DFmode
+              if (DECL_MODE (decl) == DFmode
+                  && DECL_ALIGN (decl) 
+                    == (GET_MODE_SIZE (SFmode) * BITS_PER_UNIT))
+                {
+	      ASM_OUTPUT_ALIGNED_COMMON (asm_out_file, name, size, 
+	      GET_MODE_SIZE (DFmode) * BITS_PER_UNIT);
+                }
+              else
+#endif
+	      ASM_OUTPUT_ALIGNED_COMMON (asm_out_file, name, size,
+	 	 		         DECL_ALIGN (decl));
 #else
-		ASM_OUTPUT_COMMON (asm_out_file, name, size, rounded);
+	      ASM_OUTPUT_COMMON (asm_out_file, name, size, rounded);
 #endif
-	      }
+		}
 	}
       else
 	{
@@ -1104,12 +1115,23 @@
 	    else
 	      {
 #ifdef ASM_OUTPUT_ALIGNED_LOCAL
-		ASM_OUTPUT_ALIGNED_LOCAL (asm_out_file, name, size,
-					  DECL_ALIGN (decl));
+/* intel1 */
+#ifdef ALIGN_DFmode
+            if (DECL_MODE (decl) == DFmode
+                && DECL_ALIGN (decl) 
+                  == (GET_MODE_SIZE (SFmode) * BITS_PER_UNIT))
+              {
+	    ASM_OUTPUT_ALIGNED_COMMON (asm_out_file, name, size, 
+	    GET_MODE_SIZE (DFmode) * BITS_PER_UNIT);
+              }
+            else
+#endif
+	    ASM_OUTPUT_ALIGNED_LOCAL (asm_out_file, name, size,
+				      DECL_ALIGN (decl));
 #else
-		ASM_OUTPUT_LOCAL (asm_out_file, name, size, rounded);
+	    ASM_OUTPUT_LOCAL (asm_out_file, name, size, rounded);
 #endif
-	      }
+		}
 	}
       goto finish;
     }
@@ -1251,6 +1273,14 @@
      from it in get_pointer_alignment.  */
   DECL_ALIGN (decl) = align;
 
+/* intel1 */
+#ifdef ALIGN_DFmode
+    if (DECL_MODE (decl) == DFmode
+        && DECL_ALIGN (decl) == (GET_MODE_SIZE (SFmode) * BITS_PER_UNIT))
+      {
+        align = GET_MODE_SIZE (DFmode) * BITS_PER_UNIT;
+      }
+#endif
   if (align > BITS_PER_UNIT)
     {
       if (output_bytecode)
@@ -3068,6 +3098,10 @@
       align = (mode == VOIDmode) ? UNITS_PER_WORD : GET_MODE_SIZE (mode);
       if (align > BIGGEST_ALIGNMENT / BITS_PER_UNIT)
 	align = BIGGEST_ALIGNMENT / BITS_PER_UNIT;
+      /* intel1 */
+#ifdef ALIGN_DFmode
+      align = (mode == DFmode) ? GET_MODE_SIZE (mode) : align;
+#endif
 
       pool_offset += align - 1;
       pool_offset &= ~ (align - 1);
diff -r -u -H -N gcc-2.6.3/version.c gcc-i2.6.3/version.c
--- gcc-2.6.3/version.c	Mon Nov 14 18:12:47 1994
+++ gcc-i2.6.3/version.c	Wed Feb 15 23:55:26 1995
@@ -1 +1 @@
-char *version_string = "2.6.3";
+char *version_string = "i2.6.3";
